projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0dc0e846 MD |
1 | /* |
| 2 | * Palm Treo 680 configuration file | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com> | |
| 5 | * | |
| 6 | * This file is released under the terms of GPL v2 and any later version. | |
| 7 | * See the file COPYING in the root directory of the source tree for details. | |
| 8 | * | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 14 | /* | |
| 15 | * High Level Board Configuration Options | |
| 16 | */ | |
| 17 | #define CONFIG_CPU_PXA27X | |
| 18 | #define CONFIG_PALMTREO680 | |
| 19 | #define CONFIG_MACH_TYPE MACH_TYPE_TREO680 | |
| 20 | ||
| 21 | #define CONFIG_SYS_MALLOC_LEN (4096*1024) | |
| 22 | ||
| 23 | #define CONFIG_LZMA | |
| 24 | ||
| 25 | /* | |
| 26 | * Serial Console Configuration | |
| 27 | */ | |
| 28 | #define CONFIG_PXA_SERIAL | |
| 29 | #define CONFIG_FFUART 1 | |
| 30 | #define CONFIG_BAUDRATE 9600 | |
| 31 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 32 | #define CONFIG_CONS_INDEX 3 | |
| 33 | ||
| 34 | /* we have nand (although technically nand *is* flash...) */ | |
| 35 | #define CONFIG_SYS_NO_FLASH | |
| 36 | ||
| 37 | #define CONFIG_LCD | |
| 38 | /* #define CONFIG_KEYBOARD */ /* TODO */ | |
| 39 | ||
| 40 | /* | |
| 41 | * Bootloader Components Configuration | |
| 42 | */ | |
| 0dc0e846 MD |
43 | #define CONFIG_CMD_ENV |
| 44 | #define CONFIG_CMD_MMC | |
| 45 | #define CONFIG_CMD_NAND | |
| 46 | ||
| 47 | #define CONFIG_CMDLINE_TAG | |
| 48 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 49 | ||
| 50 | /* | |
| 51 | * MMC Card Configuration | |
| 52 | */ | |
| 53 | #ifdef CONFIG_CMD_MMC | |
| 54 | #define CONFIG_MMC | |
| 55 | #define CONFIG_GENERIC_MMC | |
| 56 | #define CONFIG_PXA_MMC_GENERIC | |
| 57 | ||
| 58 | #define CONFIG_CMD_FAT | |
| 59 | #define CONFIG_CMD_EXT2 | |
| 60 | #define CONFIG_DOS_PARTITION | |
| 61 | #endif | |
| 62 | ||
| 63 | /* | |
| 64 | * LCD | |
| 65 | */ | |
| 66 | #ifdef CONFIG_LCD | |
| 67 | #define CONFIG_PXA_LCD | |
| 68 | #define CONFIG_ACX544AKN | |
| 69 | #define CONFIG_LCD_LOGO | |
| 70 | #define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */ | |
| 71 | #define LCD_BPP LCD_COLOR16 | |
| 72 | #define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */ | |
| 73 | #define CONFIG_CMD_BMP | |
| 74 | #define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */ | |
| 75 | #define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */ | |
| 76 | #define CONFIG_VIDEO_BMP_GZIP | |
| 77 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) | |
| 78 | ||
| 79 | #endif | |
| 80 | ||
| 81 | /* | |
| 82 | * KGDB | |
| 83 | */ | |
| 84 | #ifdef CONFIG_CMD_KGDB | |
| 85 | #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ | |
| 0dc0e846 MD |
86 | #endif |
| 87 | ||
| 88 | /* | |
| 89 | * HUSH Shell Configuration | |
| 90 | */ | |
| 91 | #define CONFIG_SYS_HUSH_PARSER 1 | |
| 92 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 93 | ||
| 94 | #define CONFIG_SYS_LONGHELP | |
| 181bd9dc | 95 | #undef CONFIG_SYS_PROMPT |
| 0dc0e846 MD |
96 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 97 | #define CONFIG_SYS_PROMPT "$ " | |
| 98 | #else | |
| 0dc0e846 MD |
99 | #endif |
| 100 | #define CONFIG_SYS_CBSIZE 256 | |
| 101 | #define CONFIG_SYS_PBSIZE \ | |
| 102 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 103 | #define CONFIG_SYS_MAXARGS 16 | |
| 104 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 105 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
| 106 | ||
| 107 | /* | |
| 108 | * Clock Configuration | |
| 109 | */ | |
| 0dc0e846 MD |
110 | #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ |
| 111 | ||
| 112 | /* | |
| 113 | * Stack sizes | |
| 114 | */ | |
| 115 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
| 116 | #ifdef CONFIG_USE_IRQ | |
| 117 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
| 118 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
| 119 | #endif | |
| 120 | ||
| 121 | /* | |
| 122 | * DRAM Map | |
| 123 | */ | |
| 124 | #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ | |
| 125 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
| 126 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
| 127 | ||
| 128 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 | |
| 129 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ | |
| 130 | ||
| 131 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | |
| 132 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
| 133 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE | |
| 134 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
| 135 | ||
| 136 | /* | |
| 137 | * GPIO settings | |
| 138 | */ | |
| 139 | #define CONFIG_SYS_GAFR0_L_VAL 0x0E000000 | |
| 140 | #define CONFIG_SYS_GAFR0_U_VAL 0xA500001A | |
| 141 | #define CONFIG_SYS_GAFR1_L_VAL 0x60000002 | |
| 142 | #define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959 | |
| 143 | #define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA | |
| 144 | #define CONFIG_SYS_GAFR2_U_VAL 0x41440F08 | |
| 145 | #define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF | |
| 146 | #define CONFIG_SYS_GAFR3_U_VAL 0x00001401 | |
| 147 | #define CONFIG_SYS_GPCR0_VAL 0x1FF80400 | |
| 148 | #define CONFIG_SYS_GPCR1_VAL 0x03003FC1 | |
| 149 | #define CONFIG_SYS_GPCR2_VAL 0x01C1E000 | |
| 150 | #define CONFIG_SYS_GPCR3_VAL 0x01C1E000 | |
| 151 | #define CONFIG_SYS_GPDR0_VAL 0xCFF90400 | |
| 152 | #define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1 | |
| 153 | #define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF | |
| 154 | #define CONFIG_SYS_GPDR3_VAL 0x0069FF81 | |
| 155 | #define CONFIG_SYS_GPSR0_VAL 0x02000018 | |
| 156 | #define CONFIG_SYS_GPSR1_VAL 0x00000000 | |
| 157 | #define CONFIG_SYS_GPSR2_VAL 0x000C0000 | |
| 158 | #define CONFIG_SYS_GPSR3_VAL 0x00080000 | |
| 159 | ||
| 160 | #define CONFIG_SYS_PSSR_VAL 0x30 | |
| 161 | ||
| 162 | /* | |
| 163 | * Clock settings | |
| 164 | */ | |
| 165 | #define CONFIG_SYS_CKEN 0x01ffffff | |
| 166 | #define CONFIG_SYS_CCCR 0x02000210 | |
| 167 | ||
| 168 | /* | |
| 169 | * Memory settings | |
| 170 | */ | |
| 171 | #define CONFIG_SYS_MSC0_VAL 0x7ff844c8 | |
| 172 | #define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 | |
| 173 | #define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 | |
| 174 | #define CONFIG_SYS_MDCNFG_VAL 0x0B880acd | |
| 175 | #define CONFIG_SYS_MDREFR_VAL 0x201fa031 | |
| 176 | #define CONFIG_SYS_MDMRS_VAL 0x00320032 | |
| 177 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 | |
| 178 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 | |
| 179 | #define CONFIG_SYS_MECR_VAL 0x00000003 | |
| 180 | #define CONFIG_SYS_MCMEM0_VAL 0x0001c391 | |
| 181 | #define CONFIG_SYS_MCMEM1_VAL 0x0001c391 | |
| 182 | #define CONFIG_SYS_MCATT0_VAL 0x0001c391 | |
| 183 | #define CONFIG_SYS_MCATT1_VAL 0x0001c391 | |
| 184 | #define CONFIG_SYS_MCIO0_VAL 0x00014611 | |
| 185 | #define CONFIG_SYS_MCIO1_VAL 0x0001c391 | |
| 186 | ||
| 187 | /* | |
| 188 | * USB | |
| 189 | */ | |
| 190 | #define CONFIG_USB_DEVICE | |
| 191 | #define CONFIG_USB_TTY | |
| 192 | #define CONFIG_USB_DEV_PULLUP_GPIO 114 | |
| 193 | ||
| 194 | /* | |
| 195 | * SPL | |
| 196 | */ | |
| 0dc0e846 MD |
197 | #define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */ |
| 198 | #define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */ | |
| 199 | #define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */ | |
| 200 | #define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */ | |
| 201 | #define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */ | |
| 202 | ||
| 203 | /* | |
| 204 | * NAND | |
| 205 | */ | |
| 206 | #define CONFIG_NAND_DOCG4 | |
| 207 | #define CONFIG_SYS_NAND_SELF_INIT | |
| 208 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */ | |
| 209 | #define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */ | |
| 210 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x200 | |
| 211 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 | |
| 212 | #define CONFIG_BITREVERSE /* needed by docg4 driver */ | |
| 213 | #define CONFIG_BCH /* needed by docg4 driver */ | |
| 214 | ||
| 215 | /* | |
| 216 | * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It | |
| 217 | * will be rounded up to the next 64k boundary (the spl flash block size), so it | |
| 218 | * does not have to be exact, but you must ensure that it is not less than the | |
| 219 | * actual image size, or it may fail to boot (bricked phone)! | |
| 220 | * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.) | |
| 221 | */ | |
| 222 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */ | |
| 223 | ||
| 224 | /* | |
| 225 | * This is the byte offset into the flash at which the concatenated spl + u-boot | |
| 226 | * image is placed. It must be at the start of a block (256k boundary). Blocks | |
| 227 | * 0 - 5 are write-protected, so we start at block 6. | |
| 228 | */ | |
| 229 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */ | |
| 230 | ||
| 231 | /* DRAM address to which u-boot proper is loaded (before it relocates itself) */ | |
| 232 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000 | |
| 233 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
| 234 | ||
| 235 | /* passed to linker by Makefile as arg to -Ttext option */ | |
| 236 | #define CONFIG_SYS_TEXT_BASE 0xa0000000 | |
| 237 | ||
| 238 | #define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */ | |
| 239 | ||
| 240 | /* | |
| 241 | * environment | |
| 242 | */ | |
| 243 | #define CONFIG_ENV_IS_NOWHERE | |
| 244 | #define CONFIG_BUILD_ENVCRC | |
| 245 | #define CONFIG_ENV_SIZE 0x200 | |
| 246 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 247 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 248 | "stdin=usbtty\0" \ | |
| 249 | "stdout=usbtty\0" \ | |
| 250 | "stderr=usbtty" | |
| 251 | #define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \ | |
| 252 | ip=192.168.11.102:::255.255.255.0:treo:usb0" | |
| 253 | #define CONFIG_BOOTDELAY 3 | |
| 254 | ||
| 255 | #if 0 /* example: try 2nd mmc partition, then nand */ | |
| 256 | #define CONFIG_BOOTCOMMAND \ | |
| 257 | "mmc rescan; " \ | |
| 258 | "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \ | |
| 259 | "bootm 0xa1000000; " \ | |
| 260 | "elif nand read 0xa1000000 0x280000 0x240000; then " \ | |
| 261 | "bootm 0xa1000000; " \ | |
| 262 | "fi; " | |
| 263 | #endif | |
| 264 | ||
| 265 | /* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */ | |
| 266 | #define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000 | |
| 267 | ||
| 268 | #define CONFIG_SYS_DCACHE_OFF | |
| 269 | #define CONFIG_SYS_ICACHE_OFF | |
| 270 | ||
| 271 | #endif /* __CONFIG_H */ |