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Commit | Line | Data |
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265817c7 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
265817c7 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * This file contains the configuration parameters for the dbau1x00 board. | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
265817c7 | 15 | #define CONFIG_PB1X00 1 |
8bde63eb | 16 | #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ |
265817c7 WD |
17 | |
18 | #ifdef CONFIG_PB1000 | |
8bde63eb | 19 | #define CONFIG_SOC_AU1000 1 |
265817c7 WD |
20 | #else |
21 | #ifdef CONFIG_PB1100 | |
8bde63eb | 22 | #define CONFIG_SOC_AU1100 1 |
265817c7 WD |
23 | #else |
24 | #ifdef CONFIG_PB1500 | |
8bde63eb | 25 | #define CONFIG_SOC_AU1500 1 |
265817c7 WD |
26 | #else |
27 | #error "No valid board set" | |
28 | #endif | |
29 | #endif | |
30 | #endif | |
31 | ||
265817c7 | 32 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
265817c7 WD |
33 | |
34 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
fe126d8b WD |
35 | "addmisc=setenv bootargs ${bootargs} " \ |
36 | "console=ttyS0,${baudrate} " \ | |
265817c7 WD |
37 | "panic=1\0" \ |
38 | "bootfile=/vmlinux.img\0" \ | |
fe126d8b | 39 | "load=tftp 80500000 ${u-boot}\0" \ |
265817c7 WD |
40 | "" |
41 | /* Boot from NFS root */ | |
fe126d8b | 42 | #define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm" |
265817c7 WD |
43 | |
44 | /* | |
45 | * Miscellaneous configurable options | |
46 | */ | |
6d0f6bcf | 47 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
265817c7 | 48 | |
6d0f6bcf | 49 | #define CONFIG_SYS_MALLOC_LEN 128*1024 |
265817c7 | 50 | |
6d0f6bcf | 51 | #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 |
265817c7 | 52 | |
6d0f6bcf | 53 | #define CONFIG_SYS_MIPS_TIMER_FREQ 396000000 |
a55d4817 | 54 | |
6d0f6bcf | 55 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
265817c7 | 56 | |
6d0f6bcf | 57 | #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ |
265817c7 | 58 | |
6d0f6bcf JCPV |
59 | #define CONFIG_SYS_MEMTEST_START 0x80100000 |
60 | #undef CONFIG_SYS_MEMTEST_START | |
61 | #define CONFIG_SYS_MEMTEST_START 0x80200000 | |
62 | #define CONFIG_SYS_MEMTEST_END 0x83800000 | |
265817c7 WD |
63 | |
64 | /*----------------------------------------------------------------------- | |
65 | * FLASH and environment organization | |
66 | */ | |
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
68 | #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ | |
265817c7 WD |
69 | |
70 | #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ | |
71 | #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ | |
72 | ||
14d0a02a | 73 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 74 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) |
265817c7 | 75 | |
6d0f6bcf | 76 | #define CONFIG_SYS_INIT_SP_OFFSET 0x4000000 |
265817c7 WD |
77 | |
78 | /* We boot from this flash, selected with dip switch */ | |
6d0f6bcf | 79 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 |
265817c7 WD |
80 | |
81 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
83 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
265817c7 | 84 | |
265817c7 | 85 | /* Address and size of Primary Environment Sector */ |
0e8d1586 JCPV |
86 | #define CONFIG_ENV_ADDR 0xB0030000 |
87 | #define CONFIG_ENV_SIZE 0x10000 | |
265817c7 WD |
88 | |
89 | #define CONFIG_FLASH_16BIT | |
90 | ||
91 | #define CONFIG_NR_DRAM_BANKS 2 | |
92 | ||
265817c7 WD |
93 | #define CONFIG_MEMSIZE_IN_BYTES |
94 | ||
265817c7 WD |
95 | /*---USB -------------------------------------------*/ |
96 | #if 0 | |
97 | #define CONFIG_USB_OHCI | |
265817c7 WD |
98 | #endif |
99 | ||
100 | /*---ATA PCMCIA ------------------------------------*/ | |
101 | #if 0 | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ |
103 | #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 | |
265817c7 WD |
104 | #define CONFIG_PCMCIA_SLOT_A |
105 | ||
106 | #define CONFIG_ATAPI 1 | |
265817c7 WD |
107 | |
108 | /* We run CF in "true ide" mode or a harddrive via pcmcia */ | |
109 | #define CONFIG_IDE_PCMCIA 1 | |
110 | ||
111 | /* We only support one slot for now */ | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
113 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
265817c7 | 114 | |
265817c7 WD |
115 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
116 | ||
6d0f6bcf | 117 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
265817c7 | 118 | |
6d0f6bcf | 119 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
265817c7 WD |
120 | |
121 | /* Offset for data I/O */ | |
6d0f6bcf | 122 | #define CONFIG_SYS_ATA_DATA_OFFSET 8 |
265817c7 WD |
123 | |
124 | /* Offset for normal register accesses */ | |
6d0f6bcf | 125 | #define CONFIG_SYS_ATA_REG_OFFSET 0 |
265817c7 WD |
126 | |
127 | /* Offset for alternate registers */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
265817c7 WD |
129 | |
130 | #endif | |
265817c7 | 131 | |
079a136c JL |
132 | /* |
133 | * BOOTP options | |
134 | */ | |
135 | #define CONFIG_BOOTP_BOOTFILESIZE | |
136 | #define CONFIG_BOOTP_BOOTPATH | |
137 | #define CONFIG_BOOTP_GATEWAY | |
138 | #define CONFIG_BOOTP_HOSTNAME | |
139 | ||
26a34560 JL |
140 | /* |
141 | * Command line configuration. | |
142 | */ | |
26a34560 | 143 | |
265817c7 | 144 | #endif /* __CONFIG_H */ |