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a4c8d138 SR |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************ | |
25 | * pcs440ep.h - configuration for PCS440EP board | |
26 | ***********************************************************************/ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
388b82fd BS |
30 | |
31 | /* new uImage format support */ | |
32 | #define CONFIG_FIT 1 | |
33 | #define CONFIG_OF_LIBFDT 1 | |
34 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
35 | ||
a4c8d138 SR |
36 | /*----------------------------------------------------------------------- |
37 | * High Level Configuration Options | |
38 | *----------------------------------------------------------------------*/ | |
39 | #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ | |
40 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ | |
efa35cf1 | 41 | #define CONFIG_440 1 /* ... PPC440 family */ |
a4c8d138 SR |
42 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
43 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
44 | ||
45 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
46 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
47 | ||
48 | /*----------------------------------------------------------------------- | |
49 | * Base addresses -- Note these are effective addresses where the | |
50 | * actual resources get mapped (not physical addresses) | |
51 | *----------------------------------------------------------------------*/ | |
e461a241 | 52 | #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ |
a4c8d138 SR |
53 | #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
54 | #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) | |
55 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
56 | #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ | |
57 | #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
58 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
59 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
60 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
61 | ||
62 | /*Don't change either of these*/ | |
63 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ | |
64 | #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ | |
65 | /*Don't change either of these*/ | |
66 | ||
67 | #define CFG_USB_DEVICE 0x50000000 | |
68 | #define CFG_BOOT_BASE_ADDR 0xf0000000 | |
69 | ||
70 | /*----------------------------------------------------------------------- | |
71 | * Initial RAM & stack pointer (placed in SDRAM) | |
72 | *----------------------------------------------------------------------*/ | |
887e2ec9 | 73 | #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
a4c8d138 | 74 | #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ |
28d77d96 | 75 | #define CFG_INIT_RAM_END (4 << 10) |
a4c8d138 SR |
76 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ |
77 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
78 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
79 | ||
80 | /*----------------------------------------------------------------------- | |
81 | * Serial Port | |
82 | *----------------------------------------------------------------------*/ | |
83 | #undef CFG_EXT_SERIAL_CLOCK /* no external clk used */ | |
84 | #define CONFIG_BAUDRATE 115200 | |
85 | #define CONFIG_SERIAL_MULTI 1 | |
86 | /*define this if you want console on UART1*/ | |
87 | #undef CONFIG_UART1_CONSOLE | |
88 | ||
89 | #define CFG_BAUDRATE_TABLE \ | |
90 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
91 | ||
92 | /*----------------------------------------------------------------------- | |
93 | * Environment | |
94 | *----------------------------------------------------------------------*/ | |
5a1aceb0 | 95 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
a4c8d138 SR |
96 | |
97 | /*----------------------------------------------------------------------- | |
98 | * FLASH related | |
99 | *----------------------------------------------------------------------*/ | |
100 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
101 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
102 | ||
103 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
104 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
105 | ||
106 | #define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ | |
107 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
108 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
109 | ||
110 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
111 | ||
5a1aceb0 | 112 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
113 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
114 | #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) | |
115 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
566a494f HS |
116 | |
117 | #define CONFIG_ENV_OVERWRITE 1 | |
a4c8d138 SR |
118 | |
119 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
120 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
121 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 122 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
a4c8d138 | 123 | |
566a494f HS |
124 | #define ENV_NAME_REVLEV "revision_level" |
125 | #define ENV_NAME_SOLDER "solder_switch" | |
126 | #define ENV_NAME_DIP "dip" | |
127 | ||
a4c8d138 SR |
128 | /*----------------------------------------------------------------------- |
129 | * DDR SDRAM | |
130 | *----------------------------------------------------------------------*/ | |
131 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
132 | #undef CONFIG_DDR_ECC /* don't use ECC */ | |
ed4633c9 | 133 | #define SPD_EEPROM_ADDRESS {0x50} |
566a494f | 134 | #define CONFIG_PROG_SDRAM_TLB 1 |
a4c8d138 SR |
135 | |
136 | /*----------------------------------------------------------------------- | |
137 | * I2C | |
138 | *----------------------------------------------------------------------*/ | |
139 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
140 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
ed4633c9 | 141 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ |
a4c8d138 SR |
142 | #define CFG_I2C_SLAVE 0x7F |
143 | ||
ed4633c9 | 144 | #define CFG_I2C_EEPROM_ADDR (0xa4>>1) |
a4c8d138 | 145 | #define CFG_I2C_EEPROM_ADDR_LEN 1 |
a4c8d138 SR |
146 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 |
147 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
148 | ||
149 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 150 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
a4c8d138 SR |
151 | "echo" |
152 | ||
153 | #undef CONFIG_BOOTARGS | |
154 | ||
155 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
156 | "netdev=eth0\0" \ | |
157 | "hostname=pcs440ep\0" \ | |
566a494f HS |
158 | "use_eeprom_ethaddr=default\0" \ |
159 | "cs_test=off\0" \ | |
a4c8d138 SR |
160 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
161 | "nfsroot=${serverip}:${rootpath}\0" \ | |
162 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
163 | "addip=setenv bootargs ${bootargs} " \ | |
164 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
165 | ":${hostname}:${netdev}:off panic=1\0" \ | |
166 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
167 | "flash_nfs=run nfsargs addip addtty;" \ | |
168 | "bootm ${kernel_addr}\0" \ | |
169 | "flash_self=run ramargs addip addtty;" \ | |
170 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
171 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
172 | "bootm\0" \ | |
173 | "rootpath=/opt/eldk/ppc_4xx\0" \ | |
174 | "bootfile=/tftpboot/pcs440ep/uImage\0" \ | |
e461a241 WD |
175 | "kernel_addr=FFF00000\0" \ |
176 | "ramdisk_addr=FFF00000\0" \ | |
a4c8d138 | 177 | "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \ |
e461a241 WD |
178 | "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ |
179 | "cp.b 100000 FFFA0000 60000\0" \ | |
d8ab58b2 | 180 | "upd=run load update\0" \ |
a4c8d138 SR |
181 | "" |
182 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
183 | ||
184 | #if 0 | |
185 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
186 | #else | |
187 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
188 | #endif | |
189 | ||
566a494f HS |
190 | /* check U-Boot image with SHA1 sum */ |
191 | #define CONFIG_SHA1_CHECK_UB_IMG 1 | |
192 | #define CONFIG_SHA1_START CFG_MONITOR_BASE | |
193 | #define CONFIG_SHA1_LEN CFG_MONITOR_LEN | |
194 | ||
195 | /*----------------------------------------------------------------------- | |
196 | * Definitions for status LED | |
197 | */ | |
198 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
199 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
200 | ||
96e1d75b | 201 | #define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ |
566a494f HS |
202 | #define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ |
203 | #define STATUS_LED_STATE STATUS_LED_OFF | |
96e1d75b | 204 | #define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ |
566a494f HS |
205 | #define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ |
206 | #define STATUS_LED_STATE1 STATUS_LED_ON | |
96e1d75b | 207 | #define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ |
566a494f HS |
208 | #define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ |
209 | #define STATUS_LED_STATE2 STATUS_LED_OFF | |
96e1d75b | 210 | #define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ |
566a494f HS |
211 | #define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ |
212 | #define STATUS_LED_STATE3 STATUS_LED_OFF | |
213 | ||
214 | #define CONFIG_SHOW_BOOT_PROGRESS 1 | |
215 | ||
a4c8d138 SR |
216 | #define CONFIG_BAUDRATE 115200 |
217 | ||
218 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
219 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
220 | ||
221 | #define CONFIG_MII 1 /* MII PHY management */ | |
222 | #define CONFIG_NET_MULTI 1 /* required for netconsole */ | |
223 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
224 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
225 | #define CONFIG_PHY1_ADDR 2 | |
226 | ||
227 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
228 | ||
229 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
230 | ||
231 | /* Partitions */ | |
232 | #define CONFIG_MAC_PARTITION | |
233 | #define CONFIG_DOS_PARTITION | |
234 | #define CONFIG_ISO_PARTITION | |
235 | ||
236 | #ifdef CONFIG_440EP | |
237 | /* USB */ | |
238 | #define CONFIG_USB_OHCI | |
239 | #define CONFIG_USB_STORAGE | |
240 | ||
241 | /*Comment this out to enable USB 1.1 device*/ | |
242 | #define USB_2_0_DEVICE | |
243 | #endif /*CONFIG_440EP*/ | |
244 | ||
245 | #ifdef DEBUG | |
246 | #define CONFIG_PANIC_HANG | |
247 | #else | |
248 | #define CONFIG_HW_WATCHDOG /* watchdog */ | |
249 | #endif | |
250 | ||
a4c8d138 | 251 | |
079a136c JL |
252 | /* |
253 | * BOOTP options | |
254 | */ | |
255 | #define CONFIG_BOOTP_BOOTFILESIZE | |
256 | #define CONFIG_BOOTP_BOOTPATH | |
257 | #define CONFIG_BOOTP_GATEWAY | |
258 | #define CONFIG_BOOTP_HOSTNAME | |
a4c8d138 | 259 | |
a4c8d138 | 260 | |
26a34560 JL |
261 | /* |
262 | * Command line configuration. | |
263 | */ | |
264 | #include <config_cmd_default.h> | |
265 | #define CONFIG_CMD_ASKENV | |
266 | #define CONFIG_CMD_DHCP | |
267 | #define CONFIG_CMD_DIAG | |
268 | #define CONFIG_CMD_EEPROM | |
269 | #define CONFIG_CMD_ELF | |
f98984cb HS |
270 | #define CONFIG_CMD_EXT2 |
271 | #define CONFIG_CMD_FAT | |
26a34560 | 272 | #define CONFIG_CMD_I2C |
f98984cb | 273 | #define CONFIG_CMD_IDE |
26a34560 JL |
274 | #define CONFIG_CMD_IRQ |
275 | #define CONFIG_CMD_MII | |
276 | #define CONFIG_CMD_NET | |
277 | #define CONFIG_CMD_NFS | |
278 | #define CONFIG_CMD_PCI | |
279 | #define CONFIG_CMD_PING | |
280 | #define CONFIG_CMD_REGINFO | |
f98984cb | 281 | #define CONFIG_CMD_REISER |
26a34560 | 282 | #define CONFIG_CMD_SDRAM |
26a34560 | 283 | #define CONFIG_CMD_USB |
a4c8d138 | 284 | |
26a34560 | 285 | #define CONFIG_SUPPORT_VFAT |
a4c8d138 SR |
286 | |
287 | /* | |
288 | * Miscellaneous configurable options | |
289 | */ | |
290 | #define CFG_LONGHELP /* undef to save memory */ | |
291 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
26a34560 | 292 | #if defined(CONFIG_CMD_KGDB) |
a4c8d138 SR |
293 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
294 | #else | |
295 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
296 | #endif | |
297 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
298 | #define CFG_MAXARGS 16 /* max number of command args */ | |
299 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
300 | ||
301 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
302 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
303 | ||
304 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
305 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
306 | #define CONFIG_LYNXKDI 1 /* support kdi files */ | |
307 | ||
308 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
309 | ||
310 | /*----------------------------------------------------------------------- | |
311 | * PCI stuff | |
312 | *----------------------------------------------------------------------- | |
313 | */ | |
314 | /* General PCI */ | |
315 | #define CONFIG_PCI /* include pci support */ | |
316 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
317 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
318 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ | |
319 | ||
320 | /* Board-specific PCI */ | |
a4c8d138 SR |
321 | #define CFG_PCI_TARGET_INIT |
322 | #define CFG_PCI_MASTER_INIT | |
323 | ||
324 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
325 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
326 | ||
327 | /* | |
328 | * For booting Linux, the board info and command line data | |
329 | * have to be in the first 8 MB of memory, since this is | |
330 | * the maximum mapped by the Linux kernel during initialization. | |
331 | */ | |
332 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
333 | ||
334 | /*----------------------------------------------------------------------- | |
335 | * External Bus Controller (EBC) Setup | |
336 | *----------------------------------------------------------------------*/ | |
337 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ | |
338 | #define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */ | |
339 | ||
340 | #define CFG_FLASH FLASH_BASE0_PRELIM | |
341 | #define CFG_SRAM 0xF1000000 | |
342 | #define CFG_FPGA 0xF2000000 | |
343 | #define CFG_CF1 0xF0000000 | |
344 | #define CFG_CF2 0xF0100000 | |
345 | ||
346 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
347 | #define CFG_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */ | |
348 | #define CFG_EBC_PB0CR (CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ | |
349 | ||
350 | /* Memory Bank 1 (SRAM) initialization */ | |
351 | #define CFG_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */ | |
352 | #define CFG_EBC_PB1CR (CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ | |
353 | ||
354 | /* Memory Bank 2 (FPGA) initialization */ | |
355 | #define CFG_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */ | |
356 | #define CFG_EBC_PB2CR (CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ | |
357 | ||
358 | /* Memory Bank 3 (CompactFlash) initialization */ | |
359 | #define CFG_EBC_PB3AP 0x080BD400 | |
360 | #define CFG_EBC_PB3CR (CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ | |
361 | ||
362 | /* Memory Bank 4 (CompactFlash) initialization */ | |
363 | #define CFG_EBC_PB4AP 0x080BD400 | |
364 | #define CFG_EBC_PB4CR (CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ | |
365 | ||
366 | /*----------------------------------------------------------------------- | |
367 | * PPC440 GPIO Configuration | |
368 | */ | |
aee747f1 | 369 | #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
a4c8d138 SR |
370 | { \ |
371 | /* GPIO Core 0 */ \ | |
85f73737 SR |
372 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ |
373 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
374 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
375 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
376 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
377 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
378 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \ | |
379 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \ | |
380 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \ | |
381 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \ | |
382 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \ | |
383 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \ | |
384 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \ | |
385 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \ | |
386 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \ | |
387 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \ | |
388 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \ | |
389 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \ | |
390 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \ | |
391 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \ | |
392 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \ | |
393 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \ | |
394 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \ | |
395 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \ | |
396 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \ | |
397 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \ | |
398 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \ | |
399 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
400 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \ | |
401 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
402 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
403 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
a4c8d138 SR |
404 | }, \ |
405 | { \ | |
406 | /* GPIO Core 1 */ \ | |
85f73737 SR |
407 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ |
408 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ | |
409 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
410 | {GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
411 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ | |
412 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ | |
413 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
414 | {GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
415 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \ | |
416 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \ | |
417 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \ | |
418 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \ | |
419 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
420 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
421 | {GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
422 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
423 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
424 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
425 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
426 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
427 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
428 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
429 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
430 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
431 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
432 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
433 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
434 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
435 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
436 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
437 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
438 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
a4c8d138 SR |
439 | } \ |
440 | } | |
441 | ||
a4c8d138 SR |
442 | /* |
443 | * Internal Definitions | |
444 | * | |
445 | * Boot Flags | |
446 | */ | |
447 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
448 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
449 | ||
26a34560 | 450 | #if defined(CONFIG_CMD_KGDB) |
a4c8d138 SR |
451 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
452 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
453 | #endif | |
454 | ||
566a494f HS |
455 | /*----------------------------------------------------------------------- |
456 | * IDE/ATA stuff Supports IDE harddisk | |
457 | *----------------------------------------------------------------------- | |
458 | */ | |
459 | ||
460 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
461 | ||
462 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
463 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
464 | ||
465 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
466 | #define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ | |
467 | ||
468 | #define CONFIG_IDE_PREINIT 1 | |
469 | #define CONFIG_IDE_RESET 1 | |
470 | ||
471 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
472 | ||
473 | #define CFG_ATA_BASE_ADDR CFG_CF1 | |
474 | ||
475 | /* Offset for data I/O */ | |
476 | #define CFG_ATA_DATA_OFFSET 0 | |
477 | ||
478 | /* Offset for normal register accesses */ | |
479 | #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) | |
480 | ||
481 | /* Offset for alternate registers */ | |
482 | #define CFG_ATA_ALT_OFFSET (0x0000) | |
483 | ||
a4c8d138 | 484 | #endif /* __CONFIG_H */ |