]>
Commit | Line | Data |
---|---|---|
ba94a1bb | 1 | /* |
1bbf5eae | 2 | * (C) Copyright 2006-2007 |
ba94a1bb WD |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * Configuation settings for the PDNB3 board. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | * (easy to change) | |
32 | */ | |
33 | #define CONFIG_IXP425 1 /* This is an IXP425 CPU */ | |
34 | #define CONFIG_PDNB3 1 /* on an PDNB3 board */ | |
35 | ||
36 | #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ | |
37 | #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ | |
38 | ||
39 | /* | |
40 | * Ethernet | |
41 | */ | |
42 | #define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ | |
43 | #define CONFIG_NET_MULTI 1 | |
44 | #define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */ | |
45 | #define CONFIG_HAS_ETH1 | |
46 | #define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */ | |
47 | #define CONFIG_MII 1 /* MII PHY management */ | |
6d0f6bcf | 48 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
ba94a1bb WD |
49 | |
50 | /* | |
51 | * Misc configuration options | |
52 | */ | |
53 | #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ | |
b54384e3 | 54 | #define CONFIG_TIMER_IRQ |
ba94a1bb WD |
55 | |
56 | #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ | |
6d0f6bcf | 57 | #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ |
ba94a1bb WD |
58 | |
59 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
60 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
61 | #define CONFIG_INITRD_TAG 1 | |
62 | ||
63 | /* | |
64 | * Size of malloc() pool | |
65 | */ | |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) |
67 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
ba94a1bb WD |
68 | |
69 | /* allow to overwrite serial and ethaddr */ | |
70 | #define CONFIG_ENV_OVERWRITE | |
71 | ||
930590f3 | 72 | #define CONFIG_IXP_SERIAL |
ba94a1bb | 73 | #define CONFIG_BAUDRATE 115200 |
6d0f6bcf | 74 | #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ |
ba94a1bb | 75 | |
26a34560 | 76 | |
079a136c JL |
77 | /* |
78 | * BOOTP options | |
79 | */ | |
80 | #define CONFIG_BOOTP_BOOTFILESIZE | |
81 | #define CONFIG_BOOTP_BOOTPATH | |
82 | #define CONFIG_BOOTP_GATEWAY | |
83 | #define CONFIG_BOOTP_HOSTNAME | |
84 | ||
85 | ||
26a34560 JL |
86 | /* |
87 | * Command line configuration. | |
88 | */ | |
89 | #include <config_cmd_default.h> | |
90 | ||
91 | #define CONFIG_CMD_DHCP | |
92 | #define CONFIG_CMD_DATE | |
93 | #define CONFIG_CMD_NET | |
94 | #define CONFIG_CMD_MII | |
95 | #define CONFIG_CMD_I2C | |
96 | #define CONFIG_CMD_ELF | |
97 | #define CONFIG_CMD_PING | |
98 | ||
99 | #if !defined(CONFIG_SCPU) | |
100 | #define CONFIG_CMD_NAND | |
9d8d5a5b SR |
101 | #endif |
102 | ||
ba94a1bb WD |
103 | |
104 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
105 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
106 | ||
107 | /* | |
108 | * Miscellaneous configurable options | |
109 | */ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
111 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
112 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
113 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
114 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
115 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
116 | ||
117 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
118 | #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ | |
119 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ | |
120 | ||
6d0f6bcf | 121 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
ba94a1bb | 122 | /* valid baudrates */ |
6d0f6bcf | 123 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
ba94a1bb WD |
124 | |
125 | /* | |
126 | * Stack sizes | |
127 | * | |
128 | * The stack sizes are set up in start.S using the settings below | |
129 | */ | |
130 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
131 | #ifdef CONFIG_USE_IRQ | |
132 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
133 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
134 | #endif | |
135 | ||
136 | /*************************************************************** | |
137 | * Platform/Board specific defines start here. | |
138 | ***************************************************************/ | |
139 | ||
140 | /*----------------------------------------------------------------------- | |
141 | * Default configuration (environment varibles...) | |
142 | *----------------------------------------------------------------------*/ | |
143 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 144 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
ba94a1bb WD |
145 | "echo" |
146 | ||
147 | #undef CONFIG_BOOTARGS | |
148 | ||
149 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
150 | "netdev=eth0\0" \ | |
151 | "hostname=pdnb3\0" \ | |
152 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
153 | "nfsroot=${serverip}:${rootpath}\0" \ | |
154 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
155 | "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ | |
156 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
157 | ":${hostname}:${netdev}:off panic=1\0" \ | |
158 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \ | |
159 | "mtdparts=${mtdparts}\0" \ | |
160 | "flash_nfs=run nfsargs addip addtty;" \ | |
161 | "bootm ${kernel_addr}\0" \ | |
162 | "flash_self=run ramargs addip addtty;" \ | |
163 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
164 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
165 | "bootm\0" \ | |
166 | "rootpath=/opt/buildroot\0" \ | |
167 | "bootfile=/tftpboot/netbox/uImage\0" \ | |
168 | "kernel_addr=50080000\0" \ | |
169 | "ramdisk_addr=50200000\0" \ | |
170 | "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \ | |
171 | "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \ | |
172 | "cp.b 100000 50000000 ${filesize};" \ | |
173 | "setenv filesize;saveenv\0" \ | |
d8ab58b2 | 174 | "upd=run load update\0" \ |
ba94a1bb WD |
175 | "ipaddr=10.0.0.233\0" \ |
176 | "serverip=10.0.0.152\0" \ | |
a99715b8 | 177 | "netmask=255.255.0.0\0" \ |
ba94a1bb WD |
178 | "ethaddr=c6:6f:13:36:f3:81\0" \ |
179 | "eth1addr=c6:6f:13:36:f3:82\0" \ | |
180 | "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \ | |
181 | "4k@508k(renv)\0" \ | |
182 | "" | |
183 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
184 | ||
185 | /* | |
186 | * Physical Memory Map | |
187 | */ | |
188 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
189 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
190 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
191 | ||
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_FLASH_BASE 0x50000000 |
193 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
9d8d5a5b | 194 | #if defined(CONFIG_SCPU) |
6d0f6bcf | 195 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ |
9d8d5a5b | 196 | #else |
6d0f6bcf | 197 | #define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ |
9d8d5a5b | 198 | #endif |
ba94a1bb WD |
199 | |
200 | /* | |
201 | * Expansion bus settings | |
202 | */ | |
9d8d5a5b | 203 | #if defined(CONFIG_SCPU) |
6d0f6bcf | 204 | #define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */ |
9d8d5a5b | 205 | #else |
6d0f6bcf | 206 | #define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */ |
9d8d5a5b | 207 | #endif |
6d0f6bcf | 208 | #define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */ |
ba94a1bb WD |
209 | |
210 | /* | |
211 | * SDRAM settings | |
212 | */ | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_SDR_CONFIG 0x18 |
214 | #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 | |
215 | #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a | |
ba94a1bb WD |
216 | |
217 | /* | |
218 | * FLASH and environment organization | |
219 | */ | |
9d8d5a5b | 220 | #if defined(CONFIG_SCPU) |
6d0f6bcf | 221 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 222 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
6d0f6bcf | 223 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ |
9d8d5a5b SR |
224 | #endif |
225 | ||
6d0f6bcf | 226 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
ba94a1bb | 227 | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
229 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
ba94a1bb | 230 | |
6d0f6bcf JCPV |
231 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
232 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
ba94a1bb | 233 | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
235 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
236 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
ba94a1bb WD |
237 | /* |
238 | * The following defines are added for buggy IOP480 byte interface. | |
239 | * All other boards should use the standard values (CPCI405 etc.) | |
240 | */ | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
242 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
243 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
ba94a1bb | 244 | |
6d0f6bcf | 245 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
ba94a1bb | 246 | |
5a1aceb0 | 247 | #define CONFIG_ENV_IS_IN_FLASH 1 |
ba94a1bb | 248 | |
6d0f6bcf | 249 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
9d8d5a5b | 250 | #if defined(CONFIG_SCPU) |
1bbf5eae | 251 | /* no redundant environment on SCPU */ |
0e8d1586 JCPV |
252 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
253 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
9d8d5a5b | 254 | #else |
0e8d1586 JCPV |
255 | #define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ |
256 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
ba94a1bb WD |
257 | |
258 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
259 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
260 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
1bbf5eae | 261 | #endif |
ba94a1bb | 262 | |
9d8d5a5b | 263 | #if !defined(CONFIG_SCPU) |
ba94a1bb WD |
264 | /* |
265 | * NAND-FLASH stuff | |
266 | */ | |
6d0f6bcf | 267 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
2eb99ca8 WD |
268 | #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ |
269 | #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ | |
9d8d5a5b | 270 | #endif |
ba94a1bb WD |
271 | |
272 | /* | |
273 | * GPIO settings | |
274 | */ | |
275 | ||
276 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/ |
278 | #define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */ | |
279 | #define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */ | |
280 | #define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */ | |
281 | #define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */ | |
ba94a1bb WD |
282 | |
283 | /* other GPIO's */ | |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_GPIO_RESTORE_INT 0 |
285 | #define CONFIG_SYS_GPIO_RESTART_INT 1 | |
286 | #define CONFIG_SYS_GPIO_SYS_RUNNING 2 | |
287 | #define CONFIG_SYS_GPIO_PCI_INTA 3 | |
288 | #define CONFIG_SYS_GPIO_PCI_INTB 4 | |
289 | #define CONFIG_SYS_GPIO_I2C_SCL 6 | |
290 | #define CONFIG_SYS_GPIO_I2C_SDA 7 | |
291 | #define CONFIG_SYS_GPIO_FPGA_RESET 9 | |
292 | #define CONFIG_SYS_GPIO_CLK_33M 15 | |
ba94a1bb WD |
293 | |
294 | /* | |
295 | * I2C stuff | |
296 | */ | |
297 | ||
298 | /* enable I2C and select the hardware/software driver */ | |
299 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
300 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
301 | ||
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */ |
303 | #define CONFIG_SYS_I2C_SLAVE 0xFE | |
ba94a1bb WD |
304 | |
305 | /* | |
306 | * Software (bit-bang) I2C driver configuration | |
307 | */ | |
6d0f6bcf JCPV |
308 | #define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL) |
309 | #define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA) | |
ba94a1bb | 310 | |
6d0f6bcf JCPV |
311 | #define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL) |
312 | #define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA) | |
313 | #define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA) | |
ba94a1bb | 314 | #define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0) |
6d0f6bcf JCPV |
315 | #define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \ |
316 | else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA) | |
317 | #define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \ | |
318 | else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL) | |
ba94a1bb WD |
319 | #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ |
320 | ||
321 | /* | |
322 | * I2C RTC | |
323 | */ | |
9d8d5a5b SR |
324 | #if 0 /* test-only */ |
325 | #define CONFIG_RTC_DS1340 1 | |
6d0f6bcf | 326 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
9d8d5a5b SR |
327 | #else |
328 | /* M41T11 Serial Access Timekeeper(R) SRAM */ | |
ba94a1bb | 329 | #define CONFIG_RTC_M41T11 1 |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
331 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ | |
9d8d5a5b | 332 | #endif |
ba94a1bb WD |
333 | |
334 | /* | |
335 | * Spartan3 FPGA configuration support | |
336 | */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */ |
ba94a1bb | 338 | |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/ |
340 | #define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */ | |
341 | #define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */ | |
342 | #define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */ | |
343 | #define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */ | |
ba94a1bb WD |
344 | |
345 | /* | |
346 | * Cache Configuration | |
347 | */ | |
6d0f6bcf | 348 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
ba94a1bb WD |
349 | |
350 | #endif /* __CONFIG_H */ |