[people/ms/u-boot.git] / include / configs / pdnb3.h

/*
 * (C) Copyright 2006-2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * Configuation settings for the PDNB3 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_IXP425		1       /* This is an IXP425 CPU	*/
#define CONFIG_PDNB3		1       /* on an PDNB3 board		*/

#define	CONFIG_MACH_TYPE	1002

#define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
#define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/

/*
 * Ethernet
 */
#define CONFIG_IXP4XX_NPE	1	/* include IXP4xx NPE support	*/
#define	CONFIG_PHY_ADDR		16	/* NPE0 PHY address		*/
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	18	/* NPE1 PHY address		*/
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */

/*
 * Misc configuration options
 */
#define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
#define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(1 << 20)

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_IXP_SERIAL
#define CONFIG_BAUDRATE         115200
#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_PING

#if !defined(CONFIG_SCPU)
#define CONFIG_CMD_NAND
#endif


#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
#define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */

#define CONFIG_IXP425_TIMER_CLK		66666666
#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */

/***************************************************************
 * Platform/Board specific defines start here.
 ***************************************************************/

/*-----------------------------------------------------------------------
 * Default configuration (environment varibles...)
 *----------------------------------------------------------------------*/
#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=pdnb3\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} "		\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} "	\
	"mtdparts=${mtdparts}\0"					\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
		"bootm\0"						\
	"rootpath=/opt/buildroot\0"					\
	"bootfile=/tftpboot/netbox/uImage\0"				\
	"kernel_addr=50080000\0"					\
	"ramdisk_addr=50200000\0"					\
	"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0"		\
	"update=protect off 50000000 5007dfff;era 50000000 5007dfff;"	\
		"cp.b 100000 50000000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	"ipaddr=10.0.0.233\0"						\
	"serverip=10.0.0.152\0"						\
	"netmask=255.255.0.0\0"						\
	"ethaddr=c6:6f:13:36:f3:81\0"					\
	"eth1addr=c6:6f:13:36:f3:82\0"					\
	"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env),"		\
	"4k@508k(renv)\0"						\
	""
#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */

#define CONFIG_SYS_TEXT_BASE	       0x50000000
#define CONFIG_SYS_FLASH_BASE          0x50000000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#if defined(CONFIG_SCPU)
#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 512 kB for Monitor	*/
#else
#define CONFIG_SYS_MONITOR_LEN		(504 << 10)	/* Reserve 512 kB for Monitor	*/
#endif

/*
 * Expansion bus settings
 */
#if defined(CONFIG_SCPU)
#define CONFIG_SYS_EXP_CS0		0x94d23C42	/* 8bit, max size		*/
#else
#define CONFIG_SYS_EXP_CS0		0x94913C43	/* 8bit, max size		*/
#endif
#define CONFIG_SYS_EXP_CS1		0x85000043	/* 8bit, 512bytes		*/

/*
 * SDRAM settings
 */
#define CONFIG_SYS_SDR_CONFIG		0x18
#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a

/*
 * FLASH and environment organization
 */
#if defined(CONFIG_SCPU)
#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
#endif

#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE		/* FLASH bank #0	*/

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define	CONFIG_ENV_IS_IN_FLASH	1

#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#if defined(CONFIG_SCPU)
/* no redundant environment on SCPU */
#define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector		*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
#else
#define CONFIG_ENV_SECT_SIZE	0x1000	/* size of one complete sector		*/
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

#if !defined(CONFIG_SCPU)
/*
 * NAND-FLASH stuff
 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x51000000	/* NAND FLASH Base Address */
#endif

/*
 * GPIO settings
 */

/* FPGA program pin configuration */
#define CONFIG_SYS_GPIO_PRG		12		/* FPGA program pin (cpu output)*/
#define CONFIG_SYS_GPIO_CLK		10		/* FPGA clk pin (cpu output)    */
#define CONFIG_SYS_GPIO_DATA		14		/* FPGA data pin (cpu output)   */
#define CONFIG_SYS_GPIO_INIT		13		/* FPGA init pin (cpu input)    */
#define CONFIG_SYS_GPIO_DONE		11		/* FPGA done pin (cpu input)    */

/* other GPIO's */
#define CONFIG_SYS_GPIO_RESTORE_INT	0
#define CONFIG_SYS_GPIO_RESTART_INT	1
#define CONFIG_SYS_GPIO_SYS_RUNNING	2
#define CONFIG_SYS_GPIO_PCI_INTA	3
#define CONFIG_SYS_GPIO_PCI_INTB	4
#define CONFIG_SYS_GPIO_I2C_SCL	6
#define CONFIG_SYS_GPIO_I2C_SDA	7
#define CONFIG_SYS_GPIO_FPGA_RESET	9
#define CONFIG_SYS_GPIO_CLK_33M	15

/*
 * I2C stuff
 */

/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	83000	/* 83 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		(1 << CONFIG_SYS_GPIO_I2C_SCL)
#define PB_SDA		(1 << CONFIG_SYS_GPIO_I2C_SDA)

#define I2C_INIT	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
#define I2C_ACTIVE	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_TRISTATE	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_READ	((*IXP425_GPIO_GPINR & PB_SDA) != 0)
#define I2C_SDA(bit)	if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA);	\
			else     GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_SCL(bit)	if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL);	\
			else     GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
#define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */

/*
 * I2C RTC
 */
#if 0 /* test-only */
#define CONFIG_RTC_DS1340	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#else
/* M41T11 Serial Access Timekeeper(R) SRAM */
#define CONFIG_RTC_M41T11	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with the linux driver */
#endif

/*
 * Spartan3 FPGA configuration support
 */
#define CONFIG_SYS_FPGA_MAX_SIZE	700*1024	/* 700kByte for XC3S500E	*/

#define CONFIG_SYS_FPGA_PRG	(1 << CONFIG_SYS_GPIO_PRG)	/* FPGA program pin (cpu output)*/
#define CONFIG_SYS_FPGA_CLK	(1 << CONFIG_SYS_GPIO_CLK)	/* FPGA clk pin (cpu output)    */
#define CONFIG_SYS_FPGA_DATA	(1 << CONFIG_SYS_GPIO_DATA)	/* FPGA data pin (cpu output)   */
#define CONFIG_SYS_FPGA_INIT	(1 << CONFIG_SYS_GPIO_INIT)	/* FPGA init pin (cpu input)    */
#define CONFIG_SYS_FPGA_DONE	(1 << CONFIG_SYS_GPIO_DONE)	/* FPGA done pin (cpu input)    */

/*
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_INIT_SP_ADDR        \
	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)

#endif  /* __CONFIG_H */
Commit	Line	Data
ba94a1bb	1	/*
1bbf5eae	2	* (C) Copyright 2006-2007
ba94a1bb WD	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* Configuation settings for the PDNB3 board.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
ba94a1bb WD	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	* (easy to change)
	16	*/
	17	#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
	18	#define CONFIG_PDNB3 1 /* on an PDNB3 board */
	19
8e807ec3 MV	20	#define CONFIG_MACH_TYPE 1002
8e807ec3 MV	21
ba94a1bb WD	22	#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
	23	#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
	24
	25	/*
	26	* Ethernet
	27	*/
	28	#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
ba94a1bb WD	29	#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
	30	#define CONFIG_HAS_ETH1
	31	#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
	32	#define CONFIG_MII 1 /* MII PHY management */
6d0f6bcf	33	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
ba94a1bb WD	34
	35	/*
	36	* Misc configuration options
	37	*/
ba94a1bb	38	#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
6d0f6bcf	39	#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
ba94a1bb WD	40
	41	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	42	#define CONFIG_SETUP_MEMORY_TAGS 1
	43	#define CONFIG_INITRD_TAG 1
	44
	45	/*
	46	* Size of malloc() pool
	47	*/
6d0f6bcf	48	#define CONFIG_SYS_MALLOC_LEN (1 << 20)
ba94a1bb WD	49
	50	/* allow to overwrite serial and ethaddr */
	51	#define CONFIG_ENV_OVERWRITE
	52
930590f3	53	#define CONFIG_IXP_SERIAL
ba94a1bb	54	#define CONFIG_BAUDRATE 115200
6d0f6bcf	55	#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
ba94a1bb	56
26a34560	57
079a136c JL	58	/*
	59	* BOOTP options
	60	*/
	61	#define CONFIG_BOOTP_BOOTFILESIZE
	62	#define CONFIG_BOOTP_BOOTPATH
	63	#define CONFIG_BOOTP_GATEWAY
	64	#define CONFIG_BOOTP_HOSTNAME
	65
	66
26a34560 JL	67	/*
	68	* Command line configuration.
	69	*/
	70	#include <config_cmd_default.h>
	71
	72	#define CONFIG_CMD_DHCP
	73	#define CONFIG_CMD_DATE
	74	#define CONFIG_CMD_NET
	75	#define CONFIG_CMD_MII
	76	#define CONFIG_CMD_I2C
	77	#define CONFIG_CMD_ELF
	78	#define CONFIG_CMD_PING
	79
	80	#if !defined(CONFIG_SCPU)
	81	#define CONFIG_CMD_NAND
9d8d5a5b SR	82	#endif
9d8d5a5b SR	83
ba94a1bb WD	84
	85	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	86	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	87
	88	/*
	89	* Miscellaneous configurable options
	90	*/
6d0f6bcf	91	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	92	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	93	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	94	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	95	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	96
	97	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
	98	#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
	99	#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
	100
904ec57b	101	#define CONFIG_IXP425_TIMER_CLK 66666666
6d0f6bcf	102	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
ba94a1bb	103
ba94a1bb WD	104	/***************************************************************
	105	* Platform/Board specific defines start here.
	106	***************************************************************/
	107
	108	/*-----------------------------------------------------------------------
	109	* Default configuration (environment varibles...)
	110	----------------------------------------------------------------------/
	111	#define CONFIG_PREBOOT "echo;" \
32bf3d14	112	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
ba94a1bb WD	113	"echo"
	114
	115	#undef CONFIG_BOOTARGS
	116
	117	#define CONFIG_EXTRA_ENV_SETTINGS \
	118	"netdev=eth0\0" \
	119	"hostname=pdnb3\0" \
	120	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	121	"nfsroot=${serverip}:${rootpath}\0" \
	122	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	123	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
	124	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	125	":${hostname}:${netdev}:off panic=1\0" \
	126	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
	127	"mtdparts=${mtdparts}\0" \
	128	"flash_nfs=run nfsargs addip addtty;" \
	129	"bootm ${kernel_addr}\0" \
	130	"flash_self=run ramargs addip addtty;" \
	131	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	132	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
93e14596	133	"bootm\0" \
ba94a1bb WD	134	"rootpath=/opt/buildroot\0" \
	135	"bootfile=/tftpboot/netbox/uImage\0" \
	136	"kernel_addr=50080000\0" \
	137	"ramdisk_addr=50200000\0" \
	138	"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
	139	"update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
	140	"cp.b 100000 50000000 ${filesize};" \
	141	"setenv filesize;saveenv\0" \
d8ab58b2	142	"upd=run load update\0" \
ba94a1bb WD	143	"ipaddr=10.0.0.233\0" \
ba94a1bb WD	144	"serverip=10.0.0.152\0" \
a99715b8	145	"netmask=255.255.0.0\0" \
ba94a1bb WD	146	"ethaddr=c6:6f:13:36:f3:81\0" \
	147	"eth1addr=c6:6f:13:36:f3:82\0" \
	148	"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
	149	"4k@508k(renv)\0" \
	150	""
	151	#define CONFIG_BOOTCOMMAND "run net_nfs"
	152
	153	/*
	154	* Physical Memory Map
	155	*/
	156	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	157	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
	158	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
	159
904ec57b	160	#define CONFIG_SYS_TEXT_BASE 0x50000000
6d0f6bcf JCPV	161	#define CONFIG_SYS_FLASH_BASE 0x50000000
6d0f6bcf JCPV	162	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
9d8d5a5b	163	#if defined(CONFIG_SCPU)
6d0f6bcf	164	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
9d8d5a5b	165	#else
6d0f6bcf	166	#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
9d8d5a5b	167	#endif
ba94a1bb WD	168
	169	/*
	170	* Expansion bus settings
	171	*/
9d8d5a5b	172	#if defined(CONFIG_SCPU)
6d0f6bcf	173	#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
9d8d5a5b	174	#else
6d0f6bcf	175	#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
9d8d5a5b	176	#endif
6d0f6bcf	177	#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
ba94a1bb WD	178
	179	/*
	180	* SDRAM settings
	181	*/
6d0f6bcf JCPV	182	#define CONFIG_SYS_SDR_CONFIG 0x18
	183	#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
	184	#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
ba94a1bb WD	185
	186	/*
	187	* FLASH and environment organization
	188	*/
9d8d5a5b	189	#if defined(CONFIG_SCPU)
6d0f6bcf	190	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	191	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf	192	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
9d8d5a5b SR	193	#endif
9d8d5a5b SR	194
6d0f6bcf	195	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
ba94a1bb	196
6d0f6bcf JCPV	197	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	198	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
ba94a1bb	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
ba94a1bb	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
	204	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	205	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
ba94a1bb WD	206	/*
	207	* The following defines are added for buggy IOP480 byte interface.
	208	* All other boards should use the standard values (CPCI405 etc.)
	209	*/
6d0f6bcf JCPV	210	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	211	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	212	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
ba94a1bb	213
6d0f6bcf	214	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
ba94a1bb	215
5a1aceb0	216	#define CONFIG_ENV_IS_IN_FLASH 1
ba94a1bb	217
6d0f6bcf	218	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
9d8d5a5b	219	#if defined(CONFIG_SCPU)
1bbf5eae	220	/* no redundant environment on SCPU */
0e8d1586 JCPV	221	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
0e8d1586 JCPV	222	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
9d8d5a5b	223	#else
0e8d1586 JCPV	224	#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
0e8d1586 JCPV	225	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
ba94a1bb WD	226
ba94a1bb WD	227	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	228	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	229	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
1bbf5eae	230	#endif
ba94a1bb	231
9d8d5a5b	232	#if !defined(CONFIG_SCPU)
ba94a1bb WD	233	/*
	234	* NAND-FLASH stuff
	235	*/
6d0f6bcf	236	#define CONFIG_SYS_MAX_NAND_DEVICE 1
2eb99ca8	237	#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
9d8d5a5b	238	#endif
ba94a1bb WD	239
	240	/*
	241	* GPIO settings
	242	*/
	243
	244	/* FPGA program pin configuration */
6d0f6bcf JCPV	245	#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
	246	#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
	247	#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
	248	#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
	249	#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
ba94a1bb WD	250
ba94a1bb WD	251	/* other GPIO's */
6d0f6bcf JCPV	252	#define CONFIG_SYS_GPIO_RESTORE_INT 0
	253	#define CONFIG_SYS_GPIO_RESTART_INT 1
	254	#define CONFIG_SYS_GPIO_SYS_RUNNING 2
	255	#define CONFIG_SYS_GPIO_PCI_INTA 3
	256	#define CONFIG_SYS_GPIO_PCI_INTB 4
	257	#define CONFIG_SYS_GPIO_I2C_SCL 6
	258	#define CONFIG_SYS_GPIO_I2C_SDA 7
	259	#define CONFIG_SYS_GPIO_FPGA_RESET 9
	260	#define CONFIG_SYS_GPIO_CLK_33M 15
ba94a1bb WD	261
	262	/*
	263	* I2C stuff
	264	*/
	265
	266	/* enable I2C and select the hardware/software driver */
ea818dbb HS	267	#define CONFIG_SYS_I2C
	268	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	269	#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
	270	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
ba94a1bb WD	271	/*
	272	* Software (bit-bang) I2C driver configuration
	273	*/
6d0f6bcf JCPV	274	#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
6d0f6bcf JCPV	275	#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
ba94a1bb	276
6d0f6bcf JCPV	277	#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
	278	#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
	279	#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
ba94a1bb	280	#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
6d0f6bcf	281	#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
93e14596	282	else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
6d0f6bcf JCPV	283	#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
6d0f6bcf JCPV	284	else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
ba94a1bb WD	285	#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
	286
	287	/*
	288	* I2C RTC
	289	*/
9d8d5a5b SR	290	#if 0 /* test-only */
9d8d5a5b SR	291	#define CONFIG_RTC_DS1340 1
6d0f6bcf	292	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
9d8d5a5b SR	293	#else
9d8d5a5b SR	294	/* M41T11 Serial Access Timekeeper(R) SRAM */
ba94a1bb	295	#define CONFIG_RTC_M41T11 1
6d0f6bcf JCPV	296	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
6d0f6bcf JCPV	297	#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
9d8d5a5b	298	#endif
ba94a1bb WD	299
	300	/*
	301	* Spartan3 FPGA configuration support
	302	*/
6d0f6bcf	303	#define CONFIG_SYS_FPGA_MAX_SIZE 7001024 / 700kByte for XC3S500E */
ba94a1bb	304
6d0f6bcf JCPV	305	#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
	306	#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
	307	#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
	308	#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
	309	#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
ba94a1bb WD	310
	311	/*
	312	* Cache Configuration
	313	*/
6d0f6bcf	314	#define CONFIG_SYS_CACHELINE_SIZE 32
ba94a1bb	315
904ec57b MS	316	/* additions for new relocation code, must be added to all boards */
	317	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	318	#define CONFIG_SYS_INIT_SP_ADDR \
	319	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
	320
ba94a1bb	321	#endif /* __CONFIG_H */