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8e4ab1d5 AS |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * | |
4 | * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_PEACH_PIT_H | |
10 | #define __CONFIG_PEACH_PIT_H | |
11 | ||
d7e1f02e SS |
12 | #define MEM_LAYOUT_ENV_SETTINGS \ |
13 | "bootm_size=0x10000000\0" \ | |
14 | "kernel_addr_r=0x22000000\0" \ | |
15 | "fdt_addr_r=0x23000000\0" \ | |
16 | "ramdisk_addr_r=0x23300000\0" \ | |
17 | "scriptaddr=0x30000000\0" \ | |
18 | "pxefile_addr_r=0x31000000\0" | |
19 | ||
87033d4d | 20 | #include <configs/exynos5420-common.h> |
7d159536 | 21 | #include <configs/exynos5-dt-common.h> |
bf637ea5 | 22 | #include <configs/exynos5-common.h> |
8e4ab1d5 | 23 | |
43900da8 | 24 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
43900da8 HH |
25 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) |
26 | ||
8e4ab1d5 AS |
27 | /* select serial console configuration */ |
28 | #define CONFIG_SERIAL3 /* use SERIAL 3 */ | |
43900da8 | 29 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" |
8e4ab1d5 | 30 | |
43581c83 AS |
31 | /* DRAM Memory Banks */ |
32 | #define CONFIG_NR_DRAM_BANKS 4 | |
33 | #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ | |
34 | ||
8e4ab1d5 | 35 | #endif /* __CONFIG_PEACH_PIT_H */ |