[people/ms/u-boot.git] / include / configs / pf5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*************************************************************************
 * (c) 2005 esd gmbh Hannover
 *
 *
 * from IceCube.h file
 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
 *
 *************************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */
#define CONFIG_PF5200		1	/* ... on PF5200  board */
#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */
/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#if 0				/* test-only */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#else
#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
#endif
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_MII		1
#if 0				/* test-only !!! */
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1
#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#if 0
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE

#define CONFIG_CMD_PCI


#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT16	1
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT08	1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Welcome to ParaFinder pf5200;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=eth0\0" \
	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
	"loadaddr=01000000\0" \
	"serverip=192.168.2.99\0" \
	"gatewayip=10.0.0.79\0" \
	"user=mu\0" \
	"target=pf5200.esd\0" \
	"script=pf5200.bat\0" \
	"image=/tftpboot/vxWorks_pf5200\0" \
	"ipaddr=10.0.13.196\0" \
	"netmask=255.255.0.0\0" \
	""

#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		86000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/*
 * Environment settings
 */
#if 1				/* test-only */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_OVERWRITE	1
#else
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
				   /* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE	1
#endif

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_UDP_CHECKSUM	1

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0004DD00

#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS1_START		0xfd000000
#define CONFIG_SYS_CS1_SIZE		0x00010000
#define CONFIG_SYS_CS1_CFG		0x10101410

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/

#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CONFIG_SYS_ATA_STRIDE		4

/*-----------------------------------------------------------------------
 * CPLD stuff
 */
#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */

/* CPLD program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
#define CONFIG_SYS_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
#define CONFIG_SYS_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
#define CONFIG_SYS_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */

#define JTAG_GPIO_ADDR_TMS	(CONFIG_SYS_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
#define JTAG_GPIO_ADDR_TCK	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
#define JTAG_GPIO_ADDR_TDI	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDO	(CONFIG_SYS_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */

#define JTAG_GPIO_ADDR_CFG	(CONFIG_SYS_MBAR + 0xB00)
#define JTAG_GPIO_CFG_SET	0x00000000
#define JTAG_GPIO_CFG_RESET	0x00F00000

#define JTAG_GPIO_ADDR_EN_TMS	(CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TMS_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TMS	(CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TMS_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TCK	(CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TCK_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TCK	(CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TCK_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDI	(CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDI_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDI	(CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
#define JTAG_GPIO_TDI_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDO	(CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDO_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDO	(CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TDO_DDR_SET	0x00000000
#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */

#endif				/* __CONFIG_H */
Commit	Line	Data
5e4b3361 SR	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
5e4b3361 SR	6	*/
	7
	8	/*************************************************************************
	9	* (c) 2005 esd gmbh Hannover
	10	*
	11	*
	12	* from IceCube.h file
	13	* by Reinhard Arlt reinhard.arlt@esd-electronics.com
	14	*
	15	*************************************************************************/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/*
	21	* High Level Configuration Options
	22	* (easy to change)
	23	*/
	24
b2a6dfe4	25	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
5e4b3361 SR	26	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
	27	#define CONFIG_PF5200 1 /* ... on PF5200 board */
	28	#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
	29
2ae18241 WD	30	#ifndef CONFIG_SYS_TEXT_BASE
	31	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	32	#endif
	33
6d0f6bcf	34	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
5e4b3361	35
31d82672	36	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
5e4b3361 SR	37	/*
	38	* Serial console configuration
	39	*/
	40	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	41	#if 0 /* test-only */
	42	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	43	#else
	44	#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
	45	#endif
6d0f6bcf	46	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
5e4b3361	47
5e4b3361 SR	48	/*
	49	* PCI Mapping:
	50	* 0x40000000 - 0x4fffffff - PCI Memory
	51	* 0x50000000 - 0x50ffffff - PCI IO Space
	52	*/
	53	#define CONFIG_PCI 1
	54	#define CONFIG_PCI_PNP 1
	55	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	56	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
5e4b3361 SR	57
	58	#define CONFIG_PCI_MEM_BUS 0x40000000
	59	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	60	#define CONFIG_PCI_MEM_SIZE 0x10000000
	61
	62	#define CONFIG_PCI_IO_BUS 0x50000000
	63	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	64	#define CONFIG_PCI_IO_SIZE 0x01000000
	65
63ff004c	66	#define CONFIG_MII 1
5e4b3361	67	#if 0 /* test-only !!! */
5e4b3361	68	#define CONFIG_EEPRO100 1
6d0f6bcf	69	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
5e4b3361 SR	70	#define CONFIG_NS8382X 1
5e4b3361 SR	71	#endif
5e4b3361 SR	72
	73	/* Partitions */
	74	#define CONFIG_MAC_PARTITION
	75	#define CONFIG_DOS_PARTITION
	76
	77	/* USB */
	78	#if 0
	79	#define CONFIG_USB_OHCI
5e4b3361	80	#define CONFIG_USB_STORAGE
5e4b3361 SR	81	#endif
5e4b3361 SR	82
d794cfef	83
079a136c JL	84	/*
	85	* BOOTP options
	86	*/
	87	#define CONFIG_BOOTP_BOOTFILESIZE
	88	#define CONFIG_BOOTP_BOOTPATH
	89	#define CONFIG_BOOTP_GATEWAY
	90	#define CONFIG_BOOTP_HOSTNAME
	91
	92
5e4b3361	93	/*
d794cfef	94	* Command line configuration.
5e4b3361	95	*/
d794cfef JL	96	#include <config_cmd_default.h>
	97
	98	#define CONFIG_CMD_BSP
d794cfef JL	99	#define CONFIG_CMD_EEPROM
	100	#define CONFIG_CMD_ELF
	101	#define CONFIG_CMD_FAT
	102	#define CONFIG_CMD_I2C
	103	#define CONFIG_CMD_IDE
	104
079a136c	105	#define CONFIG_CMD_PCI
079a136c	106
5e4b3361	107
14d0a02a	108	#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	109	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	110	# define CONFIG_SYS_LOWBOOT16 1
5e4b3361	111	#endif
14d0a02a	112	#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
6d0f6bcf JCPV	113	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	114	# define CONFIG_SYS_LOWBOOT08 1
5e4b3361 SR	115	#endif
	116
	117	/*
	118	* Autobooting
	119	*/
	120	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	121
	122	#define CONFIG_PREBOOT "echo;" \
	123	"echo Welcome to ParaFinder pf5200;" \
	124	"echo"
	125
	126	#undef CONFIG_BOOTARGS
	127
	128	#define CONFIG_EXTRA_ENV_SETTINGS \
	129	"netdev=eth0\0" \
	130	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
	131	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
fe126d8b WD	132	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	133	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	134	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
5e4b3361 SR	135	"loadaddr=01000000\0" \
	136	"serverip=192.168.2.99\0" \
	137	"gatewayip=10.0.0.79\0" \
	138	"user=mu\0" \
	139	"target=pf5200.esd\0" \
	140	"script=pf5200.bat\0" \
	141	"image=/tftpboot/vxWorks_pf5200\0" \
	142	"ipaddr=10.0.13.196\0" \
	143	"netmask=255.255.0.0\0" \
	144	""
	145
	146	#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
	147
5e4b3361 SR	148	/*
	149	* IPB Bus clocking configuration.
	150	*/
6d0f6bcf	151	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
5e4b3361 SR	152	/*
	153	* I2C configuration
	154	*/
	155	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	156	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
5e4b3361	157
6d0f6bcf JCPV	158	#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
6d0f6bcf JCPV	159	#define CONFIG_SYS_I2C_SLAVE 0x7F
5e4b3361 SR	160
	161	/*
	162	* EEPROM configuration
	163	*/
6d0f6bcf JCPV	164	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	165	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	166	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	167	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
	168	#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
5e4b3361 SR	169	/*
	170	* Flash configuration
	171	*/
6d0f6bcf JCPV	172	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	173	#define CONFIG_SYS_FLASH_SIZE 0x02000000
	174	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
	175	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	176	#define CONFIG_SYS_MAX_FLASH_SECT 512
5e4b3361	177
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	179	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
5e4b3361 SR	180
	181	/*
	182	* Environment settings
	183	*/
	184	#if 1 /* test-only */
5a1aceb0	185	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	186	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	187	#define CONFIG_ENV_SECT_SIZE 0x10000
5e4b3361 SR	188	#define CONFIG_ENV_OVERWRITE 1
5e4b3361 SR	189	#else
bb1f8b4f	190	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	191	#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	192	#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
5e4b3361 SR	193	/* total size of a CAT24WC32 is 8192 bytes */
	194	#define CONFIG_ENV_OVERWRITE 1
	195	#endif
	196
	197	/*
	198	* Memory map
	199	*/
6d0f6bcf JCPV	200	#define CONFIG_SYS_MBAR 0xF0000000
	201	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	202	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
5e4b3361 SR	203
5e4b3361 SR	204	/* Use SRAM until RAM will be available */
6d0f6bcf	205	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	206	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
5e4b3361	207
25ddd1fb	208	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	209	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e4b3361	210
14d0a02a	211	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	212	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	213	# define CONFIG_SYS_RAMBOOT 1
5e4b3361 SR	214	#endif
5e4b3361 SR	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	217	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	218	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5e4b3361 SR	219
	220	/*
	221	* Ethernet configuration
	222	*/
	223	#define CONFIG_MPC5xxx_FEC 1
86321fc1	224	#define CONFIG_MPC5xxx_FEC_MII100
5e4b3361	225	/*
86321fc1	226	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
5e4b3361	227	*/
86321fc1	228	/* #define CONFIG_MPC5xxx_FEC_MII10 */
5e4b3361 SR	229	#define CONFIG_PHY_ADDR 0x00
	230	#define CONFIG_UDP_CHECKSUM 1
	231
	232	/*
	233	* GPIO configuration
	234	*/
6d0f6bcf	235	#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
5e4b3361 SR	236
	237	/*
	238	* Miscellaneous configurable options
	239	*/
6d0f6bcf	240	#define CONFIG_SYS_LONGHELP /* undef to save memory */
d794cfef	241	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	242	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5e4b3361	243	#else
6d0f6bcf	244	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5e4b3361	245	#endif
6d0f6bcf JCPV	246	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	247	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	248	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5e4b3361	249
6d0f6bcf JCPV	250	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	251	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
5e4b3361	252
6d0f6bcf	253	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
5e4b3361	254
6d0f6bcf	255	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
5e4b3361	256
6d0f6bcf	257	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	258	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	259	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	260	#endif
d794cfef JL	261
5e4b3361 SR	262	/*
	263	* Various low-level settings
	264	*/
6d0f6bcf JCPV	265	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	266	#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e4b3361	267
6d0f6bcf JCPV	268	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	269	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	270	#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
5e4b3361	271
6d0f6bcf JCPV	272	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	273	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e4b3361	274
6d0f6bcf JCPV	275	#define CONFIG_SYS_CS1_START 0xfd000000
	276	#define CONFIG_SYS_CS1_SIZE 0x00010000
	277	#define CONFIG_SYS_CS1_CFG 0x10101410
5e4b3361	278
6d0f6bcf JCPV	279	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	280	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
5e4b3361	281
6d0f6bcf	282	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
5e4b3361 SR	283
	284	/*-----------------------------------------------------------------------
	285	* USB stuff
	286	*-----------------------------------------------------------------------
	287	*/
	288	#define CONFIG_USB_CLOCK 0x0001BBBB
	289	#define CONFIG_USB_CONFIG 0x00001000
	290
	291	/*-----------------------------------------------------------------------
	292	* IDE/ATA stuff Supports IDE harddisk
	293	*-----------------------------------------------------------------------
	294	*/
	295
	296	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	297
	298	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	299	#undef CONFIG_IDE_LED /* LED for ide not supported */
	300
	301	#define CONFIG_IDE_RESET /* reset for ide supported */
	302	#define CONFIG_IDE_PREINIT
	303
6d0f6bcf JCPV	304	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	305	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
5e4b3361	306
6d0f6bcf	307	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5e4b3361	308
6d0f6bcf	309	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
5e4b3361 SR	310
5e4b3361 SR	311	/* Offset for data I/O */
6d0f6bcf	312	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
5e4b3361 SR	313
5e4b3361 SR	314	/* Offset for normal register accesses */
6d0f6bcf	315	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
5e4b3361 SR	316
5e4b3361 SR	317	/* Offset for alternate registers */
6d0f6bcf	318	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
5e4b3361 SR	319
5e4b3361 SR	320	/* Interval between registers */
6d0f6bcf	321	#define CONFIG_SYS_ATA_STRIDE 4
5e4b3361 SR	322
	323	/*-----------------------------------------------------------------------
	324	* CPLD stuff
	325	*/
6d0f6bcf JCPV	326	#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
6d0f6bcf JCPV	327	#define CONFIG_SYS_FPGA_MAX_SIZE 321024 / 32kByte is enough for CPLD */
5e4b3361 SR	328
5e4b3361 SR	329	/* CPLD program pin configuration */
6d0f6bcf JCPV	330	#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
	331	#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
	332	#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
	333	#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
5e4b3361	334
6d0f6bcf JCPV	335	#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
	336	#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
	337	#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
	338	#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
5e4b3361	339
6d0f6bcf	340	#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
5e4b3361 SR	341	#define JTAG_GPIO_CFG_SET 0x00000000
	342	#define JTAG_GPIO_CFG_RESET 0x00F00000
	343
6d0f6bcf	344	#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
5e4b3361 SR	345	#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
5e4b3361 SR	346	#define JTAG_GPIO_TMS_EN_RESET 0x00000000
6d0f6bcf	347	#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
5e4b3361 SR	348	#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
	349	#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
	350
6d0f6bcf	351	#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
5e4b3361 SR	352	#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
5e4b3361 SR	353	#define JTAG_GPIO_TCK_EN_RESET 0x00000000
6d0f6bcf	354	#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
5e4b3361 SR	355	#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
	356	#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
	357
6d0f6bcf	358	#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
5e4b3361 SR	359	#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
5e4b3361 SR	360	#define JTAG_GPIO_TDI_EN_RESET 0x00000000
6d0f6bcf	361	#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
5e4b3361 SR	362	#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
	363	#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
	364
6d0f6bcf	365	#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
5e4b3361 SR	366	#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
5e4b3361 SR	367	#define JTAG_GPIO_TDO_EN_RESET 0x00000000
6d0f6bcf	368	#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
5e4b3361 SR	369	#define JTAG_GPIO_TDO_DDR_SET 0x00000000
	370	#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
	371
	372	#endif /* __CONFIG_H */