[people/ms/u-boot.git] / include / configs / pleb2.h

/*
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuration settings for the PLEB 2 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
#define CONFIG_PLEB2		1	/* on an PLEB2 Board	    */
#undef CONFIG_LCD
#undef CONFIG_MMC
#define BOARD_LATE_INIT		1
#define	CONFIG_SYS_TEXT_BASE	0x0

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)

/*
 * Hardware drivers
 */

/* None - PLEB 2 doesn't have any of this.
	#define CONFIG_LAN91C96
	#define CONFIG_LAN91C96_BASE 0x0C000000
 */

/*
 * select serial console configuration
 */
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART	       1       /* we use FFUART on PLEB 2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS


#define CONFIG_BOOTDELAY	3
#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.0.0
#define CONFIG_IPADDR		192.168.0.21
#define CONFIG_SERVERIP		192.168.0.250
#define CONFIG_BOOTCOMMAND	"bootm 40000"
#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"

#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_SETUP_MEMORY_TAGS

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER		1
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_DEVICE_NULLDEV	1

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0xa2000000	/* default load address */

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 200/200/100 MHz */

						/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#ifdef CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_CMD_MMC
#endif

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
#define PHYS_FLASH_SIZE		0x00800000 /* 4 MB */

/* Not entirely sure about this - DS/CHC */
#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
#define PHYS_FLASH_SECT_SIZE	0x00010000 /* 64 KB sectors (x2) */

#define CONFIG_SYS_DRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_DRAM_SIZE		PHYS_SDRAM_1_SIZE

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)

/*
 * GPIO settings
 */
#define CONFIG_SYS_GPSR0_VAL		0x00000000  /* Don't set anything */
#define CONFIG_SYS_GPSR1_VAL		0x00000080
#define CONFIG_SYS_GPSR2_VAL		0x00000000

#define CONFIG_SYS_GPCR0_VAL		0x00000000  /* Don't clear anything */
#define CONFIG_SYS_GPCR1_VAL		0x00000000
#define CONFIG_SYS_GPCR2_VAL		0x00000000

#define CONFIG_SYS_GPDR0_VAL		0x00000000
#define CONFIG_SYS_GPDR1_VAL		0x000007C3
#define CONFIG_SYS_GPDR2_VAL		0x00000000

/* Edge detect registers (these are set by the kernel) */
#define CONFIG_SYS_GRER0_VAL	    0x00000000
#define CONFIG_SYS_GRER1_VAL	    0x00000000
#define CONFIG_SYS_GRER2_VAL	    0x00000000
#define CONFIG_SYS_GFER0_VAL	    0x00000000
#define CONFIG_SYS_GFER1_VAL	    0x00000000
#define CONFIG_SYS_GFER2_VAL	    0x00000000

#define CONFIG_SYS_GAFR0_L_VAL		0x00000000
#define CONFIG_SYS_GAFR0_U_VAL		0x00000000
#define CONFIG_SYS_GAFR1_L_VAL		0x00008010  /* Use FF UART Send and Receive */
#define CONFIG_SYS_GAFR1_U_VAL		0x00000000
#define CONFIG_SYS_GAFR2_L_VAL		0x00000000
#define CONFIG_SYS_GAFR2_U_VAL		0x00000000

#define CONFIG_SYS_PSSR_VAL		0x20
#define CONFIG_SYS_CCCR		    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
#define CONFIG_SYS_CKEN		    0x00000060	/* FFUART and STUART enabled	*/
#define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/

/*
 * Memory settings
 */
#define CONFIG_SYS_MSC0_VAL		0x00007FF0 /* Not properly calculated - FIXME (DS) */
#define CONFIG_SYS_MSC1_VAL		0x00000000
#define CONFIG_SYS_MSC2_VAL		0x00000000

#define CONFIG_SYS_MDCNFG_VAL		0x00000aC9 /* Memory timings for the SDRAM.
					      tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */

#define CONFIG_SYS_MDREFR_VAL		0x00403018 /* Initial setting, individual	*/
					   /* bits set in lowlevel_init.S	*/
#define CONFIG_SYS_MDMRS_VAL		0x00000000

#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
#define	CONFIG_SYS_SXCNFG_VAL		0x00000000

/*
 * PCMCIA and CF Interfaces
 */
#define CONFIG_SYS_MECR_VAL		0x00000000  /* Hangover from Lubbock.
					       Needs calculating. (DS/CHC) */
#define CONFIG_SYS_MCMEM0_VAL		0x00010504
#define CONFIG_SYS_MCMEM1_VAL		0x00010504
#define CONFIG_SYS_MCATT0_VAL		0x00010504
#define CONFIG_SYS_MCATT1_VAL		0x00010504
#define CONFIG_SYS_MCIO0_VAL		0x00004715
#define CONFIG_SYS_MCIO1_VAL		0x00004715

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/

/* timeout values are in ticks */
/* FIXME */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/* Flash protection */
#define CONFIG_SYS_FLASH_PROTECTION	1

/* FIXME */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x3C000)	/* Addr of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment */
#define CONFIG_ENV_SECT_SIZE	0x20000

/* Option added to get around byte ordering issues in the flash driver */
#define CONFIG_SYS_LITTLE_ENDIAN	1

#endif	/* __CONFIG_H */
Commit	Line	Data
6310eb9d WD	1	/*
	2	* (C) Copyright 2002
	3	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* Configuration settings for the PLEB 2 board.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
6310eb9d WD	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
	38	#define CONFIG_PLEB2 1 /* on an PLEB2 Board */
	39	#undef CONFIG_LCD
	40	#undef CONFIG_MMC
	41	#define BOARD_LATE_INIT 1
08eb21ee	42	#define CONFIG_SYS_TEXT_BASE 0x0
6310eb9d WD	43
	44	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	45
b3acb6cd	46	/* we will never enable dcache, because we have to setup MMU first */
e47f2db5	47	#define CONFIG_SYS_DCACHE_OFF
b3acb6cd	48
6310eb9d WD	49	/*
	50	* Size of malloc() pool
	51	*/
6d0f6bcf	52	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
6310eb9d WD	53
	54	/*
	55	* Hardware drivers
	56	*/
	57
	58	/* None - PLEB 2 doesn't have any of this.
ac6b362a NM	59	#define CONFIG_LAN91C96
	60	#define CONFIG_LAN91C96_BASE 0x0C000000
	61	*/
6310eb9d WD	62
	63	/*
	64	* select serial console configuration
	65	*/
379be585	66	#define CONFIG_PXA_SERIAL
6310eb9d WD	67	#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */
	68
	69	/* allow to overwrite serial and ethaddr */
	70	#define CONFIG_ENV_OVERWRITE
	71
	72	#define CONFIG_BAUDRATE 115200
	73
6310eb9d	74
079a136c JL	75	/*
	76	* BOOTP options
	77	*/
	78	#define CONFIG_BOOTP_BOOTFILESIZE
	79	#define CONFIG_BOOTP_BOOTPATH
	80	#define CONFIG_BOOTP_GATEWAY
	81	#define CONFIG_BOOTP_HOSTNAME
	82
	83
26a34560 JL	84	/*
	85	* Command line configuration.
	86	*/
	87	#include <config_cmd_default.h>
	88
	89	#undef CONFIG_CMD_NET
6d8962e8	90	#undef CONFIG_CMD_NFS
26a34560	91
6310eb9d WD	92
	93	#define CONFIG_BOOTDELAY 3
	94	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	95	#define CONFIG_NETMASK 255.255.0.0
	96	#define CONFIG_IPADDR 192.168.0.21
	97	#define CONFIG_SERVERIP 192.168.0.250
	98	#define CONFIG_BOOTCOMMAND "bootm 40000"
	99	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"
	100
	101	#define CONFIG_CMDLINE_TAG
	102	#define CONFIG_INITRD_TAG
	103	#define CONFIG_SETUP_MEMORY_TAGS
	104
26a34560	105	#if defined(CONFIG_CMD_KGDB)
6310eb9d WD	106	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	107	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	108	#endif
	109
	110	/*
	111	* Miscellaneous configurable options
	112	*/
6d0f6bcf JCPV	113	#define CONFIG_SYS_HUSH_PARSER 1
6d0f6bcf JCPV	114	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
6310eb9d	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	117	#ifdef CONFIG_SYS_HUSH_PARSER
	118	#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
6310eb9d	119	#else
6d0f6bcf	120	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
6310eb9d	121	#endif
6d0f6bcf JCPV	122	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	123	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	124	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	125	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	126	#define CONFIG_SYS_DEVICE_NULLDEV 1
6310eb9d	127
6d0f6bcf JCPV	128	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
6d0f6bcf JCPV	129	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
6310eb9d	130
6d0f6bcf	131	#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
6310eb9d	132
94a33129	133	#define CONFIG_SYS_HZ 1000
6d0f6bcf	134	#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
6310eb9d WD	135
6310eb9d WD	136	/* valid baudrates */
6d0f6bcf	137	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
6310eb9d	138
b03d92e5 JCPV	139	#ifdef CONFIG_MMC
	140	#define CONFIG_PXA_MMC
	141	#define CONFIG_CMD_MMC
	142	#endif
	143
6310eb9d WD	144	/*
	145	* Stack sizes
	146	*
	147	* The stack sizes are set up in start.S using the settings below
	148	*/
	149	#define CONFIG_STACKSIZE (1281024) / regular stack */
	150	#ifdef CONFIG_USE_IRQ
	151	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	152	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	153	#endif
	154
	155	/*
	156	* Physical Memory Map
	157	*/
08eb21ee	158	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
6310eb9d WD	159	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
6310eb9d WD	160	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
6310eb9d WD	161
	162	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	163	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
	164	#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */
	165
	166	/* Not entirely sure about this - DS/CHC */
	167	#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
	168	#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1
6d0f6bcf JCPV	171	#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
6310eb9d	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
6d0f6bcf JCPV	174	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6310eb9d	175
6ef6eb91	176	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
25ddd1fb	177	#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
6ef6eb91	178
6310eb9d WD	179	/*
	180	* GPIO settings
	181	*/
6d0f6bcf JCPV	182	#define CONFIG_SYS_GPSR0_VAL 0x00000000 /* Don't set anything */
	183	#define CONFIG_SYS_GPSR1_VAL 0x00000080
	184	#define CONFIG_SYS_GPSR2_VAL 0x00000000
6310eb9d	185
6d0f6bcf JCPV	186	#define CONFIG_SYS_GPCR0_VAL 0x00000000 /* Don't clear anything */
	187	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	188	#define CONFIG_SYS_GPCR2_VAL 0x00000000
6310eb9d	189
6d0f6bcf JCPV	190	#define CONFIG_SYS_GPDR0_VAL 0x00000000
	191	#define CONFIG_SYS_GPDR1_VAL 0x000007C3
	192	#define CONFIG_SYS_GPDR2_VAL 0x00000000
6310eb9d WD	193
6310eb9d WD	194	/* Edge detect registers (these are set by the kernel) */
6d0f6bcf JCPV	195	#define CONFIG_SYS_GRER0_VAL 0x00000000
	196	#define CONFIG_SYS_GRER1_VAL 0x00000000
	197	#define CONFIG_SYS_GRER2_VAL 0x00000000
	198	#define CONFIG_SYS_GFER0_VAL 0x00000000
	199	#define CONFIG_SYS_GFER1_VAL 0x00000000
	200	#define CONFIG_SYS_GFER2_VAL 0x00000000
	201
	202	#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
	203	#define CONFIG_SYS_GAFR0_U_VAL 0x00000000
	204	#define CONFIG_SYS_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */
	205	#define CONFIG_SYS_GAFR1_U_VAL 0x00000000
	206	#define CONFIG_SYS_GAFR2_L_VAL 0x00000000
	207	#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
	208
	209	#define CONFIG_SYS_PSSR_VAL 0x20
08eb21ee MV	210	#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
	211	#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
	212	#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
6310eb9d WD	213
	214	/*
	215	* Memory settings
	216	*/
6d0f6bcf JCPV	217	#define CONFIG_SYS_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */
	218	#define CONFIG_SYS_MSC1_VAL 0x00000000
	219	#define CONFIG_SYS_MSC2_VAL 0x00000000
6310eb9d	220
6d0f6bcf	221	#define CONFIG_SYS_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM.
6310eb9d WD	222	tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
6310eb9d WD	223
6d0f6bcf	224	#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual */
400558b5	225	/* bits set in lowlevel_init.S */
6d0f6bcf	226	#define CONFIG_SYS_MDMRS_VAL 0x00000000
6310eb9d	227
08eb21ee MV	228	#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
	229	#define CONFIG_SYS_SXCNFG_VAL 0x00000000
	230
6310eb9d WD	231	/*
	232	* PCMCIA and CF Interfaces
	233	*/
6d0f6bcf	234	#define CONFIG_SYS_MECR_VAL 0x00000000 /* Hangover from Lubbock.
6310eb9d	235	Needs calculating. (DS/CHC) */
6d0f6bcf JCPV	236	#define CONFIG_SYS_MCMEM0_VAL 0x00010504
	237	#define CONFIG_SYS_MCMEM1_VAL 0x00010504
	238	#define CONFIG_SYS_MCATT0_VAL 0x00010504
	239	#define CONFIG_SYS_MCATT1_VAL 0x00010504
	240	#define CONFIG_SYS_MCIO0_VAL 0x00004715
	241	#define CONFIG_SYS_MCIO1_VAL 0x00004715
6310eb9d WD	242
	243	/*
	244	* FLASH and environment organization
	245	*/
6d0f6bcf JCPV	246	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	247	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
6310eb9d WD	248
	249	/* timeout values are in ticks */
	250	/* FIXME */
6d0f6bcf JCPV	251	#define CONFIG_SYS_FLASH_ERASE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	252	#define CONFIG_SYS_FLASH_WRITE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Write */
6310eb9d WD	253
6310eb9d WD	254	/* Flash protection */
6d0f6bcf	255	#define CONFIG_SYS_FLASH_PROTECTION 1
6310eb9d WD	256
6310eb9d WD	257	/* FIXME */
5a1aceb0	258	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	259	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */
	260	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
	261	#define CONFIG_ENV_SECT_SIZE 0x20000
6310eb9d WD	262
6310eb9d WD	263	/* Option added to get around byte ordering issues in the flash driver */
6d0f6bcf	264	#define CONFIG_SYS_LITTLE_ENDIAN 1
6310eb9d WD	265
6310eb9d WD	266	#endif /* __CONFIG_H */