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32949232 II |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
32949232 II |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * Ilko Iliev <www.ronetix.at> | |
6 | * | |
7 | * Configuation settings for the RONETIX PM9261 board. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
32949232 II |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
f47316a8 AD |
15 | /* |
16 | * SoC must be defined first, before hardware.h is included. | |
17 | * In this case SoC is defined in boards.cfg. | |
18 | */ | |
19 | ||
20 | #include <asm/hardware.h> | |
32949232 | 21 | /* ARM asynchronous clock */ |
32949232 | 22 | |
ebf7bef1 | 23 | |
32949232 II |
24 | #define CONFIG_DISPLAY_BOARDINFO |
25 | ||
26 | #define MASTER_PLL_DIV 15 | |
27 | #define MASTER_PLL_MUL 162 | |
28 | #define MAIN_PLL_DIV 2 | |
f47316a8 | 29 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
7c966a8b | 30 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 |
32949232 | 31 | |
f47316a8 | 32 | #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" |
32949232 II |
33 | #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ |
34 | #define CONFIG_ARCH_CPU_INIT | |
4f81bf43 | 35 | #define CONFIG_SYS_TEXT_BASE 0 |
32949232 | 36 | |
a3e09cc2 AD |
37 | #define MACH_TYPE_PM9261 1187 |
38 | #define CONFIG_MACH_TYPE MACH_TYPE_PM9261 | |
39 | ||
32949232 II |
40 | /* clocks */ |
41 | /* CKGR_MOR - enable main osc. */ | |
42 | #define CONFIG_SYS_MOR_VAL \ | |
e3150c77 | 43 | (AT91_PMC_MOR_MOSCEN | \ |
32949232 II |
44 | (255 << 8)) /* Main Oscillator Start-up Time */ |
45 | #define CONFIG_SYS_PLLAR_VAL \ | |
e3150c77 AD |
46 | (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ |
47 | AT91_PMC_PLLXR_OUT(3) | \ | |
32949232 II |
48 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) |
49 | ||
50 | /* PCK/2 = MCK Master Clock from PLLA */ | |
51 | #define CONFIG_SYS_MCKR1_VAL \ | |
e3150c77 AD |
52 | (AT91_PMC_MCKR_CSS_SLOW | \ |
53 | AT91_PMC_MCKR_PRES_1 | \ | |
7ac2e7c1 | 54 | AT91_PMC_MCKR_MDIV_2) |
32949232 II |
55 | |
56 | /* PCK/2 = MCK Master Clock from PLLA */ | |
57 | #define CONFIG_SYS_MCKR2_VAL \ | |
e3150c77 AD |
58 | (AT91_PMC_MCKR_CSS_PLLA | \ |
59 | AT91_PMC_MCKR_PRES_1 | \ | |
7ac2e7c1 | 60 | AT91_PMC_MCKR_MDIV_2) |
32949232 II |
61 | |
62 | /* define PDC[31:16] as DATA[31:16] */ | |
63 | #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 | |
64 | /* no pull-up for D[31:16] */ | |
65 | #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 | |
66 | ||
67 | /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ | |
68 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ | |
e3150c77 | 69 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) |
32949232 II |
70 | |
71 | /* SDRAM */ | |
72 | /* SDRAMC_MR Mode register */ | |
73 | #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL | |
74 | /* SDRAMC_TR - Refresh Timer register */ | |
75 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C | |
76 | /* SDRAMC_CR - Configuration register*/ | |
77 | #define CONFIG_SYS_SDRC_CR_VAL \ | |
78 | (AT91_SDRAMC_NC_9 | \ | |
79 | AT91_SDRAMC_NR_13 | \ | |
80 | AT91_SDRAMC_NB_4 | \ | |
81 | AT91_SDRAMC_CAS_3 | \ | |
82 | AT91_SDRAMC_DBW_32 | \ | |
83 | (1 << 8) | /* Write Recovery Delay */ \ | |
84 | (7 << 12) | /* Row Cycle Delay */ \ | |
85 | (3 << 16) | /* Row Precharge Delay */ \ | |
86 | (2 << 20) | /* Row to Column Delay */ \ | |
87 | (5 << 24) | /* Active to Precharge Delay */ \ | |
88 | (1 << 28)) /* Exit Self Refresh to Active Delay */ | |
89 | ||
90 | /* Memory Device Register -> SDRAM */ | |
91 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM | |
92 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
93 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ | |
94 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH | |
95 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ | |
96 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
97 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
98 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
99 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
100 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
101 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
102 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
103 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR | |
104 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ | |
105 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL | |
106 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ | |
107 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
108 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
109 | ||
110 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | |
111 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ | |
e3150c77 AD |
112 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
113 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) | |
32949232 | 114 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
e3150c77 AD |
115 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
116 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) | |
32949232 | 117 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
e3150c77 | 118 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
32949232 | 119 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
e3150c77 AD |
120 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
121 | AT91_SMC_MODE_DBW_16 | \ | |
122 | AT91_SMC_MODE_TDF | \ | |
123 | AT91_SMC_MODE_TDF_CYCLE(6)) | |
32949232 II |
124 | |
125 | /* user reset enable */ | |
126 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
127 | (AT91_RSTC_KEY | \ | |
e3150c77 AD |
128 | AT91_RSTC_CR_PROCRST | \ |
129 | AT91_RSTC_MR_ERSTL(1) | \ | |
130 | AT91_RSTC_MR_ERSTL(2)) | |
32949232 II |
131 | |
132 | /* Disable Watchdog */ | |
133 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
e3150c77 AD |
134 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
135 | AT91_WDT_MR_WDV(0xfff) | \ | |
136 | AT91_WDT_MR_WDDIS | \ | |
137 | AT91_WDT_MR_WDD(0xfff)) | |
32949232 II |
138 | |
139 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
140 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
141 | #define CONFIG_INITRD_TAG 1 | |
142 | ||
143 | #undef CONFIG_SKIP_LOWLEVEL_INIT | |
0160c1e1 | 144 | #define CONFIG_BOARD_EARLY_INIT_F |
32949232 II |
145 | |
146 | /* | |
147 | * Hardware drivers | |
148 | */ | |
ea8fbba7 | 149 | #define CONFIG_AT91_GPIO 1 |
32949232 | 150 | #define CONFIG_ATMEL_USART 1 |
f47316a8 AD |
151 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
152 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
32949232 II |
153 | |
154 | /* LCD */ | |
155 | #define CONFIG_LCD 1 | |
156 | #define LCD_BPP LCD_COLOR8 | |
157 | #define CONFIG_LCD_LOGO 1 | |
158 | #undef LCD_TEST_PATTERN | |
159 | #define CONFIG_LCD_INFO 1 | |
160 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
161 | #define CONFIG_SYS_WHITE_ON_BLACK 1 | |
162 | #define CONFIG_ATMEL_LCD 1 | |
163 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
164 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
165 | ||
166 | /* LED */ | |
167 | #define CONFIG_AT91_LED | |
bcf9fe37 AB |
168 | #define CONFIG_RED_LED GPIO_PIN_PC(12) |
169 | #define CONFIG_GREEN_LED GPIO_PIN_PC(13) | |
170 | #define CONFIG_YELLOW_LED GPIO_PIN_PC(15) | |
32949232 II |
171 | |
172 | #define CONFIG_BOOTDELAY 3 | |
173 | ||
174 | /* | |
175 | * BOOTP options | |
176 | */ | |
177 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
178 | #define CONFIG_BOOTP_BOOTPATH 1 | |
179 | #define CONFIG_BOOTP_GATEWAY 1 | |
180 | #define CONFIG_BOOTP_HOSTNAME 1 | |
181 | ||
182 | /* | |
183 | * Command line configuration. | |
184 | */ | |
6741b531 | 185 | #define CONFIG_CMD_CACHE |
32949232 II |
186 | #define CONFIG_CMD_PING 1 |
187 | #define CONFIG_CMD_DHCP 1 | |
188 | #define CONFIG_CMD_NAND 1 | |
189 | #define CONFIG_CMD_USB 1 | |
190 | ||
191 | /* SDRAM */ | |
192 | #define CONFIG_NR_DRAM_BANKS 1 | |
193 | #define PHYS_SDRAM 0x20000000 | |
194 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
195 | ||
196 | /* DataFlash */ | |
197 | #define CONFIG_ATMEL_DATAFLASH_SPI | |
198 | #define CONFIG_HAS_DATAFLASH | |
32949232 II |
199 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 |
200 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | |
201 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ | |
202 | #define AT91_SPI_CLK 15000000 | |
203 | #define DATAFLASH_TCSS (0x1a << 16) | |
204 | #define DATAFLASH_TCHS (0x1 << 24) | |
205 | ||
206 | /* NAND flash */ | |
207 | #define CONFIG_NAND_ATMEL | |
32949232 II |
208 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
209 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
210 | #define CONFIG_SYS_NAND_DBW_8 1 | |
211 | /* our ALE is AD22 */ | |
212 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) | |
213 | /* our CLE is AD21 */ | |
214 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) | |
ac45bb16 AB |
215 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) |
216 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) | |
32949232 | 217 | |
32949232 II |
218 | /* NOR flash */ |
219 | #define CONFIG_SYS_FLASH_CFI 1 | |
220 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
221 | #define PHYS_FLASH_1 0x10000000 | |
222 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
223 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
224 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
225 | ||
226 | /* Ethernet */ | |
227 | #define CONFIG_DRIVER_DM9000 1 | |
228 | #define CONFIG_DM9000_BASE 0x30000000 | |
229 | #define DM9000_IO CONFIG_DM9000_BASE | |
230 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
231 | #define CONFIG_DM9000_USE_16BIT 1 | |
232 | #define CONFIG_NET_RETRY_COUNT 20 | |
233 | #define CONFIG_RESET_PHY_R 1 | |
234 | ||
235 | /* USB */ | |
236 | #define CONFIG_USB_ATMEL | |
dcd2f1a0 | 237 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
32949232 II |
238 | #define CONFIG_USB_OHCI_NEW 1 |
239 | #define CONFIG_DOS_PARTITION 1 | |
240 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
241 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 | |
242 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" | |
243 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
244 | #define CONFIG_USB_STORAGE 1 | |
245 | ||
246 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 | |
247 | ||
248 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
249 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
250 | ||
251 | #undef CONFIG_SYS_USE_DATAFLASH_CS0 | |
252 | #undef CONFIG_SYS_USE_NANDFLASH | |
253 | #define CONFIG_SYS_USE_FLASH 1 | |
254 | ||
255 | #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 | |
256 | ||
257 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
258 | #define CONFIG_ENV_IS_IN_DATAFLASH 1 | |
259 | #define CONFIG_SYS_MONITOR_BASE \ | |
260 | (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) | |
261 | #define CONFIG_ENV_OFFSET 0x4200 | |
262 | #define CONFIG_ENV_ADDR \ | |
263 | (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) | |
264 | #define CONFIG_ENV_SIZE 0x4200 | |
265 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" | |
266 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
267 | "root=/dev/mtdblock0 " \ | |
918319c7 | 268 | "mtdparts=atmel_nand:-(root) " \ |
32949232 II |
269 | "rw rootfstype=jffs2" |
270 | ||
271 | #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ | |
272 | ||
273 | /* bootstrap + u-boot + env + linux in nandflash */ | |
274 | #define CONFIG_ENV_IS_IN_NAND 1 | |
275 | #define CONFIG_ENV_OFFSET 0x60000 | |
276 | #define CONFIG_ENV_OFFSET_REDUND 0x80000 | |
277 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | |
278 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" | |
279 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
280 | "root=/dev/mtdblock5 " \ | |
918319c7 | 281 | "mtdparts=atmel_nand:128k(bootstrap)ro," \ |
32949232 II |
282 | "256k(uboot)ro,128k(env1)ro," \ |
283 | "128k(env2)ro,2M(linux),-(root) " \ | |
284 | "rw rootfstype=jffs2" | |
285 | ||
286 | #elif defined (CONFIG_SYS_USE_FLASH) | |
287 | ||
288 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
289 | #define CONFIG_ENV_OFFSET 0x40000 | |
290 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
291 | #define CONFIG_ENV_SIZE 0x10000 | |
292 | #define CONFIG_ENV_OVERWRITE 1 | |
293 | ||
294 | /* JFFS Partition offset set */ | |
295 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 | |
296 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
297 | ||
298 | /* 512k reserved for u-boot */ | |
299 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 | |
300 | ||
301 | #define CONFIG_BOOTCOMMAND "run flashboot" | |
302 | ||
303 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" | |
304 | #define MTDPARTS_DEFAULT \ | |
305 | "mtdparts=physmap-flash.0:" \ | |
306 | "256k(u-boot)ro," \ | |
307 | "64k(u-boot-env)ro," \ | |
308 | "1408k(kernel)," \ | |
309 | "-(rootfs);" \ | |
310 | "nand:-(nand)" | |
311 | ||
312 | #define CONFIG_CON_ROT "fbcon=rotate:3 " | |
313 | #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT | |
314 | ||
315 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
316 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
317 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
318 | "partition=nand0,0\0" \ | |
319 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ | |
320 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
321 | CONFIG_CON_ROT \ | |
322 | "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ | |
323 | "addip=setenv bootargs $(bootargs) " \ | |
324 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ | |
325 | ":$(hostname):eth0:off\0" \ | |
326 | "ramboot=tftpboot 0x22000000 vmImage;" \ | |
327 | "run ramargs;run addip;bootm 22000000\0" \ | |
328 | "nfsboot=tftpboot 0x22000000 vmImage;" \ | |
329 | "run nfsargs;run addip;bootm 22000000\0" \ | |
330 | "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ | |
331 | "" | |
332 | #else | |
333 | #error "Undefined memory device" | |
334 | #endif | |
335 | ||
336 | #define CONFIG_BAUDRATE 115200 | |
32949232 | 337 | |
32949232 II |
338 | #define CONFIG_SYS_CBSIZE 256 |
339 | #define CONFIG_SYS_MAXARGS 16 | |
340 | #define CONFIG_SYS_PBSIZE \ | |
341 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
342 | #define CONFIG_SYS_LONGHELP 1 | |
343 | #define CONFIG_CMDLINE_EDITING 1 | |
344 | ||
32949232 II |
345 | /* |
346 | * Size of malloc() pool | |
347 | */ | |
348 | #define CONFIG_SYS_MALLOC_LEN \ | |
349 | ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) | |
32949232 | 350 | |
4f81bf43 AD |
351 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
352 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
353 | GENERATED_GBL_DATA_SIZE) | |
354 | ||
32949232 | 355 | #endif |