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32949232 II |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
32949232 II |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * Ilko Iliev <www.ronetix.at> | |
6 | * | |
7 | * Configuation settings for the RONETIX PM9261 board. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
32949232 II |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
f47316a8 AD |
15 | /* |
16 | * SoC must be defined first, before hardware.h is included. | |
17 | * In this case SoC is defined in boards.cfg. | |
18 | */ | |
19 | ||
20 | #include <asm/hardware.h> | |
32949232 | 21 | /* ARM asynchronous clock */ |
32949232 | 22 | |
32949232 II |
23 | #define MASTER_PLL_DIV 15 |
24 | #define MASTER_PLL_MUL 162 | |
25 | #define MAIN_PLL_DIV 2 | |
f47316a8 | 26 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
7c966a8b | 27 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 |
32949232 | 28 | |
f47316a8 | 29 | #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" |
32949232 II |
30 | #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ |
31 | #define CONFIG_ARCH_CPU_INIT | |
32949232 | 32 | |
a3e09cc2 AD |
33 | #define CONFIG_MACH_TYPE MACH_TYPE_PM9261 |
34 | ||
32949232 II |
35 | /* clocks */ |
36 | /* CKGR_MOR - enable main osc. */ | |
37 | #define CONFIG_SYS_MOR_VAL \ | |
e3150c77 | 38 | (AT91_PMC_MOR_MOSCEN | \ |
32949232 II |
39 | (255 << 8)) /* Main Oscillator Start-up Time */ |
40 | #define CONFIG_SYS_PLLAR_VAL \ | |
e3150c77 AD |
41 | (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ |
42 | AT91_PMC_PLLXR_OUT(3) | \ | |
32949232 II |
43 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) |
44 | ||
45 | /* PCK/2 = MCK Master Clock from PLLA */ | |
46 | #define CONFIG_SYS_MCKR1_VAL \ | |
e3150c77 AD |
47 | (AT91_PMC_MCKR_CSS_SLOW | \ |
48 | AT91_PMC_MCKR_PRES_1 | \ | |
7ac2e7c1 | 49 | AT91_PMC_MCKR_MDIV_2) |
32949232 II |
50 | |
51 | /* PCK/2 = MCK Master Clock from PLLA */ | |
52 | #define CONFIG_SYS_MCKR2_VAL \ | |
e3150c77 AD |
53 | (AT91_PMC_MCKR_CSS_PLLA | \ |
54 | AT91_PMC_MCKR_PRES_1 | \ | |
7ac2e7c1 | 55 | AT91_PMC_MCKR_MDIV_2) |
32949232 II |
56 | |
57 | /* define PDC[31:16] as DATA[31:16] */ | |
58 | #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 | |
59 | /* no pull-up for D[31:16] */ | |
60 | #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 | |
61 | ||
62 | /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ | |
63 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ | |
e3150c77 | 64 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) |
32949232 II |
65 | |
66 | /* SDRAM */ | |
67 | /* SDRAMC_MR Mode register */ | |
68 | #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL | |
69 | /* SDRAMC_TR - Refresh Timer register */ | |
70 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C | |
71 | /* SDRAMC_CR - Configuration register*/ | |
72 | #define CONFIG_SYS_SDRC_CR_VAL \ | |
73 | (AT91_SDRAMC_NC_9 | \ | |
74 | AT91_SDRAMC_NR_13 | \ | |
75 | AT91_SDRAMC_NB_4 | \ | |
76 | AT91_SDRAMC_CAS_3 | \ | |
77 | AT91_SDRAMC_DBW_32 | \ | |
78 | (1 << 8) | /* Write Recovery Delay */ \ | |
79 | (7 << 12) | /* Row Cycle Delay */ \ | |
80 | (3 << 16) | /* Row Precharge Delay */ \ | |
81 | (2 << 20) | /* Row to Column Delay */ \ | |
82 | (5 << 24) | /* Active to Precharge Delay */ \ | |
83 | (1 << 28)) /* Exit Self Refresh to Active Delay */ | |
84 | ||
85 | /* Memory Device Register -> SDRAM */ | |
86 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM | |
87 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
88 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ | |
89 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH | |
90 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ | |
91 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
92 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
93 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
94 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
95 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
96 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
97 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
98 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR | |
99 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ | |
100 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL | |
101 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ | |
102 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
103 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
104 | ||
105 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | |
106 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ | |
e3150c77 AD |
107 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
108 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) | |
32949232 | 109 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
e3150c77 AD |
110 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
111 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) | |
32949232 | 112 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
e3150c77 | 113 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
32949232 | 114 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
e3150c77 AD |
115 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
116 | AT91_SMC_MODE_DBW_16 | \ | |
117 | AT91_SMC_MODE_TDF | \ | |
118 | AT91_SMC_MODE_TDF_CYCLE(6)) | |
32949232 II |
119 | |
120 | /* user reset enable */ | |
121 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
122 | (AT91_RSTC_KEY | \ | |
e3150c77 AD |
123 | AT91_RSTC_CR_PROCRST | \ |
124 | AT91_RSTC_MR_ERSTL(1) | \ | |
125 | AT91_RSTC_MR_ERSTL(2)) | |
32949232 II |
126 | |
127 | /* Disable Watchdog */ | |
128 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
e3150c77 AD |
129 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
130 | AT91_WDT_MR_WDV(0xfff) | \ | |
131 | AT91_WDT_MR_WDDIS | \ | |
132 | AT91_WDT_MR_WDD(0xfff)) | |
32949232 II |
133 | |
134 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
135 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
136 | #define CONFIG_INITRD_TAG 1 | |
137 | ||
138 | #undef CONFIG_SKIP_LOWLEVEL_INIT | |
32949232 II |
139 | |
140 | /* | |
141 | * Hardware drivers | |
142 | */ | |
32949232 II |
143 | |
144 | /* LCD */ | |
32949232 II |
145 | #define LCD_BPP LCD_COLOR8 |
146 | #define CONFIG_LCD_LOGO 1 | |
147 | #undef LCD_TEST_PATTERN | |
148 | #define CONFIG_LCD_INFO 1 | |
149 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
32949232 II |
150 | #define CONFIG_ATMEL_LCD 1 |
151 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
32949232 | 152 | |
32949232 II |
153 | /* |
154 | * BOOTP options | |
155 | */ | |
156 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
157 | #define CONFIG_BOOTP_BOOTPATH 1 | |
158 | #define CONFIG_BOOTP_GATEWAY 1 | |
159 | #define CONFIG_BOOTP_HOSTNAME 1 | |
160 | ||
32949232 II |
161 | /* SDRAM */ |
162 | #define CONFIG_NR_DRAM_BANKS 1 | |
163 | #define PHYS_SDRAM 0x20000000 | |
164 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
165 | ||
32949232 II |
166 | /* NAND flash */ |
167 | #define CONFIG_NAND_ATMEL | |
32949232 II |
168 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
169 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
170 | #define CONFIG_SYS_NAND_DBW_8 1 | |
171 | /* our ALE is AD22 */ | |
172 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) | |
173 | /* our CLE is AD21 */ | |
174 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) | |
ac45bb16 AB |
175 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) |
176 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) | |
32949232 | 177 | |
32949232 II |
178 | /* NOR flash */ |
179 | #define CONFIG_SYS_FLASH_CFI 1 | |
180 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
181 | #define PHYS_FLASH_1 0x10000000 | |
182 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
183 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
184 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
185 | ||
186 | /* Ethernet */ | |
187 | #define CONFIG_DRIVER_DM9000 1 | |
188 | #define CONFIG_DM9000_BASE 0x30000000 | |
189 | #define DM9000_IO CONFIG_DM9000_BASE | |
190 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
191 | #define CONFIG_DM9000_USE_16BIT 1 | |
192 | #define CONFIG_NET_RETRY_COUNT 20 | |
193 | #define CONFIG_RESET_PHY_R 1 | |
194 | ||
195 | /* USB */ | |
196 | #define CONFIG_USB_ATMEL | |
dcd2f1a0 | 197 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
32949232 | 198 | #define CONFIG_USB_OHCI_NEW 1 |
32949232 II |
199 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
200 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 | |
201 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" | |
202 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
32949232 II |
203 | |
204 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 | |
205 | ||
206 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
207 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
208 | ||
209 | #undef CONFIG_SYS_USE_DATAFLASH_CS0 | |
210 | #undef CONFIG_SYS_USE_NANDFLASH | |
211 | #define CONFIG_SYS_USE_FLASH 1 | |
212 | ||
213 | #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 | |
214 | ||
215 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
32949232 | 216 | #define CONFIG_ENV_OFFSET 0x4200 |
32949232 | 217 | #define CONFIG_ENV_SIZE 0x4200 |
c53a825e WY |
218 | #define CONFIG_ENV_SECT_SIZE 0x210 |
219 | #define CONFIG_ENV_SPI_MAX_HZ 15000000 | |
220 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ | |
221 | "sf read 0x22000000 0x84000 0x210000; " \ | |
222 | "bootm 0x22000000" | |
32949232 II |
223 | |
224 | #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ | |
225 | ||
226 | /* bootstrap + u-boot + env + linux in nandflash */ | |
32949232 II |
227 | #define CONFIG_ENV_OFFSET 0x60000 |
228 | #define CONFIG_ENV_OFFSET_REDUND 0x80000 | |
229 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | |
230 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" | |
32949232 II |
231 | |
232 | #elif defined (CONFIG_SYS_USE_FLASH) | |
233 | ||
32949232 II |
234 | #define CONFIG_ENV_OFFSET 0x40000 |
235 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
236 | #define CONFIG_ENV_SIZE 0x10000 | |
237 | #define CONFIG_ENV_OVERWRITE 1 | |
238 | ||
239 | /* JFFS Partition offset set */ | |
240 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 | |
241 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
242 | ||
243 | /* 512k reserved for u-boot */ | |
244 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 | |
245 | ||
246 | #define CONFIG_BOOTCOMMAND "run flashboot" | |
247 | ||
32949232 | 248 | #define CONFIG_CON_ROT "fbcon=rotate:3 " |
32949232 II |
249 | |
250 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
43ede0bc TR |
251 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
252 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ | |
32949232 II |
253 | "partition=nand0,0\0" \ |
254 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ | |
255 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
256 | CONFIG_CON_ROT \ | |
257 | "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ | |
258 | "addip=setenv bootargs $(bootargs) " \ | |
259 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ | |
260 | ":$(hostname):eth0:off\0" \ | |
261 | "ramboot=tftpboot 0x22000000 vmImage;" \ | |
262 | "run ramargs;run addip;bootm 22000000\0" \ | |
263 | "nfsboot=tftpboot 0x22000000 vmImage;" \ | |
264 | "run nfsargs;run addip;bootm 22000000\0" \ | |
265 | "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ | |
266 | "" | |
267 | #else | |
268 | #error "Undefined memory device" | |
269 | #endif | |
270 | ||
32949232 II |
271 | #define CONFIG_SYS_LONGHELP 1 |
272 | #define CONFIG_CMDLINE_EDITING 1 | |
273 | ||
32949232 II |
274 | /* |
275 | * Size of malloc() pool | |
276 | */ | |
277 | #define CONFIG_SYS_MALLOC_LEN \ | |
278 | ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) | |
32949232 | 279 | |
4f81bf43 | 280 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
c53a825e | 281 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ |
4f81bf43 AD |
282 | GENERATED_GBL_DATA_SIZE) |
283 | ||
32949232 | 284 | #endif |