[people/ms/u-boot.git] / include / configs / pm9261.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * Configuation settings for the RONETIX PM9261 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define AT91_CPU_NAME		"AT91SAM9261"

#define CONFIG_DISPLAY_BOARDINFO

#define MASTER_PLL_DIV		15
#define MASTER_PLL_MUL		162
#define MAIN_PLL_DIV		2
#define AT91_MAIN_CLOCK		18432000

#define CONFIG_SYS_HZ		1000

#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
#define CONFIG_AT91SAM9261	1	/* It's an Atmel AT91SAM9261 SoC*/
#define CONFIG_PM9261		1	/* on a Ronetix PM9261 Board	*/
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

/* clocks */
/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_OUT |						\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_CSS_SLOW |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_2 |	\
		 AT91_PMC_PDIV_1)

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_CSS_PLLA |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_2 |	\
		 AT91_PMC_PDIV_1)

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000

/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
       (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_3 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (1 <<  8) |		/* Write Recovery Delay */		\
		 (7 << 12) |		/* Row Cycle Delay */			\
		 (3 << 16) |		/* Row Precharge Delay */		\
		 (2 << 20) |		/* Row to Column Delay */		\
		 (5 << 24) |		/* Active to Precharge Delay */		\
		 (1 << 28))		/* Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
		 AT91_SMC_DBW_16 |				\
		 AT91_SMC_TDFMODE |				\
		 AT91_SMC_TDF_(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_PROCRST |		\
		AT91_RSTC_RSTTYP_WAKEUP |	\
		AT91_RSTC_RSTTYP_WATCHDOG)

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
		 AT91_WDT_WDV |					\
		 AT91_WDT_WDDIS |				\
		 AT91_WDT_WDD)

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#undef CONFIG_SKIP_LOWLEVEL_INIT
#undef CONFIG_SKIP_RELOCATE_UBOOT

/*
 * Hardware drivers
 */
#define CONFIG_ATMEL_USART	1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3		1	/* USART 3 is DBGU */

/* LCD */
#define CONFIG_LCD			1
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_SYS_WHITE_ON_BLACK	1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

/* LED */
#define CONFIG_AT91_LED
#define	CONFIG_RED_LED		AT91_PIN_PC12
#define	CONFIG_GREEN_LED	AT91_PIN_PC13
#define	CONFIG_YELLOW_LED	AT91_PIN_PC15

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1
#define CONFIG_BOOTP_BOOTPATH		1
#define CONFIG_BOOTP_GATEWAY		1
#define CONFIG_BOOTP_HOSTNAME		1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS

#define CONFIG_CMD_PING		1
#define CONFIG_CMD_DHCP		1
#define CONFIG_CMD_NAND		1
#define CONFIG_CMD_USB		1

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS			1
#define PHYS_SDRAM				0x20000000
#define PHYS_SDRAM_SIZE				0x04000000	/* 64 megs */

/* DataFlash */
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_HAS_DATAFLASH
#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
#define AT91_SPI_CLK				15000000
#define DATAFLASH_TCSS				(0x1a << 16)
#define DATAFLASH_TCHS				(0x1 << 24)

/* NAND flash */
#define CONFIG_NAND_ATMEL
#define NAND_MAX_CHIPS				1
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA16

#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */


/* NOR flash */
#define CONFIG_SYS_FLASH_CFI			1
#define CONFIG_FLASH_CFI_DRIVER			1
#define PHYS_FLASH_1				0x10000000
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		256
#define CONFIG_SYS_MAX_FLASH_BANKS		1

/* Ethernet */
#define CONFIG_DRIVER_DM9000			1
#define CONFIG_DM9000_BASE			0x30000000
#define DM9000_IO				CONFIG_DM9000_BASE
#define DM9000_DATA				(CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT			1
#define CONFIG_NET_RETRY_COUNT			20
#define CONFIG_RESET_PHY_R			1
#define CONFIG_NET_MULTI

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW			1
#define CONFIG_DOS_PARTITION			1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE			1

#define CONFIG_SYS_LOAD_ADDR			0x22000000

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#undef CONFIG_SYS_USE_DATAFLASH_CS0
#undef CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SYS_USE_FLASH	1

#ifdef CONFIG_SYS_USE_DATAFLASH_CS0

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_IS_IN_DATAFLASH	1
#define CONFIG_SYS_MONITOR_BASE		\
		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_ADDR		\
		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock0 "			\
				"mtdparts=atmel_nand:-(root) "		\
				"rw rootfstype=jffs2"

#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND		1
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock5 "			\
				"mtdparts=atmel_nand:128k(bootstrap)ro,"	\
				"256k(uboot)ro,128k(env1)ro,"		\
				"128k(env2)ro,2M(linux),-(root) "	\
				"rw rootfstype=jffs2"

#elif defined (CONFIG_SYS_USE_FLASH)

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET	0x40000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define	CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_OVERWRITE	1

/* JFFS Partition offset set */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11

#define CONFIG_BOOTCOMMAND	"run flashboot"

#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=nand"
#define MTDPARTS_DEFAULT		\
	"mtdparts=physmap-flash.0:"	\
		"256k(u-boot)ro,"	\
		"64k(u-boot-env)ro,"	\
		"1408k(kernel),"	\
		"-(rootfs);"		\
	"nand:-(nand)"

#define CONFIG_CON_ROT "fbcon=rotate:3 "
#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
		CONFIG_CON_ROT					\
		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
	"addip=setenv bootargs $(bootargs) "			\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
		":$(hostname):eth0:off\0"			\
	"ramboot=tftpboot 0x22000000 vmImage;"			\
		"run ramargs;run addip;bootm 22000000\0"	\
	"nfsboot=tftpboot 0x22000000 vmImage;"			\
		"run nfsargs;run addip;bootm 22000000\0"	\
	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
	""
#else
#error "Undefined memory device"
#endif

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#define CONFIG_SYS_PROMPT		"pm9261> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		\
		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
#define CONFIG_SYS_GBL_DATA_SIZE	128

#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
32949232 II	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Ilko Iliev <www.ronetix.at>
	6	*
	7	* Configuation settings for the RONETIX PM9261 board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/* ARM asynchronous clock */
	32	#define AT91_CPU_NAME "AT91SAM9261"
	33
	34	#define CONFIG_DISPLAY_BOARDINFO
	35
	36	#define MASTER_PLL_DIV 15
	37	#define MASTER_PLL_MUL 162
	38	#define MAIN_PLL_DIV 2
	39	#define AT91_MAIN_CLOCK 18432000
	40
	41	#define CONFIG_SYS_HZ 1000
	42
	43	#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
	44	#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
	45	#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
	46	#define CONFIG_ARCH_CPU_INIT
	47	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	48
	49	/* clocks */
	50	/* CKGR_MOR - enable main osc. */
	51	#define CONFIG_SYS_MOR_VAL \
	52	(AT91_PMC_MOSCEN \| \
	53	(255 << 8)) /* Main Oscillator Start-up Time */
	54	#define CONFIG_SYS_PLLAR_VAL \
	55	(AT91_PMC_PLLA_WR_ERRATA \| /* Bit 29 must be 1 when prog */ \
	56	AT91_PMC_OUT \| \
	57	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
	58
	59	/* PCK/2 = MCK Master Clock from PLLA */
	60	#define CONFIG_SYS_MCKR1_VAL \
	61	(AT91_PMC_CSS_SLOW \| \
	62	AT91_PMC_PRES_1 \| \
	63	AT91SAM9_PMC_MDIV_2 \| \
	64	AT91_PMC_PDIV_1)
65
66	/* PCK/2 = MCK Master Clock from PLLA */
67	#define CONFIG_SYS_MCKR2_VAL \
68	(AT91_PMC_CSS_PLLA \| \
69	AT91_PMC_PRES_1 \| \
70	AT91SAM9_PMC_MDIV_2 \| \
71	AT91_PMC_PDIV_1)
72
73	/* define PDC[31:16] as DATA[31:16] */
74	#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
75	/* no pull-up for D[31:16] */
76	#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
77
78	/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
79	#define CONFIG_SYS_MATRIX_EBICSA_VAL \
80	(AT91_MATRIX_DBPUC \| AT91_MATRIX_CS1A_SDRAMC)
81
82	/* SDRAM */
83	/* SDRAMC_MR Mode register */
84	#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
85	/* SDRAMC_TR - Refresh Timer register */
86	#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
87	/* SDRAMC_CR - Configuration register*/
88	#define CONFIG_SYS_SDRC_CR_VAL \
89	(AT91_SDRAMC_NC_9 \| \
90	AT91_SDRAMC_NR_13 \| \
91	AT91_SDRAMC_NB_4 \| \
92	AT91_SDRAMC_CAS_3 \| \
93	AT91_SDRAMC_DBW_32 \| \
94	(1 << 8) \| /* Write Recovery Delay */ \
95	(7 << 12) \| /* Row Cycle Delay */ \
96	(3 << 16) \| /* Row Precharge Delay */ \
97	(2 << 20) \| /* Row to Column Delay */ \
98	(5 << 24) \| /* Active to Precharge Delay */ \
99	(1 << 28)) /* Exit Self Refresh to Active Delay */
100
101	/* Memory Device Register -> SDRAM */
102	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
103	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
104	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
105	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
106	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
107	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
108	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
109	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
110	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
111	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
112	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
113	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
114	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
115	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
116	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
117	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
118	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
119	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
120
121	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
122	#define CONFIG_SYS_SMC0_SETUP0_VAL \
123	(AT91_SMC_NWESETUP_(10) \| AT91_SMC_NCS_WRSETUP_(10) \| \
124	AT91_SMC_NRDSETUP_(10) \| AT91_SMC_NCS_RDSETUP_(10))
125	#define CONFIG_SYS_SMC0_PULSE0_VAL \
126	(AT91_SMC_NWEPULSE_(11) \| AT91_SMC_NCS_WRPULSE_(11) \| \
127	AT91_SMC_NRDPULSE_(11) \| AT91_SMC_NCS_RDPULSE_(11))
128	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
129	(AT91_SMC_NWECYCLE_(22) \| AT91_SMC_NRDCYCLE_(22))
130	#define CONFIG_SYS_SMC0_MODE0_VAL \
131	(AT91_SMC_READMODE \| AT91_SMC_WRITEMODE \| \
132	AT91_SMC_DBW_16 \| \
133	AT91_SMC_TDFMODE \| \
134	AT91_SMC_TDF_(6))
135
136	/* user reset enable */
137	#define CONFIG_SYS_RSTC_RMR_VAL \
138	(AT91_RSTC_KEY \| \
139	AT91_RSTC_PROCRST \| \
140	AT91_RSTC_RSTTYP_WAKEUP \| \
141	AT91_RSTC_RSTTYP_WATCHDOG)
142
143	/* Disable Watchdog */
144	#define CONFIG_SYS_WDTC_WDMR_VAL \
145	(AT91_WDT_WDIDLEHLT \| AT91_WDT_WDDBGHLT \| \
146	AT91_WDT_WDV \| \
147	AT91_WDT_WDDIS \| \
148	AT91_WDT_WDD)
149
150	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
151	#define CONFIG_SETUP_MEMORY_TAGS 1
152	#define CONFIG_INITRD_TAG 1
153
154	#undef CONFIG_SKIP_LOWLEVEL_INIT
155	#undef CONFIG_SKIP_RELOCATE_UBOOT
156
157	/*
158	* Hardware drivers
159	*/
160	#define CONFIG_ATMEL_USART 1
161	#undef CONFIG_USART0
162	#undef CONFIG_USART1
163	#undef CONFIG_USART2
164	#define CONFIG_USART3 1 /* USART 3 is DBGU */
165
166	/* LCD */
167	#define CONFIG_LCD 1
168	#define LCD_BPP LCD_COLOR8
169	#define CONFIG_LCD_LOGO 1
170	#undef LCD_TEST_PATTERN
171	#define CONFIG_LCD_INFO 1
172	#define CONFIG_LCD_INFO_BELOW_LOGO 1
173	#define CONFIG_SYS_WHITE_ON_BLACK 1
174	#define CONFIG_ATMEL_LCD 1
175	#define CONFIG_ATMEL_LCD_BGR555 1
176	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
177
178	/* LED */
179	#define CONFIG_AT91_LED
180	#define CONFIG_RED_LED AT91_PIN_PC12
181	#define CONFIG_GREEN_LED AT91_PIN_PC13
182	#define CONFIG_YELLOW_LED AT91_PIN_PC15
183
184	#define CONFIG_BOOTDELAY 3
185
186	/*
187	* BOOTP options
188	*/
189	#define CONFIG_BOOTP_BOOTFILESIZE 1
190	#define CONFIG_BOOTP_BOOTPATH 1
191	#define CONFIG_BOOTP_GATEWAY 1
192	#define CONFIG_BOOTP_HOSTNAME 1
193
194	/*
195	* Command line configuration.
196	*/
197	#include <config_cmd_default.h>
198	#undef CONFIG_CMD_BDI
199	#undef CONFIG_CMD_IMI
200	#undef CONFIG_CMD_AUTOSCRIPT
201	#undef CONFIG_CMD_FPGA
202	#undef CONFIG_CMD_LOADS
203	#undef CONFIG_CMD_IMLS
204
205	#define CONFIG_CMD_PING 1
206	#define CONFIG_CMD_DHCP 1
207	#define CONFIG_CMD_NAND 1
208	#define CONFIG_CMD_USB 1
209
210	/* SDRAM */
211	#define CONFIG_NR_DRAM_BANKS 1
212	#define PHYS_SDRAM 0x20000000
213	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
214
215	/* DataFlash */
216	#define CONFIG_ATMEL_DATAFLASH_SPI
217	#define CONFIG_HAS_DATAFLASH
218	#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
219	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
220	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
221	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
222	#define AT91_SPI_CLK 15000000
223	#define DATAFLASH_TCSS (0x1a << 16)
224	#define DATAFLASH_TCHS (0x1 << 24)
225
226	/* NAND flash */
227	#define CONFIG_NAND_ATMEL
228	#define NAND_MAX_CHIPS 1
229	#define CONFIG_SYS_MAX_NAND_DEVICE 1
230	#define CONFIG_SYS_NAND_BASE 0x40000000
231	#define CONFIG_SYS_NAND_DBW_8 1
232	/* our ALE is AD22 */
233	#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
234	/* our CLE is AD21 */
235	#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
236	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
237	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
238
2eb99ca8 WD	239	#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
2eb99ca8 WD	240
32949232 II	241
	242	/* NOR flash */
	243	#define CONFIG_SYS_FLASH_CFI 1
	244	#define CONFIG_FLASH_CFI_DRIVER 1
	245	#define PHYS_FLASH_1 0x10000000
	246	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	247	#define CONFIG_SYS_MAX_FLASH_SECT 256
	248	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	249
	250	/* Ethernet */
	251	#define CONFIG_DRIVER_DM9000 1
	252	#define CONFIG_DM9000_BASE 0x30000000
	253	#define DM9000_IO CONFIG_DM9000_BASE
	254	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	255	#define CONFIG_DM9000_USE_16BIT 1
	256	#define CONFIG_NET_RETRY_COUNT 20
	257	#define CONFIG_RESET_PHY_R 1
c8badbe5	258	#define CONFIG_NET_MULTI
32949232 II	259
	260	/* USB */
	261	#define CONFIG_USB_ATMEL
	262	#define CONFIG_USB_OHCI_NEW 1
	263	#define CONFIG_DOS_PARTITION 1
	264	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	265	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
	266	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
	267	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
	268	#define CONFIG_USB_STORAGE 1
	269
	270	#define CONFIG_SYS_LOAD_ADDR 0x22000000
	271
	272	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
	273	#define CONFIG_SYS_MEMTEST_END 0x23e00000
	274
	275	#undef CONFIG_SYS_USE_DATAFLASH_CS0
	276	#undef CONFIG_SYS_USE_NANDFLASH
	277	#define CONFIG_SYS_USE_FLASH 1
	278
	279	#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
	280
	281	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
	282	#define CONFIG_ENV_IS_IN_DATAFLASH 1
	283	#define CONFIG_SYS_MONITOR_BASE \
	284	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
	285	#define CONFIG_ENV_OFFSET 0x4200
	286	#define CONFIG_ENV_ADDR \
	287	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
	288	#define CONFIG_ENV_SIZE 0x4200
	289	#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
	290	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	291	"root=/dev/mtdblock0 " \
918319c7	292	"mtdparts=atmel_nand:-(root) " \
32949232 II	293	"rw rootfstype=jffs2"
	294
	295	#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
	296
	297	/* bootstrap + u-boot + env + linux in nandflash */
	298	#define CONFIG_ENV_IS_IN_NAND 1
	299	#define CONFIG_ENV_OFFSET 0x60000
	300	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	301	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
	302	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
	303	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	304	"root=/dev/mtdblock5 " \
918319c7	305	"mtdparts=atmel_nand:128k(bootstrap)ro," \
32949232 II	306	"256k(uboot)ro,128k(env1)ro," \
	307	"128k(env2)ro,2M(linux),-(root) " \
	308	"rw rootfstype=jffs2"
	309
	310	#elif defined (CONFIG_SYS_USE_FLASH)
	311
	312	#define CONFIG_ENV_IS_IN_FLASH 1
	313	#define CONFIG_ENV_OFFSET 0x40000
	314	#define CONFIG_ENV_SECT_SIZE 0x10000
	315	#define CONFIG_ENV_SIZE 0x10000
	316	#define CONFIG_ENV_OVERWRITE 1
	317
	318	/* JFFS Partition offset set */
	319	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	320	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	321
	322	/* 512k reserved for u-boot */
	323	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
	324
	325	#define CONFIG_BOOTCOMMAND "run flashboot"
	326
	327	#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
	328	#define MTDPARTS_DEFAULT \
	329	"mtdparts=physmap-flash.0:" \
	330	"256k(u-boot)ro," \
	331	"64k(u-boot-env)ro," \
	332	"1408k(kernel)," \
	333	"-(rootfs);" \
	334	"nand:-(nand)"
	335
	336	#define CONFIG_CON_ROT "fbcon=rotate:3 "
	337	#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
	338
	339	#define CONFIG_EXTRA_ENV_SETTINGS \
	340	"mtdids=" MTDIDS_DEFAULT "\0" \
	341	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	342	"partition=nand0,0\0" \
	343	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	344	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	345	CONFIG_CON_ROT \
	346	"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
	347	"addip=setenv bootargs $(bootargs) " \
	348	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
	349	":$(hostname):eth0:off\0" \
	350	"ramboot=tftpboot 0x22000000 vmImage;" \
	351	"run ramargs;run addip;bootm 22000000\0" \
	352	"nfsboot=tftpboot 0x22000000 vmImage;" \
	353	"run nfsargs;run addip;bootm 22000000\0" \
	354	"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
	355	""
	356	#else
	357	#error "Undefined memory device"
	358	#endif
	359
	360	#define CONFIG_BAUDRATE 115200
	361	#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
	362
	363	#define CONFIG_SYS_PROMPT "pm9261> "
	364	#define CONFIG_SYS_CBSIZE 256
	365	#define CONFIG_SYS_MAXARGS 16
	366	#define CONFIG_SYS_PBSIZE \
	367	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	368	#define CONFIG_SYS_LONGHELP 1
	369	#define CONFIG_CMDLINE_EDITING 1
370
32949232 II	371	/*
	372	* Size of malloc() pool
	373	*/
	374	#define CONFIG_SYS_MALLOC_LEN \
	375	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
	376	#define CONFIG_SYS_GBL_DATA_SIZE 128
	377
	378	#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
	379
	380	#ifdef CONFIG_USE_IRQ
	381	#error CONFIG_USE_IRQ not supported
	382	#endif
	383
	384	#endif