[thirdparty/u-boot.git] / include / configs / porter.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * include/configs/porter.h
 *     This file is Porter board configuration.
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 */

#ifndef __PORTER_H
#define __PORTER_H

#include "rcar-gen2-common.h"

#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
#define STACK_AREA_SIZE			0x00100000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(1024u * 1024 * 1024)

/* FLASH */
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootm_size=0x10000000\0"

/* SPL support */
#define CONFIG_SPL_STACK		0xe6340000
#define CONFIG_SPL_MAX_SIZE		0x4000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ		65000000
#endif

#endif /* __PORTER_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
60c0467a VB	2	/*
	3	* include/configs/porter.h
	4	* This file is Porter board configuration.
	5	*
	6	* Copyright (C) 2015 Renesas Electronics Corporation
	7	* Copyright (C) 2015 Cogent Embedded, Inc.
60c0467a VB	8	*/
	9
	10	#ifndef __PORTER_H
	11	#define __PORTER_H
	12
60c0467a VB	13	#include "rcar-gen2-common.h"
60c0467a VB	14
7ee37d0e MV	15	#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
7ee37d0e MV	16	#define STACK_AREA_SIZE 0x00100000
60c0467a VB	17	#define LOW_LEVEL_MERAM_STACK \
	18	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	19
	20	/* MEMORY */
	21	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	22	#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
	23	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
	24
60c0467a	25	/* FLASH */
60c0467a	26	#define CONFIG_SPI_FLASH_QUAD
60c0467a VB	27
60c0467a VB	28	/* SH Ether */
60c0467a VB	29	#define CONFIG_SH_ETHER_USE_PORT 0
	30	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	31	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	32	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	33	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	34	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
60c0467a VB	35	#define CONFIG_BITBANGMII_MULTI
	36
	37	/* Board Clock */
	38	#define RMOBILE_XTAL_CLK 20000000u
	39	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
60c0467a	40
7b8eeb40	41	#define CONFIG_EXTRA_ENV_SETTINGS \
07a8060a	42	"bootm_size=0x10000000\0"
7b8eeb40	43
7ee37d0e	44	/* SPL support */
7ee37d0e	45	#define CONFIG_SPL_STACK 0xe6340000
0e592d07	46	#define CONFIG_SPL_MAX_SIZE 0x4000
0e592d07	47	#ifdef CONFIG_SPL_BUILD
9a5483e9 MV	48	#define CONFIG_CONS_SCIF0
	49	#define CONFIG_SH_SCIF_CLK_FREQ 65000000
	50	#endif
	51
60c0467a	52	#endif /* __PORTER_H */