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Commit | Line | Data |
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f5e0d039 HS |
1 | /* |
2 | * ppmc7xx.h | |
3 | * --------- | |
b87dfd28 | 4 | * |
f5e0d039 | 5 | * Wind River PPMC 7xx/74xx board configuration file. |
b87dfd28 | 6 | * |
f5e0d039 HS |
7 | * By Richard Danter (richard.danter@windriver.com) |
8 | * Copyright (C) 2005 Wind River Systems | |
9 | */ | |
10 | ||
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | #define CONFIG_PPMC7XX | |
16 | ||
17 | ||
18 | /*=================================================================== | |
b87dfd28 | 19 | * |
f5e0d039 | 20 | * User configurable settings - Modify to your preference |
b87dfd28 | 21 | * |
f5e0d039 HS |
22 | *=================================================================== |
23 | */ | |
24 | ||
25 | /* | |
26 | * Debug | |
b87dfd28 | 27 | * |
cdd917a4 WD |
28 | * DEBUG - Define this is you want extra debug info |
29 | * GTREGREAD - Required to build with debug | |
30 | * do_bdinfo - Required to build with debug | |
f5e0d039 HS |
31 | */ |
32 | ||
33 | #undef DEBUG | |
cdd917a4 WD |
34 | #ifdef DEBUG |
35 | #define GTREGREAD(x) 0xFFFFFFFF | |
f5e0d039 | 36 | #define do_bdinfo(a,b,c,d) |
cdd917a4 | 37 | #endif |
f5e0d039 HS |
38 | |
39 | /* | |
40 | * CPU type | |
b87dfd28 | 41 | * |
cdd917a4 WD |
42 | * CONFIG_7xx - We have a 750 or 755 CPU |
43 | * CONFIG_74xx - We have a 7400 CPU | |
44 | * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) | |
45 | * CONFIG_BUS_CLK - System bus clock in Hz | |
f5e0d039 HS |
46 | */ |
47 | ||
48 | #define CONFIG_7xx | |
49 | #undef CONFIG_74xx | |
50 | #undef CONFIG_ALTIVEC | |
cdd917a4 | 51 | #define CONFIG_BUS_CLK 66000000 |
f5e0d039 HS |
52 | |
53 | ||
54 | /* | |
55 | * Monitor configuration | |
b87dfd28 | 56 | * |
26a34560 | 57 | * List of command sets to include in shell |
b87dfd28 | 58 | * |
f5e0d039 | 59 | * The following command sets have been tested and known to work: |
b87dfd28 | 60 | * |
26a34560 JL |
61 | * CMD_CACHE - Cache control commands |
62 | * CMD_MEMORY - Memory display, change and test commands | |
63 | * CMD_FLASH - Erase and program flash | |
64 | * CMD_ENV - Environment commands | |
65 | * CMD_RUN - Run commands stored in env vars | |
66 | * CMD_ELF - Load ELF files | |
67 | * CMD_NET - Networking/file download commands | |
68 | * CMD_PIN - ICMP Echo Request command | |
69 | * CMD_PCI - PCI Bus scanning command | |
f5e0d039 HS |
70 | */ |
71 | ||
079a136c JL |
72 | /* |
73 | * BOOTP options | |
74 | */ | |
75 | #define CONFIG_BOOTP_BOOTFILESIZE | |
76 | #define CONFIG_BOOTP_BOOTPATH | |
77 | #define CONFIG_BOOTP_GATEWAY | |
78 | #define CONFIG_BOOTP_HOSTNAME | |
79 | ||
80 | ||
26a34560 JL |
81 | /* |
82 | * Command line configuration. | |
83 | */ | |
84 | #include <config_cmd_default.h> | |
85 | ||
86 | #define CONFIG_CMD_FLASH | |
87 | #define CONFIG_CMD_ENV | |
88 | #define CONFIG_CMD_RUN | |
89 | #define CONFIG_CMD_ELF | |
90 | #define CONFIG_CMD_NET | |
91 | #define CONFIG_CMD_PING | |
92 | #define CONFIG_CMD_PCI | |
93 | ||
94 | #undef CONFIG_CMD_KGDB | |
f5e0d039 HS |
95 | |
96 | ||
97 | /* | |
98 | * Serial configuration | |
99 | * | |
100 | * CONFIG_CONS_INDEX - Serial console port number (COM1) | |
cdd917a4 | 101 | * CONFIG_BAUDRATE - Serial speed |
f5e0d039 HS |
102 | */ |
103 | ||
cdd917a4 WD |
104 | #define CONFIG_CONS_INDEX 1 |
105 | #define CONFIG_BAUDRATE 9600 | |
f5e0d039 HS |
106 | |
107 | ||
108 | /* | |
109 | * PCI config | |
b87dfd28 | 110 | * |
cdd917a4 WD |
111 | * CONFIG_PCI - Enable PCI bus |
112 | * CONFIG_PCI_PNP - Enable Plug & Play support | |
f5e0d039 HS |
113 | * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup |
114 | */ | |
115 | ||
116 | #define CONFIG_PCI | |
117 | #define CONFIG_PCI_PNP | |
118 | #undef CONFIG_PCI_SCAN_SHOW | |
119 | ||
120 | ||
121 | /* | |
122 | * Network config | |
b87dfd28 | 123 | * |
cdd917a4 WD |
124 | * CONFIG_NET_MULTI - Support for multiple network interfaces |
125 | * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller | |
126 | * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM | |
f5e0d039 HS |
127 | */ |
128 | ||
129 | #define CONFIG_NET_MULTI | |
130 | #define CONFIG_EEPRO100 | |
131 | #define CONFIG_EEPRO100_SROM_WRITE | |
132 | ||
133 | ||
134 | /* | |
135 | * Enable extra init functions | |
b87dfd28 | 136 | * |
f5e0d039 HS |
137 | * CONFIG_MISC_INIT_F - Call pre-relocation init functions |
138 | * CONFIG_MISC_INIT_R - Call post relocation init functions | |
139 | */ | |
140 | ||
141 | #undef CONFIG_MISC_INIT_F | |
b87dfd28 | 142 | #define CONFIG_MISC_INIT_R |
f5e0d039 HS |
143 | |
144 | ||
145 | /* | |
146 | * Boot config | |
b87dfd28 | 147 | * |
f5e0d039 | 148 | * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot |
cdd917a4 | 149 | * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) |
f5e0d039 HS |
150 | */ |
151 | ||
152 | #define CONFIG_BOOTCOMMAND \ | |
153 | "bootp;" \ | |
154 | "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ | |
155 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ | |
156 | "bootm" | |
157 | #define CONFIG_BOOTDELAY 5 | |
158 | ||
159 | ||
160 | /*=================================================================== | |
b87dfd28 | 161 | * |
f5e0d039 | 162 | * Board configuration settings - You should not need to modify these |
b87dfd28 | 163 | * |
f5e0d039 HS |
164 | *=================================================================== |
165 | */ | |
166 | ||
167 | ||
f5e0d039 HS |
168 | /* |
169 | * Memory map | |
b87dfd28 | 170 | * |
f5e0d039 | 171 | * This board runs in a standard CHRP (Map-B) configuration. |
b87dfd28 | 172 | * |
cdd917a4 | 173 | * Type Start End Size Width Chip Sel |
f5e0d039 | 174 | * ----------- ----------- ----------- ------- ------- -------- |
cdd917a4 WD |
175 | * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 |
176 | * User LED's 0x78000000 RCS3 | |
177 | * UART 0x7C000000 RCS2 | |
178 | * Mailbox 0xFF000000 RCS1 | |
179 | * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 | |
b87dfd28 | 180 | * |
f5e0d039 | 181 | * Flash sectors are laid out as follows. |
b87dfd28 | 182 | * |
cdd917a4 | 183 | * Sector Start End Size Comments |
f5e0d039 | 184 | * ------- ----------- ----------- ------- ----------- |
cdd917a4 WD |
185 | * 0 0xFFC00000 0xFFC3FFFF 256KB |
186 | * 1 0xFFC40000 0xFFC7FFFF 256KB | |
187 | * 2 0xFFC80000 0xFFCBFFFF 256KB | |
188 | * 3 0xFFCC0000 0xFFCFFFFF 256KB | |
189 | * 4 0xFFD00000 0xFFD3FFFF 256KB | |
190 | * 5 0xFFD40000 0xFFD7FFFF 256KB | |
191 | * 6 0xFFD80000 0xFFDBFFFF 256KB | |
192 | * 7 0xFFDC0000 0xFFDFFFFF 256KB | |
193 | * 8 0xFFE00000 0xFFE3FFFF 256KB | |
194 | * 9 0xFFE40000 0xFFE7FFFF 256KB | |
195 | * 10 0xFFE80000 0xFFEBFFFF 256KB | |
196 | * 11 0xFFEC0000 0xFFEFFFFF 256KB | |
197 | * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here | |
198 | * 13 0xFFF40000 0xFFF7FFFF 256KB | |
199 | * 14 0xFFF80000 0xFFFBFFFF 256KB | |
200 | * 15 0xFFFC0000 0xFFFDFFFF 128KB | |
201 | * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here | |
202 | * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here | |
203 | * 18 0xFFFF0000 0xFFFFFFFF 64KB | |
f5e0d039 HS |
204 | */ |
205 | ||
206 | ||
207 | /* | |
208 | * SDRAM config - see memory map details above. | |
b87dfd28 | 209 | * |
cdd917a4 WD |
210 | * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! |
211 | * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) | |
f5e0d039 HS |
212 | */ |
213 | ||
cdd917a4 WD |
214 | #define CFG_SDRAM_BASE 0x00000000 |
215 | #define CFG_SDRAM_SIZE 0x04000000 | |
f5e0d039 HS |
216 | |
217 | ||
b87dfd28 | 218 | /* |
f5e0d039 | 219 | * Flash config - see memory map details above. |
b87dfd28 | 220 | * |
cdd917a4 WD |
221 | * CFG_FLASH_BASE - Start address of flash memory |
222 | * CFG_FLASH_SIZE - Total size of contiguous flash mem | |
f5e0d039 HS |
223 | * CFG_FLASH_ERASE_TOUT - Erase timeout in ms |
224 | * CFG_FLASH_WRITE_TOUT - Write timeout in ms | |
225 | * CFG_MAX_FLASH_BANKS - Number of banks of flash on board | |
226 | * CFG_MAX_FLASH_SECT - Number of sectors in a bank | |
227 | */ | |
228 | ||
cdd917a4 WD |
229 | #define CFG_FLASH_BASE 0xFFC00000 |
230 | #define CFG_FLASH_SIZE 0x00400000 | |
f5e0d039 HS |
231 | #define CFG_FLASH_ERASE_TOUT 250000 |
232 | #define CFG_FLASH_WRITE_TOUT 5000 | |
cdd917a4 WD |
233 | #define CFG_MAX_FLASH_BANKS 1 |
234 | #define CFG_MAX_FLASH_SECT 19 | |
f5e0d039 HS |
235 | |
236 | ||
237 | /* | |
238 | * Monitor config - see memory map details above | |
b87dfd28 | 239 | * |
cdd917a4 WD |
240 | * CFG_MONITOR_BASE - Base address of monitor code |
241 | * CFG_MALLOC_LEN - Size of malloc pool (128KB) | |
f5e0d039 HS |
242 | */ |
243 | ||
cdd917a4 WD |
244 | #define CFG_MONITOR_BASE TEXT_BASE |
245 | #define CFG_MALLOC_LEN 0x20000 | |
f5e0d039 HS |
246 | |
247 | ||
248 | /* | |
249 | * Command shell settings | |
b87dfd28 | 250 | * |
f5e0d039 HS |
251 | * CFG_BARGSIZE - Boot Argument buffer size |
252 | * CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB) | |
253 | * CFG_CBSIZE - Console Buffer (input) size | |
254 | * CFG_LOAD_ADDR - Default load address | |
255 | * CFG_LONGHELP - Provide more detailed help | |
256 | * CFG_MAXARGS - Number of args accepted by monitor commands | |
257 | * CFG_MEMTEST_START - Start address of test to run on RAM | |
258 | * CFG_MEMTEST_END - End address of RAM test | |
259 | * CFG_PBSIZE - Print Buffer (output) size | |
260 | * CFG_PROMPT - Prompt string | |
261 | */ | |
262 | ||
cdd917a4 WD |
263 | #define CFG_BARGSIZE 1024 |
264 | #define CFG_BOOTMAPSZ 0x800000 | |
265 | #define CFG_CBSIZE 1024 | |
266 | #define CFG_LOAD_ADDR 0x100000 | |
f5e0d039 | 267 | #define CFG_LONGHELP |
cdd917a4 WD |
268 | #define CFG_MAXARGS 16 |
269 | #define CFG_MEMTEST_START 0x00040000 | |
270 | #define CFG_MEMTEST_END 0x00040100 | |
271 | #define CFG_PBSIZE 1024 | |
272 | #define CFG_PROMPT "=> " | |
f5e0d039 HS |
273 | |
274 | ||
275 | /* | |
276 | * Environment config - see memory map details above | |
b87dfd28 | 277 | * |
f5e0d039 HS |
278 | * CFG_ENV_IS_IN_FLASH - The env variables are stored in flash |
279 | * CFG_ENV_ADDR - Address of the sector containing env vars | |
b87dfd28 | 280 | * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB) |
f5e0d039 HS |
281 | * CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB) |
282 | */ | |
283 | ||
cdd917a4 WD |
284 | #define CFG_ENV_IS_IN_FLASH 1 |
285 | #define CFG_ENV_ADDR 0xFFFE0000 | |
286 | #define CFG_ENV_SIZE 0x1000 | |
287 | #define CFG_ENV_ADDR_REDUND 0xFFFE8000 | |
288 | #define CFG_ENV_SIZE_REDUND 0x1000 | |
289 | #define CFG_ENV_SECT_SIZE 0x8000 | |
f5e0d039 HS |
290 | |
291 | ||
292 | /* | |
293 | * Initial RAM config | |
294 | * | |
295 | * Since the main system RAM is initialised very early, we place the INIT_RAM | |
296 | * in the main system RAM just above the exception vectors. The contents are | |
297 | * copied to top of RAM by the init code. | |
b87dfd28 | 298 | * |
f5e0d039 | 299 | * CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect |
cdd917a4 | 300 | * CFG_INIT_RAM_END - Size of Init RAM |
f5e0d039 HS |
301 | * CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data |
302 | * CFG_GBL_DATA_OFFSET - Start of global data, top of stack | |
303 | */ | |
304 | ||
cdd917a4 WD |
305 | #define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000) |
306 | #define CFG_INIT_RAM_END 0x4000 | |
307 | #define CFG_GBL_DATA_SIZE 128 | |
308 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
f5e0d039 HS |
309 | |
310 | ||
311 | /* | |
312 | * Initial BAT config | |
b87dfd28 | 313 | * |
f5e0d039 HS |
314 | * BAT0 - System SDRAM |
315 | * BAT1 - LED's and Serial Port | |
316 | * BAT2 - PCI Memory | |
317 | * BAT3 - PCI I/O including Flash Memory | |
318 | */ | |
319 | ||
320 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
321 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) | |
322 | #define CFG_DBAT0L CFG_IBAT0L | |
323 | #define CFG_DBAT0U CFG_IBAT0U | |
324 | ||
325 | #define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT) | |
326 | #define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
327 | #define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
328 | #define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
329 | ||
330 | #define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) | |
331 | #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
332 | #define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
333 | #define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
334 | ||
335 | #define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) | |
336 | #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
337 | #define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
338 | #define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
339 | ||
340 | ||
341 | /* | |
342 | * Cache config | |
b87dfd28 | 343 | * |
f5e0d039 | 344 | * CFG_CACHELINE_SIZE - Size of a cache line (CPU specific) |
cdd917a4 WD |
345 | * CFG_L2 - L2 cache enabled if defined |
346 | * L2_INIT - L2 cache init flags | |
347 | * L2_ENABLE - L2 cache enable flags | |
f5e0d039 HS |
348 | */ |
349 | ||
cdd917a4 | 350 | #define CFG_CACHELINE_SIZE 32 |
f5e0d039 | 351 | #undef CFG_L2 |
cdd917a4 WD |
352 | #define L2_INIT 0 |
353 | #define L2_ENABLE 0 | |
f5e0d039 HS |
354 | |
355 | ||
356 | /* | |
357 | * Clocks config | |
b87dfd28 | 358 | * |
cdd917a4 WD |
359 | * CFG_BUS_HZ - Bus clock frequency in Hz |
360 | * CFG_BUS_CLK - As above (?) | |
361 | * CFG_HZ - Decrementer freq in Hz | |
f5e0d039 HS |
362 | */ |
363 | ||
cdd917a4 WD |
364 | #define CFG_BUS_HZ CONFIG_BUS_CLK |
365 | #define CFG_BUS_CLK CONFIG_BUS_CLK | |
366 | #define CFG_HZ 1000 | |
f5e0d039 HS |
367 | |
368 | ||
369 | /* | |
370 | * Serial port config | |
b87dfd28 | 371 | * |
f5e0d039 | 372 | * CFG_BAUDRATE_TABLE - List of valid baud rates |
cdd917a4 | 373 | * CFG_NS16550 - Include the NS16550 driver |
f5e0d039 | 374 | * CFG_NS16550_SERIAL - Include the serial (wrapper) driver |
cdd917a4 | 375 | * CFG_NS16550_CLK - Frequency of reference clock |
f5e0d039 | 376 | * CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port |
cdd917a4 | 377 | * CFG_NS16550_COM1 - Base address of 1st serial port |
f5e0d039 HS |
378 | */ |
379 | ||
cdd917a4 | 380 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
f5e0d039 HS |
381 | #define CFG_NS16550 |
382 | #define CFG_NS16550_SERIAL | |
cdd917a4 | 383 | #define CFG_NS16550_CLK 3686400 |
f5e0d039 | 384 | #define CFG_NS16550_REG_SIZE -8 |
cdd917a4 | 385 | #define CFG_NS16550_COM1 0x7C000000 |
f5e0d039 HS |
386 | |
387 | ||
388 | /* | |
389 | * PCI Config - Address Map B (CHRP) | |
390 | */ | |
391 | ||
cdd917a4 WD |
392 | #define CFG_PCI_MEMORY_BUS 0x00000000 |
393 | #define CFG_PCI_MEMORY_PHYS 0x00000000 | |
394 | #define CFG_PCI_MEMORY_SIZE 0x40000000 | |
395 | #define CFG_PCI_MEM_BUS 0x80000000 | |
396 | #define CFG_PCI_MEM_PHYS 0x80000000 | |
397 | #define CFG_PCI_MEM_SIZE 0x7D000000 | |
398 | #define CFG_ISA_MEM_BUS 0x00000000 | |
399 | #define CFG_ISA_MEM_PHYS 0xFD000000 | |
400 | #define CFG_ISA_MEM_SIZE 0x01000000 | |
401 | #define CFG_PCI_IO_BUS 0x00800000 | |
402 | #define CFG_PCI_IO_PHYS 0xFE800000 | |
403 | #define CFG_PCI_IO_SIZE 0x00400000 | |
404 | #define CFG_ISA_IO_BUS 0x00000000 | |
405 | #define CFG_ISA_IO_PHYS 0xFE000000 | |
406 | #define CFG_ISA_IO_SIZE 0x00800000 | |
f5e0d039 | 407 | #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS |
cdd917a4 WD |
408 | #define CFG_ISA_IO CFG_ISA_IO_PHYS |
409 | #define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS | |
f5e0d039 HS |
410 | |
411 | ||
412 | /* | |
413 | * Extra init functions | |
b87dfd28 | 414 | * |
f5e0d039 HS |
415 | * CFG_BOARD_ASM_INIT - Call assembly init code |
416 | */ | |
417 | ||
418 | #define CFG_BOARD_ASM_INIT | |
419 | ||
420 | ||
421 | /* | |
422 | * Boot flags | |
b87dfd28 | 423 | * |
cdd917a4 WD |
424 | * BOOTFLAG_COLD - Indicates a power-on boot |
425 | * BOOTFLAG_WARM - Indicates a software reset | |
f5e0d039 | 426 | */ |
b87dfd28 | 427 | |
cdd917a4 WD |
428 | #define BOOTFLAG_COLD 0x01 |
429 | #define BOOTFLAG_WARM 0x02 | |
f5e0d039 HS |
430 | |
431 | ||
432 | #endif /* __CONFIG_H */ |