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fe8c2806 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
4 | * | |
5 | * (C) Copyright 2000 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright 2001 | |
10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
12 | * | |
13 | * Configuation settings for the WindRiver PPMC8260 board. | |
14 | * | |
15 | * See file CREDITS for list of people who contributed to this | |
16 | * project. | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License as | |
20 | * published by the Free Software Foundation; either version 2 of | |
21 | * the License, or (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
31 | * MA 02111-1307 USA | |
32 | */ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /***************************************************************************** | |
38 | * | |
39 | * These settings must match the way _your_ board is set up | |
40 | * | |
41 | *****************************************************************************/ | |
42 | ||
43 | /* What is the oscillator's (UX2) frequency in Hz? */ | |
44 | #define CONFIG_8260_CLKIN (66 * 1000 * 1000) | |
45 | ||
46 | /*----------------------------------------------------------------------- | |
47 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
48 | *----------------------------------------------------------------------- | |
49 | * What should MODCK_H be? It is dependent on the oscillator | |
50 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
51 | * Here are some example values (all frequencies are in MHz): | |
52 | * | |
53 | * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 | |
54 | * ------- ---------- --- --- ---- ----- ----- ----- | |
55 | * 0x2 0x2 33 133 133 Close Open Close | |
56 | * 0x2 0x3 33 133 166 Close Open Open | |
57 | * 0x2 0x4 33 133 200 Open Close Close | |
58 | * 0x2 0x5 33 133 233 Open Close Open | |
59 | * 0x2 0x6 33 133 266 Open Open Close | |
60 | * | |
61 | * 0x5 0x5 66 133 133 Open Close Open | |
62 | * 0x5 0x6 66 133 166 Open Open Close | |
63 | * 0x5 0x7 66 133 200 Open Open Open | |
64 | * 0x6 0x0 66 133 233 Close Close Close | |
65 | * 0x6 0x1 66 133 266 Close Close Open | |
66 | * 0x6 0x2 66 133 300 Close Open Close | |
67 | */ | |
68 | #define CFG_PPMC_MODCK_H 0x05 | |
69 | ||
70 | /* Define this if you want to boot from 0x00000100. If you don't define | |
71 | * this, you will need to program the bootloader to 0xfff00000, and | |
72 | * get the hardware reset config words at 0xfe000000. The simplest | |
73 | * way to do that is to program the bootloader at both addresses. | |
74 | * It is suggested that you just let U-Boot live at 0x00000000. | |
75 | */ | |
76 | #define CFG_PPMC_BOOT_LOW 1 | |
77 | ||
78 | /* What should the base address of the main FLASH be and how big is | |
79 | * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk | |
80 | * The main FLASH is whichever is connected to *CS0. U-Boot expects | |
81 | * this to be the SIMM. | |
82 | */ | |
83 | #define CFG_FLASH0_BASE 0xFE000000 | |
84 | #define CFG_FLASH0_SIZE 16 | |
85 | ||
86 | /* What should be the base address of the first SDRAM DIMM and how big is | |
87 | * it (in Mbytes)? | |
88 | */ | |
89 | #define CFG_SDRAM0_BASE 0x00000000 | |
90 | #define CFG_SDRAM0_SIZE 128 | |
91 | ||
92 | /* What should be the base address of the second SDRAM DIMM and how big is | |
93 | * it (in Mbytes)? | |
94 | */ | |
95 | #define CFG_SDRAM1_BASE 0x08000000 | |
96 | #define CFG_SDRAM1_SIZE 128 | |
97 | ||
98 | /* What should be the base address of the on board SDRAM and how big is | |
99 | * it (in Mbytes)? | |
100 | */ | |
101 | #define CFG_SDRAM2_BASE 0x38000000 | |
102 | #define CFG_SDRAM2_SIZE 16 | |
103 | ||
104 | /* What should be the base address of the MAILBOX and how big is it | |
105 | * (in Bytes) | |
106 | * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000 | |
107 | */ | |
108 | #define CFG_MAILBOX_BASE 0x32000000 | |
109 | #define CFG_MAILBOX_SIZE 8192 | |
110 | ||
111 | /* What is the base address of the I/O select lines and how big is it | |
112 | * (In Mbytes)? | |
113 | */ | |
114 | ||
115 | #define CFG_IOSELECT_BASE 0xE0000000 | |
116 | #define CFG_IOSELECT_SIZE 32 | |
117 | ||
118 | ||
119 | /* What should be the base address of the LEDs and switch S0? | |
120 | * If you don't want them enabled, don't define this. | |
121 | */ | |
122 | #define CFG_LED_BASE 0xF1000000 | |
123 | ||
124 | /* | |
125 | * PPMC8260 with 256 16 MB DIMM: | |
126 | * | |
127 | * 0x0000 0000 Exception Vector code, 8k | |
128 | * : | |
129 | * 0x0000 1FFF | |
130 | * 0x0000 2000 Free for Application Use | |
131 | * : | |
132 | * : | |
133 | * | |
134 | * : | |
135 | * : | |
136 | * 0x0FF5 FF30 Monitor Stack (Growing downward) | |
137 | * Monitor Stack Buffer (0x80) | |
138 | * 0x0FF5 FFB0 Board Info Data | |
139 | * 0x0FF6 0000 Malloc Arena | |
140 | * : CFG_ENV_SECT_SIZE, 256k | |
141 | * : CFG_MALLOC_LEN, 128k | |
142 | * 0x0FFC 0000 RAM Copy of Monitor Code | |
143 | * : CFG_MONITOR_LEN, 256k | |
144 | * 0x0FFF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 | |
145 | */ | |
146 | ||
147 | ||
148 | /* | |
149 | * select serial console configuration | |
150 | * | |
151 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
152 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
153 | * for SCC). | |
154 | * | |
155 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
156 | * defined elsewhere. | |
157 | * The console can be on SMC1 or SMC2 | |
158 | */ | |
159 | #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ | |
160 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
161 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
162 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
163 | ||
164 | /* | |
165 | * select ethernet configuration | |
166 | * | |
167 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
168 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
169 | * for FCC) | |
170 | * | |
171 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 172 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
fe8c2806 WD |
173 | */ |
174 | ||
175 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ | |
176 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ | |
177 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
178 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
179 | #define CONFIG_MII /* MII PHY management */ | |
180 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
181 | /* | |
182 | * Port pins used for bit-banged MII communictions (if applicable). | |
183 | */ | |
184 | #define MDIO_PORT 2 /* Port C */ | |
185 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) | |
186 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
187 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
188 | ||
189 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
190 | else iop->pdat &= ~0x00400000 | |
191 | ||
192 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
193 | else iop->pdat &= ~0x00200000 | |
194 | ||
195 | #define MIIDELAY udelay(1) | |
196 | ||
197 | ||
198 | /* Define this to reserve an entire FLASH sector (256 KB) for | |
199 | * environment variables. Otherwise, the environment will be | |
200 | * put in the same sector as U-Boot, and changing variables | |
201 | * will erase U-Boot temporarily | |
202 | */ | |
203 | #define CFG_ENV_IN_OWN_SECT 1 | |
204 | ||
205 | /* Define to allow the user to overwrite serial and ethaddr */ | |
206 | #define CONFIG_ENV_OVERWRITE | |
207 | ||
208 | /* What should the console's baud rate be? */ | |
209 | #define CONFIG_BAUDRATE 9600 | |
210 | ||
211 | /* Ethernet MAC address */ | |
212 | ||
213 | #define CONFIG_ETHADDR 00:a0:1e:90:2b:00 | |
214 | ||
215 | /* Define this to set the last octet of the ethernet address | |
216 | * from the DS0-DS7 switch and light the leds with the result | |
217 | * The DS0-DS7 switch and the leds are backwards with respect | |
218 | * to each other. DS7 is on the board edge side of both the | |
219 | * led strip and the DS0-DS7 switch. | |
220 | */ | |
221 | #define CONFIG_MISC_INIT_R | |
222 | ||
223 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
224 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
225 | ||
226 | #if 0 | |
227 | /* Be selective on what keys can delay or stop the autoboot process | |
228 | * To stop use: " " | |
229 | */ | |
230 | # define CONFIG_AUTOBOOT_KEYED | |
c37207d7 WD |
231 | # define CONFIG_AUTOBOOT_PROMPT \ |
232 | "Autobooting in %d seconds, press \" \" to stop\n", bootdelay | |
fe8c2806 WD |
233 | # define CONFIG_AUTOBOOT_STOP_STR " " |
234 | # undef CONFIG_AUTOBOOT_DELAY_STR | |
235 | # define DEBUG_BOOTKEYS 0 | |
236 | #endif | |
237 | ||
238 | /* Define a command string that is automatically executed when no character | |
239 | * is read on the console interface withing "Boot Delay" after reset. | |
240 | */ | |
53677ef1 | 241 | #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ |
b79a11cc | 242 | #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ |
fe8c2806 | 243 | |
42dfe7a1 | 244 | #ifdef CONFIG_BOOT_ROOT_INITRD |
fe8c2806 WD |
245 | #define CONFIG_BOOTCOMMAND \ |
246 | "version;" \ | |
247 | "echo;" \ | |
248 | "bootp;" \ | |
249 | "setenv bootargs root=/dev/ram0 rw " \ | |
fe126d8b | 250 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
fe8c2806 WD |
251 | "bootm" |
252 | #endif /* CONFIG_BOOT_ROOT_INITRD */ | |
253 | ||
42dfe7a1 | 254 | #ifdef CONFIG_BOOT_ROOT_NFS |
fe8c2806 WD |
255 | #define CONFIG_BOOTCOMMAND \ |
256 | "version;" \ | |
257 | "echo;" \ | |
258 | "bootp;" \ | |
fe126d8b WD |
259 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
260 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
fe8c2806 WD |
261 | "bootm" |
262 | #endif /* CONFIG_BOOT_ROOT_NFS */ | |
263 | ||
d3b8c1a7 JL |
264 | |
265 | /* | |
266 | * BOOTP options | |
fe8c2806 | 267 | */ |
d3b8c1a7 JL |
268 | #define CONFIG_BOOTP_SUBNETMASK |
269 | #define CONFIG_BOOTP_GATEWAY | |
270 | #define CONFIG_BOOTP_HOSTNAME | |
271 | #define CONFIG_BOOTP_BOOTPATH | |
272 | #define CONFIG_BOOTP_BOOTFILESIZE | |
273 | #define CONFIG_BOOTP_DNS | |
274 | ||
fe8c2806 WD |
275 | |
276 | /* undef this to save memory */ | |
277 | #define CFG_LONGHELP | |
278 | ||
279 | /* Monitor Command Prompt */ | |
280 | #define CFG_PROMPT "=> " | |
281 | ||
26a34560 JL |
282 | |
283 | /* | |
284 | * Command line configuration. | |
285 | */ | |
286 | #include <config_cmd_default.h> | |
287 | ||
288 | #define CONFIG_CMD_ELF | |
289 | #define CONFIG_CMD_ASKENV | |
290 | #define CONFIG_CMD_REGINFO | |
291 | #define CONFIG_CMD_MEMTEST | |
292 | #define CONFIG_CMD_MII | |
293 | #define CONFIG_CMD_IMMAP | |
294 | ||
295 | #undef CONFIG_CMD_KGDB | |
fe8c2806 WD |
296 | |
297 | ||
298 | /* Where do the internal registers live? */ | |
299 | #define CFG_IMMR 0xf0000000 | |
300 | ||
301 | /***************************************************************************** | |
302 | * | |
303 | * You should not have to modify any of the following settings | |
304 | * | |
305 | *****************************************************************************/ | |
306 | ||
307 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
308 | #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ | |
9c4c5ae3 | 309 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
fe8c2806 | 310 | |
fe8c2806 WD |
311 | /* |
312 | * Miscellaneous configurable options | |
313 | */ | |
26a34560 | 314 | #if defined(CONFIG_CMD_KGDB) |
fe8c2806 WD |
315 | # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
316 | #else | |
317 | # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
318 | #endif | |
319 | ||
320 | /* Print Buffer Size */ | |
321 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) | |
322 | ||
323 | #define CFG_MAXARGS 32 /* max number of command args */ | |
324 | ||
325 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
326 | ||
327 | #define CFG_LOAD_ADDR 0x140000 /* default load address */ | |
328 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
329 | ||
330 | #define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ | |
331 | /* the exception vector table */ | |
332 | /* to the end of the DRAM */ | |
333 | /* less monitor and malloc area */ | |
334 | #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ | |
335 | #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ | |
336 | + CFG_MALLOC_LEN \ | |
337 | + CFG_ENV_SECT_SIZE \ | |
338 | + CFG_STACK_USAGE ) | |
339 | ||
340 | #define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ | |
341 | - CFG_MEM_END_USAGE ) | |
342 | ||
343 | /* valid baudrates */ | |
344 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
345 | ||
346 | /* | |
347 | * Low Level Configuration Settings | |
348 | * (address mappings, register initial values, etc.) | |
349 | * You should know what you are doing if you make changes here. | |
350 | */ | |
351 | ||
352 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
353 | /* | |
354 | * Attention: This is board specific | |
355 | * - RX clk is CLK11 | |
356 | * - TX clk is CLK12 | |
357 | */ | |
358 | #define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\ | |
359 | CMXSCR_TS1CS_CLK12) | |
360 | ||
361 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
362 | /* | |
363 | * Attention: this is board-specific | |
364 | * - Rx-CLK is CLK13 | |
365 | * - Tx-CLK is CLK14 | |
366 | * - Select bus for bd/buffers (see 28-13) | |
367 | * - Enable Full Duplex in FSMR | |
368 | */ | |
369 | #define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
370 | #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
371 | #define CFG_CPMFCR_RAMTYPE 0 | |
372 | #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
373 | #endif /* CONFIG_ETHER_INDEX */ | |
374 | ||
375 | #define CFG_FLASH_BASE CFG_FLASH0_BASE | |
376 | #define CFG_FLASH_SIZE CFG_FLASH0_SIZE | |
377 | #define CFG_SDRAM_BASE CFG_SDRAM0_BASE | |
378 | #define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) | |
379 | ||
380 | /*----------------------------------------------------------------------- | |
381 | * Hard Reset Configuration Words | |
382 | */ | |
383 | #if defined(CFG_PPMC_BOOT_LOW) | |
384 | # define CFG_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
385 | #else | |
386 | # define CFG_PPMC_HRCW_BOOT_FLAGS (0) | |
387 | #endif /* defined(CFG_PPMC_BOOT_LOW) */ | |
388 | ||
389 | /* get the HRCW ISB field from CFG_IMMR */ | |
390 | #define CFG_PPMC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ | |
391 | ((CFG_IMMR & 0x01000000) >> 7) | \ | |
392 | ((CFG_IMMR & 0x00100000) >> 4) ) | |
393 | ||
394 | #define CFG_HRCW_MASTER ( HRCW_EBM | \ | |
395 | HRCW_BPS11 | \ | |
396 | HRCW_L2CPC10 | \ | |
397 | HRCW_DPPC00 | \ | |
398 | CFG_PPMC_HRCW_IMMR | \ | |
399 | HRCW_MMR00 | \ | |
400 | HRCW_LBPC00 | \ | |
401 | HRCW_APPC10 | \ | |
402 | HRCW_CS10PC00 | \ | |
403 | (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \ | |
404 | CFG_PPMC_HRCW_BOOT_FLAGS ) | |
405 | ||
406 | /* no slaves */ | |
407 | #define CFG_HRCW_SLAVE1 0 | |
408 | #define CFG_HRCW_SLAVE2 0 | |
409 | #define CFG_HRCW_SLAVE3 0 | |
410 | #define CFG_HRCW_SLAVE4 0 | |
411 | #define CFG_HRCW_SLAVE5 0 | |
412 | #define CFG_HRCW_SLAVE6 0 | |
413 | #define CFG_HRCW_SLAVE7 0 | |
414 | ||
415 | /*----------------------------------------------------------------------- | |
416 | * Definitions for initial stack pointer and data area (in DPRAM) | |
417 | */ | |
418 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
419 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
420 | #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ | |
421 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
422 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
423 | ||
424 | /*----------------------------------------------------------------------- | |
425 | * Start addresses for the final memory configuration | |
426 | * (Set up by the startup code) | |
427 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
428 | * Note also that the logic that sets CFG_RAMBOOT is platform dependent. | |
429 | */ | |
430 | #define CFG_MONITOR_BASE CFG_FLASH0_BASE | |
431 | ||
432 | #ifndef CFG_MONITOR_BASE | |
433 | #define CFG_MONITOR_BASE 0x0ff80000 | |
434 | #endif | |
435 | ||
436 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
437 | # define CFG_RAMBOOT | |
438 | #endif | |
439 | ||
440 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */ | |
441 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
442 | ||
443 | /* | |
444 | * For booting Linux, the board info and command line data | |
445 | * have to be in the first 8 MB of memory, since this is | |
446 | * the maximum mapped by the Linux kernel during initialization. | |
447 | */ | |
448 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
449 | ||
450 | /*----------------------------------------------------------------------- | |
451 | * FLASH and environment organization | |
452 | */ | |
453 | ||
454 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
bf9e3b38 | 455 | #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
fe8c2806 WD |
456 | #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
457 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
458 | #define CFG_FLASH_INCREMENT 0 /* there is only one bank */ | |
459 | #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ | |
460 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
461 | ||
462 | ||
463 | #ifndef CFG_RAMBOOT | |
464 | ||
465 | # define CFG_ENV_IS_IN_FLASH 1 | |
466 | # ifdef CFG_ENV_IN_OWN_SECT | |
467 | # define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
468 | # define CFG_ENV_SECT_SIZE 0x40000 | |
469 | # else | |
470 | # define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) | |
471 | # define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
472 | # define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ | |
473 | # endif /* CFG_ENV_IN_OWN_SECT */ | |
474 | ||
475 | #else | |
476 | # define CFG_ENV_IS_IN_FLASH 1 | |
477 | # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) | |
478 | #define CFG_ENV_SIZE 0x1000 | |
479 | # define CFG_ENV_SECT_SIZE 0x40000 | |
480 | #endif /* CFG_RAMBOOT */ | |
481 | ||
482 | /*----------------------------------------------------------------------- | |
483 | * Cache Configuration | |
484 | */ | |
485 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
486 | ||
26a34560 | 487 | #if defined(CONFIG_CMD_KGDB) |
fe8c2806 WD |
488 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
489 | #endif | |
490 | ||
491 | /*----------------------------------------------------------------------- | |
492 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
493 | *----------------------------------------------------------------------- | |
494 | * HID0 also contains cache control - initially enable both caches and | |
495 | * invalidate contents, then the final state leaves only the instruction | |
496 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
497 | * but Soft reset does not. | |
498 | * | |
499 | * HID1 has only read-only information - nothing to set. | |
500 | */ | |
501 | #define CFG_HID0_INIT (HID0_ICE |\ | |
502 | HID0_DCE |\ | |
503 | HID0_ICFI |\ | |
504 | HID0_DCI |\ | |
505 | HID0_IFEM |\ | |
506 | HID0_ABE) | |
507 | ||
508 | #define CFG_HID0_FINAL (HID0_ICE |\ | |
509 | HID0_IFEM |\ | |
510 | HID0_ABE |\ | |
511 | HID0_EMCP) | |
512 | #define CFG_HID2 0 | |
513 | ||
514 | /*----------------------------------------------------------------------- | |
515 | * RMR - Reset Mode Register | |
516 | *----------------------------------------------------------------------- | |
517 | */ | |
518 | #define CFG_RMR 0 | |
519 | ||
520 | /*----------------------------------------------------------------------- | |
521 | * BCR - Bus Configuration 4-25 | |
522 | *----------------------------------------------------------------------- | |
523 | */ | |
524 | #define CFG_BCR (BCR_EBM |\ | |
525 | 0x30000000) | |
526 | ||
527 | /*----------------------------------------------------------------------- | |
528 | * SIUMCR - SIU Module Configuration 4-31 | |
529 | * Ref Section 4.3.2.6 page 4-31 | |
530 | *----------------------------------------------------------------------- | |
531 | */ | |
532 | ||
533 | #define CFG_SIUMCR (SIUMCR_ESE |\ | |
534 | SIUMCR_DPPC00 |\ | |
535 | SIUMCR_L2CPC10 |\ | |
536 | SIUMCR_LBPC00 |\ | |
537 | SIUMCR_APPC10 |\ | |
538 | SIUMCR_CS10PC00 |\ | |
539 | SIUMCR_BCTLC00 |\ | |
540 | SIUMCR_MMR00) | |
541 | ||
542 | ||
543 | /*----------------------------------------------------------------------- | |
544 | * SYPCR - System Protection Control 11-9 | |
545 | * SYPCR can only be written once after reset! | |
546 | *----------------------------------------------------------------------- | |
547 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
548 | */ | |
549 | #define CFG_SYPCR (SYPCR_SWTC |\ | |
550 | SYPCR_BMT |\ | |
551 | SYPCR_PBME |\ | |
552 | SYPCR_LBME |\ | |
553 | SYPCR_SWRI |\ | |
554 | SYPCR_SWP) | |
555 | ||
556 | /*----------------------------------------------------------------------- | |
557 | * TMCNTSC - Time Counter Status and Control 4-40 | |
558 | *----------------------------------------------------------------------- | |
559 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
560 | * and enable Time Counter | |
561 | */ | |
562 | #define CFG_TMCNTSC (TMCNTSC_SEC |\ | |
563 | TMCNTSC_ALR |\ | |
564 | TMCNTSC_TCF |\ | |
565 | TMCNTSC_TCE) | |
566 | ||
567 | /*----------------------------------------------------------------------- | |
568 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
569 | *----------------------------------------------------------------------- | |
570 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
571 | * Periodic timer | |
572 | */ | |
573 | #define CFG_PISCR (PISCR_PS |\ | |
574 | PISCR_PTF |\ | |
575 | PISCR_PTE) | |
576 | ||
577 | /*----------------------------------------------------------------------- | |
578 | * SCCR - System Clock Control 9-8 | |
579 | *----------------------------------------------------------------------- | |
580 | */ | |
581 | #define CFG_SCCR 0 | |
582 | ||
583 | /*----------------------------------------------------------------------- | |
584 | * RCCR - RISC Controller Configuration 13-7 | |
585 | *----------------------------------------------------------------------- | |
586 | */ | |
587 | #define CFG_RCCR 0 | |
588 | ||
589 | /* | |
590 | * Initialize Memory Controller: | |
591 | * | |
592 | * Bank Bus Machine PortSz Device | |
593 | * ---- --- ------- ------ ------ | |
594 | * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) * | |
595 | * 1 unused | |
596 | * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB) | |
597 | * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB) | |
598 | * 4 Local SDRAM 32 bit SDRAM (on board - 16MB) | |
599 | * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB) | |
600 | * 6 60x GPCM 8 bit FLASH (on board - 2MB) * | |
601 | * 7 60x GPCM 8 bit LEDs, switches | |
602 | * | |
603 | * (*) This configuration requires the PPMC8260 be configured | |
604 | * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to | |
605 | * the on board FLASH. In other words, JP24 should have | |
606 | * pins 1 and 2 jumpered and pins 3 and 4 jumpered. | |
607 | * | |
608 | */ | |
609 | ||
610 | /*----------------------------------------------------------------------- | |
611 | * BR0,BR1 - Base Register | |
612 | * Ref: Section 10.3.1 on page 10-14 | |
613 | * OR0,OR1 - Option Register | |
614 | * Ref: Section 10.3.2 on page 10-18 | |
615 | *----------------------------------------------------------------------- | |
616 | */ | |
617 | ||
618 | /* Bank 0,1 - FLASH SIMM | |
619 | * | |
620 | * This expects the FLASH SIMM to be connected to *CS0 | |
621 | * It consists of 4 AM29F080B parts. | |
622 | * | |
623 | * Note: For the 4 MB SIMM, *CS1 is unused. | |
624 | */ | |
625 | ||
626 | /* BR0 is configured as follows: | |
627 | * | |
628 | * - Base address of 0xFE000000 | |
629 | * - 32 bit port size | |
630 | * - Data errors checking is disabled | |
631 | * - Read and write access | |
632 | * - GPCM 60x bus | |
633 | * - Access are handled by the memory controller according to MSEL | |
634 | * - Not used for atomic operations | |
635 | * - No data pipelining is done | |
636 | * - Valid | |
637 | */ | |
638 | #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ | |
639 | BRx_PS_32 |\ | |
640 | BRx_MS_GPCM_P |\ | |
641 | BRx_V) | |
642 | ||
643 | /* OR0 is configured as follows: | |
644 | * | |
645 | * - 32 MB | |
646 | * - *BCTL0 is asserted upon access to the current memory bank | |
647 | * - *CW / *WE are negated a quarter of a clock earlier | |
648 | * - *CS is output at the same time as the address lines | |
649 | * - Uses a clock cycle length of 5 | |
650 | * - *PSDVAL is generated internally by the memory controller | |
651 | * unless *GTA is asserted earlier externally. | |
652 | * - Relaxed timing is generated by the GPCM for accesses | |
653 | * initiated to this memory region. | |
654 | * - One idle clock is inserted between a read access from the | |
655 | * current bank and the next access. | |
656 | */ | |
657 | #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ | |
658 | ORxG_CSNT |\ | |
659 | ORxG_ACS_DIV1 |\ | |
660 | ORxG_SCY_5_CLK |\ | |
661 | ORxG_TRLX |\ | |
662 | ORxG_EHTR) | |
663 | ||
664 | /*----------------------------------------------------------------------- | |
665 | * BR2,BR3 - Base Register | |
666 | * Ref: Section 10.3.1 on page 10-14 | |
667 | * OR2,OR3 - Option Register | |
668 | * Ref: Section 10.3.2 on page 10-16 | |
669 | *----------------------------------------------------------------------- | |
670 | */ | |
671 | ||
672 | /* | |
673 | * Bank 2,3 - 128 MB SDRAM DIMM | |
674 | */ | |
675 | ||
676 | /* With a 128 MB DIMM, the BR2 is configured as follows: | |
677 | * | |
678 | * - Base address of 0x00000000/0x08000000 | |
679 | * - 64 bit port size (60x bus only) | |
680 | * - Data errors checking is disabled | |
681 | * - Read and write access | |
682 | * - SDRAM 60x bus | |
683 | * - Access are handled by the memory controller according to MSEL | |
684 | * - Not used for atomic operations | |
685 | * - No data pipelining is done | |
686 | * - Valid | |
687 | */ | |
688 | #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ | |
689 | BRx_PS_64 |\ | |
690 | BRx_MS_SDRAM_P |\ | |
691 | BRx_V) | |
692 | ||
693 | #define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ | |
694 | BRx_PS_64 |\ | |
695 | BRx_MS_SDRAM_P |\ | |
696 | BRx_V) | |
697 | ||
698 | /* With a 128 MB DIMM, the OR2 is configured as follows: | |
699 | * | |
700 | * - 128 MB | |
701 | * - 4 internal banks per device | |
702 | * - Row start address bit is A8 with PSDMR[PBI] = 0 | |
703 | * - 13 row address lines | |
704 | * - Back-to-back page mode | |
705 | * - Internal bank interleaving within save device enabled | |
706 | */ | |
707 | ||
708 | #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ | |
709 | ORxS_BPD_4 |\ | |
710 | ORxS_ROWST_PBI0_A7 |\ | |
711 | ORxS_NUMR_13) | |
712 | ||
713 | #define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ | |
714 | ORxS_BPD_4 |\ | |
715 | ORxS_ROWST_PBI0_A7 |\ | |
716 | ORxS_NUMR_13) | |
717 | ||
718 | ||
719 | /*----------------------------------------------------------------------- | |
720 | * PSDMR - 60x Bus SDRAM Mode Register | |
721 | * Ref: Section 10.3.3 on page 10-21 | |
722 | *----------------------------------------------------------------------- | |
723 | */ | |
724 | ||
725 | /* With a 128 MB DIMM, the PSDMR is configured as follows: | |
726 | * | |
727 | * - Page Based Interleaving, | |
728 | * - Refresh Enable, | |
729 | * - Normal Operation | |
730 | * - Address Multiplexing where A5 is output on A14 pin | |
731 | * (A6 on A15, and so on), | |
732 | * - use address pins A13-A15 as bank select, | |
733 | * - A9 is output on SDA10 during an ACTIVATE command, | |
734 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
735 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
736 | * is 3 clocks, | |
737 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
738 | * 2 clocks, | |
739 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
740 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
741 | * - External Address Multiplexing enabled | |
742 | * - CAS Latency is 2. | |
743 | */ | |
744 | #define CFG_PSDMR (PSDMR_RFEN |\ | |
745 | PSDMR_SDAM_A14_IS_A5 |\ | |
746 | PSDMR_BSMA_A13_A15 |\ | |
747 | PSDMR_SDA10_PBI0_A9 |\ | |
748 | PSDMR_RFRC_7_CLK |\ | |
749 | PSDMR_PRETOACT_3W |\ | |
750 | PSDMR_ACTTORW_2W |\ | |
751 | PSDMR_LDOTOPRE_1C |\ | |
752 | PSDMR_WRC_1C |\ | |
753 | PSDMR_EAMUX |\ | |
754 | PSDMR_CL_2) | |
755 | ||
756 | ||
757 | #define CFG_PSRT 0x0e | |
758 | #define CFG_MPTPR MPTPR_PTP_DIV32 | |
759 | ||
760 | ||
761 | /*----------------------------------------------------------------------- | |
762 | * BR4 - Base Register | |
763 | * Ref: Section 10.3.1 on page 10-14 | |
764 | * OR4 - Option Register | |
765 | * Ref: Section 10.3.2 on page 10-16 | |
766 | *----------------------------------------------------------------------- | |
767 | */ | |
768 | ||
769 | /* | |
770 | * Bank 4 - On board SDRAM | |
771 | * | |
772 | */ | |
773 | /* With 16 MB of onboard SDRAM BR4 is configured as follows | |
774 | * | |
775 | * - Base address 0x38000000 | |
776 | * - 32 bit port size | |
777 | * - Data error checking disabled | |
778 | * - Read/Write access | |
779 | * - SDRAM local bus | |
780 | * - Not used for atomic operations | |
781 | * - No data pipelining is done | |
782 | * - Valid | |
783 | * | |
784 | */ | |
785 | ||
786 | #define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\ | |
787 | BRx_PS_32 |\ | |
788 | BRx_DECC_NONE |\ | |
789 | BRx_MS_SDRAM_L |\ | |
790 | BRx_V) | |
791 | ||
792 | /* | |
793 | * With 16MB SDRAM, OR4 is configured as follows | |
794 | * - 4 internal banks per device | |
795 | * - Row start address bit is A10 with LSDMR[PBI] = 0 | |
796 | * - 12 row address lines | |
797 | * - Back-to-back page mode | |
798 | * - Internal bank interleaving within save device enabled | |
799 | */ | |
800 | ||
801 | #define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE) |\ | |
802 | ORxS_BPD_4 |\ | |
803 | ORxS_ROWST_PBI0_A10 |\ | |
804 | ORxS_NUMR_12) | |
805 | ||
806 | ||
807 | /*----------------------------------------------------------------------- | |
808 | * LSDMR - Local Bus SDRAM Mode Register | |
809 | * Ref: Section 10.3.4 on page 10-24 | |
810 | *----------------------------------------------------------------------- | |
811 | */ | |
812 | ||
813 | /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows: | |
814 | * | |
815 | * - Page Based Interleaving, | |
816 | * - Refresh Enable, | |
817 | * - Normal Operation | |
818 | * - Address Multiplexing where A5 is output on A13 pin | |
819 | * (A6 on A15, and so on), | |
820 | * - use address pins A15-A17 as bank select, | |
821 | * - A11 is output on SDA10 during an ACTIVATE command, | |
822 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
823 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
824 | * is 2 clocks, | |
825 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
826 | * 2 clocks, | |
827 | * - SDRAM burst length is 8 | |
828 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
829 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
830 | * - External Address Multiplexing disabled | |
831 | * - CAS Latency is 2. | |
832 | */ | |
833 | #define CFG_LSDMR (PSDMR_RFEN |\ | |
834 | PSDMR_SDAM_A13_IS_A5 |\ | |
835 | PSDMR_BSMA_A15_A17 |\ | |
836 | PSDMR_SDA10_PBI0_A11 |\ | |
837 | PSDMR_RFRC_7_CLK |\ | |
838 | PSDMR_PRETOACT_2W |\ | |
839 | PSDMR_ACTTORW_2W |\ | |
840 | PSDMR_BL |\ | |
841 | PSDMR_LDOTOPRE_1C |\ | |
842 | PSDMR_WRC_1C |\ | |
843 | PSDMR_CL_2) | |
844 | ||
845 | #define CFG_LSRT 0x0e | |
846 | ||
847 | /*----------------------------------------------------------------------- | |
848 | * BR5 - Base Register | |
849 | * Ref: Section 10.3.1 on page 10-14 | |
850 | * OR5 - Option Register | |
851 | * Ref: Section 10.3.2 on page 10-16 | |
852 | *----------------------------------------------------------------------- | |
853 | */ | |
854 | ||
855 | /* | |
856 | * Bank 5 EEProm and Mailbox | |
857 | * | |
858 | * The EEPROM and mailbox live on the same chip select. | |
859 | * the eeprom is selected if the MSb of the address is set and the mailbox is | |
860 | * selected if the MSb of the address is clear. | |
861 | * | |
862 | */ | |
863 | ||
864 | /* BR5 is configured as follows: | |
865 | * | |
866 | * - Base address of 0x32000000/0xF2000000 | |
867 | * - 8 bit | |
868 | * - Data error checking disabled | |
869 | * - Read/Write access | |
870 | * - GPCM 60x Bus | |
871 | * - SDRAM local bus | |
872 | * - No data pipelining is done | |
873 | * - Valid | |
874 | */ | |
875 | ||
876 | #define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\ | |
877 | BRx_PS_8 |\ | |
878 | BRx_DECC_NONE |\ | |
879 | BRx_MS_GPCM_P |\ | |
880 | BRx_V) | |
881 | /* OR5 is configured as follows | |
882 | * - buffer control enabled | |
883 | * - chip select negated normally | |
884 | * - CS output 1/2 clock after address | |
885 | * - 15 wait states | |
886 | * - *PSDVAL is generated internally by the memory controller | |
887 | * unless *GTA is asserted earlier externally. | |
888 | * - Relaxed timing is generated by the GPCM for accesses | |
889 | * initiated to this memory region. | |
890 | * - One idle clock is inserted between a read access from the | |
891 | * current bank and the next access. | |
892 | */ | |
893 | ||
894 | #define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\ | |
895 | ORxG_ACS_DIV2 |\ | |
896 | ORxG_SCY_15_CLK |\ | |
897 | ORxG_TRLX |\ | |
898 | ORxG_EHTR) | |
899 | ||
900 | /*----------------------------------------------------------------------- | |
901 | * BR6 - Base Register | |
902 | * Ref: Section 10.3.1 on page 10-14 | |
903 | * OR6 - Option Register | |
904 | * Ref: Section 10.3.2 on page 10-18 | |
905 | *----------------------------------------------------------------------- | |
906 | */ | |
907 | ||
908 | /* Bank 6 - I/O select | |
909 | * | |
910 | */ | |
911 | ||
912 | /* BR6 is configured as follows: | |
913 | * | |
914 | * - Base address of 0xE0000000 | |
915 | * - 16 bit port size | |
916 | * - Data errors checking is disabled | |
917 | * - Read and write access | |
918 | * - GPCM 60x bus | |
919 | * - Access are handled by the memory controller according to MSEL | |
920 | * - Not used for atomic operations | |
921 | * - No data pipelining is done | |
922 | * - Valid | |
923 | */ | |
924 | #define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\ | |
925 | BRx_PS_16 |\ | |
926 | BRx_MS_GPCM_P |\ | |
927 | BRx_V) | |
928 | ||
929 | /* OR6 is configured as follows | |
930 | * - buffer control enabled | |
931 | * - chip select negated normally | |
932 | * - CS output 1/2 clock after address | |
933 | * - 15 wait states | |
934 | * - *PSDVAL is generated internally by the memory controller | |
935 | * unless *GTA is asserted earlier externally. | |
936 | * - Relaxed timing is generated by the GPCM for accesses | |
937 | * initiated to this memory region. | |
938 | * - One idle clock is inserted between a read access from the | |
939 | * current bank and the next access. | |
940 | */ | |
941 | ||
942 | #define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\ | |
943 | ORxG_ACS_DIV2 |\ | |
944 | ORxG_SCY_15_CLK |\ | |
945 | ORxG_TRLX |\ | |
946 | ORxG_EHTR) | |
947 | ||
948 | ||
949 | /*----------------------------------------------------------------------- | |
950 | * BR7 - Base Register | |
951 | * Ref: Section 10.3.1 on page 10-14 | |
952 | * OR7 - Option Register | |
953 | * Ref: Section 10.3.2 on page 10-18 | |
954 | *----------------------------------------------------------------------- | |
955 | */ | |
956 | ||
957 | /* Bank 7 - LEDs and switches | |
958 | * | |
959 | * LEDs are at 0x00001 (write only) | |
960 | * switches are at 0x00001 (read only) | |
961 | */ | |
962 | #ifdef CFG_LED_BASE | |
963 | ||
964 | /* BR7 is configured as follows: | |
965 | * | |
966 | * - Base address of 0xA0000000 | |
967 | * - 8 bit port size | |
968 | * - Data errors checking is disabled | |
969 | * - Read and write access | |
970 | * - GPCM 60x bus | |
971 | * - Access are handled by the memory controller according to MSEL | |
972 | * - Not used for atomic operations | |
973 | * - No data pipelining is done | |
974 | * - Valid | |
975 | */ | |
976 | #define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\ | |
977 | BRx_PS_8 |\ | |
978 | BRx_DECC_NONE |\ | |
979 | BRx_MS_GPCM_P |\ | |
980 | BRx_V) | |
981 | ||
982 | /* OR7 is configured as follows: | |
983 | * | |
984 | * - 1 byte | |
985 | * - *BCTL0 is asserted upon access to the current memory bank | |
986 | * - *CW / *WE are negated a quarter of a clock earlier | |
987 | * - *CS is output at the same time as the address lines | |
988 | * - Uses a clock cycle length of 15 | |
989 | * - *PSDVAL is generated internally by the memory controller | |
990 | * unless *GTA is asserted earlier externally. | |
991 | * - Relaxed timing is generated by the GPCM for accesses | |
992 | * initiated to this memory region. | |
993 | * - One idle clock is inserted between a read access from the | |
994 | * current bank and the next access. | |
995 | */ | |
996 | #define CFG_OR7_PRELIM (ORxG_AM_MSK |\ | |
997 | ORxG_CSNT |\ | |
998 | ORxG_ACS_DIV1 |\ | |
999 | ORxG_SCY_15_CLK |\ | |
1000 | ORxG_TRLX |\ | |
1001 | ORxG_EHTR) | |
1002 | #endif /* CFG_LED_BASE */ | |
1003 | ||
1004 | /* | |
1005 | * Internal Definitions | |
1006 | * | |
1007 | * Boot Flags | |
1008 | */ | |
1009 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
1010 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
1011 | ||
1012 | #endif /* __CONFIG_H */ |