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Commit | Line | Data |
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939b150a DP |
1 | /* |
2 | * U-boot - Configuration file for PR1 Appliance | |
3 | * | |
4 | * based on bf537-stamp.h | |
5 | * Copyright (c) Switchfin Org. <dpn@switchfin.org> | |
6 | */ | |
7 | ||
8 | #ifndef __CONFIG_PR1_H__ | |
9 | #define __CONFIG_PR1_H__ | |
10 | ||
11 | #include <asm/config-pre.h> | |
12 | ||
13 | ||
14 | /* | |
15 | * Processor Settings | |
16 | */ | |
17 | #define CONFIG_BFIN_CPU bf537-0.3 | |
18 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER | |
19 | ||
20 | ||
21 | /* | |
22 | * Clock Settings | |
23 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
24 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
25 | */ | |
26 | /* CONFIG_CLKIN_HZ is any value in Hz */ | |
27 | #define CONFIG_CLKIN_HZ 25000000 | |
28 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
29 | /* 1 = CLKIN / 2 */ | |
30 | #define CONFIG_CLKIN_HALF 0 | |
31 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
32 | /* 1 = bypass PLL */ | |
33 | #define CONFIG_PLL_BYPASS 0 | |
34 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
35 | /* Values can range from 0-63 (where 0 means 64) */ | |
36 | #define CONFIG_VCO_MULT 24 | |
37 | /* CCLK_DIV controls the core clock divider */ | |
38 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
39 | #define CONFIG_CCLK_DIV 1 | |
40 | /* SCLK_DIV controls the system clock divider */ | |
41 | /* Values can range from 1-15 */ | |
42 | #define CONFIG_SCLK_DIV 5 | |
43 | ||
44 | ||
45 | /* | |
46 | * Memory Settings | |
47 | */ | |
48 | #define CONFIG_MEM_ADD_WDTH 11 | |
49 | #define CONFIG_MEM_SIZE 128 | |
50 | ||
51 | #define CONFIG_EBIU_SDRRC_VAL 0x306 | |
52 | #define CONFIG_EBIU_SDGCTL_VAL 0x8091998d | |
53 | ||
54 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF | |
55 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 | |
56 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 | |
57 | ||
58 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
59 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) | |
60 | ||
61 | ||
62 | /* | |
63 | * Network Settings | |
64 | */ | |
65 | #ifndef __ADSPBF534__ | |
66 | #define ADI_CMDS_NETWORK 1 | |
67 | #define CONFIG_BFIN_MAC | |
68 | #define CONFIG_NETCONSOLE | |
69 | #endif | |
70 | #define CONFIG_HOSTNAME pr1 | |
71 | #define CONFIG_TFTP_BLOCKSIZE 4404 | |
939b150a DP |
72 | |
73 | ||
74 | /* | |
75 | * Flash Settings | |
76 | */ | |
77 | #define CONFIG_SYS_NO_FLASH /* We have no parallel FLASH */ | |
78 | ||
79 | ||
80 | /* | |
81 | * SPI Settings | |
82 | */ | |
83 | #define CONFIG_BFIN_SPI | |
84 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
85 | #define CONFIG_SF_DEFAULT_SPEED 30000000 | |
86 | #define CONFIG_SPI_FLASH | |
87 | #define CONFIG_SPI_FLASH_STMICRO | |
88 | ||
89 | ||
90 | /* | |
91 | * Env Storage Settings | |
92 | */ | |
93 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
94 | #define CONFIG_ENV_OFFSET 0x10000 | |
95 | #define CONFIG_ENV_SIZE 0x2000 | |
96 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
97 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR | |
98 | ||
99 | ||
100 | /* | |
101 | * I2C Settings | |
102 | */ | |
c469703b | 103 | #define CONFIG_SYS_I2C |
fea9b69a | 104 | #define CONFIG_SYS_I2C_ADI |
939b150a DP |
105 | |
106 | ||
107 | /* | |
108 | * NAND Settings | |
109 | */ | |
110 | #define CONFIG_NAND_PLAT | |
111 | #define CONFIG_SYS_NAND_BASE 0x20000000 | |
112 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
113 | ||
114 | #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) | |
115 | #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) | |
116 | #define BFIN_NAND_WRITE(addr, cmd) \ | |
117 | do { \ | |
118 | bfin_write8(addr, cmd); \ | |
119 | SSYNC(); \ | |
120 | } while (0) | |
121 | ||
122 | #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) | |
123 | #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) | |
124 | #define NAND_PLAT_GPIO_DEV_READY GPIO_PF9 | |
125 | ||
126 | /* | |
127 | * Misc Settings | |
128 | */ | |
129 | #define CONFIG_BAUDRATE 115200 | |
130 | #define CONFIG_RTC_BFIN | |
131 | #define CONFIG_UART_CONSOLE 0 | |
132 | #define CONFIG_SYS_PROMPT "pr1>" | |
133 | #define CONFIG_BOOTCOMMAND "run nandboot" | |
134 | #define CONFIG_BOOTDELAY 2 | |
135 | #define CONFIG_LOADADDR 0x2000000 | |
939b150a DP |
136 | |
137 | /* | |
138 | * Pull in common ADI header for remaining command/environment setup | |
139 | */ | |
140 | #include <configs/bfin_adi_common.h> | |
141 | ||
142 | /* | |
143 | * Overwrite some settings defined in bfin_adi_common.h | |
144 | */ | |
145 | #undef NAND_ENV_SETTINGS | |
146 | #define NAND_ENV_SETTINGS \ | |
147 | "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ | |
148 | "nandboot=" \ | |
149 | "nand read $(loadaddr) 0x0 0x900000;" \ | |
150 | "run nandargs;" \ | |
151 | "bootm" \ | |
152 | "\0" | |
153 | ||
154 | #endif |