[thirdparty/u-boot.git] / include / configs / presidio_asic.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2020 Cortina Access Inc.
 *
 * Configuration for Cortina-Access Presidio board
 */

#ifndef __PRESIDIO_ASIC_H
#define __PRESIDIO_ASIC_H

#define CONFIG_SYS_INIT_SP_ADDR		0x00100000
#define CONFIG_SYS_BOOTM_LEN		0x00c00000

/* Generic Timer Definitions */
#define CONFIG_SYS_TIMER_RATE		25000000
#define CONFIG_SYS_TIMER_COUNTER	0xf4321008

/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
 * does not yet support DT. Thus define it here.
 */
#define GICD_BASE			0xf7011000
#define GICC_BASE			0xf7012000

#define CONFIG_SYS_TIMER_BASE		0xf4321000

/* Use external clock source */
#define PRESIDIO_APB_CLK		125000000
#define CORTINA_PER_IO_FREQ		PRESIDIO_APB_CLK

/* Cortina Serial Configuration */
#define CORTINA_UART_CLOCK		(PRESIDIO_APB_CLK)
#define CORTINA_SERIAL_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
					 (void *)CONFIG_SYS_SERIAL1}

#define CONFIG_SYS_SERIAL0		PER_UART0_CFG
#define CONFIG_SYS_SERIAL1		PER_UART1_CFG

/* SDRAM Bank #1 */
#define DDR_BASE			0x00000000
#define PHYS_SDRAM_1			DDR_BASE
#define PHYS_SDRAM_1_SIZE		0x80000000 /* 2GB */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define KSEG1_ATU_XLAT(x) (x)

/* HW REG ADDR */
#define NI_READ_POLL_COUNT                      1000
#define CA_NI_MDIO_REG_BASE                     0xF4338
#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET          0x010
#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET          0x014
#define NI_HV_PT_BASE                           0x400
#define NI_HV_XRAM_BASE                         0x820
#define GLOBAL_BLOCK_RESET_OFFSET               0x04
#define GLOBAL_GLOBAL_CONFIG_OFFSET             0x20
#define GLOBAL_IO_DRIVE_CONTROL_OFFSET          0x4c

/* max command args */
#define CONFIG_EXTRA_ENV_SETTINGS	"silent=y\0"

/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
	#define CONFIG_SYS_MAX_NAND_DEVICE      1
	#define CONFIG_SYS_NAND_BASE            CONFIG_SYS_FLASH_BASE
	#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
#endif

#endif /* __PRESIDIO_ASIC_H */
Commit	Line	Data
7d706a88 AN	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright (C) 2020 Cortina Access Inc.
	4	*
c34a9275	5	* Configuration for Cortina-Access Presidio board
7d706a88 AN	6	*/
	7
	8	#ifndef __PRESIDIO_ASIC_H
	9	#define __PRESIDIO_ASIC_H
	10
7d706a88 AN	11	#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
	12	#define CONFIG_SYS_BOOTM_LEN 0x00c00000
	13
	14	/* Generic Timer Definitions */
c5b9bf55	15	#define CONFIG_SYS_TIMER_RATE 25000000
7d706a88 AN	16	#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
	17
	18	/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
	19	* does not yet support DT. Thus define it here.
	20	*/
7d706a88 AN	21	#define GICD_BASE 0xf7011000
	22	#define GICC_BASE 0xf7012000
	23
7d706a88 AN	24	#define CONFIG_SYS_TIMER_BASE 0xf4321000
	25
	26	/* Use external clock source */
	27	#define PRESIDIO_APB_CLK 125000000
	28	#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
	29
	30	/* Cortina Serial Configuration */
	31	#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
	32	#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
	33	(void *)CONFIG_SYS_SERIAL1}
	34
7d706a88 AN	35	#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
	36	#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
	37
7d706a88 AN	38	/* SDRAM Bank #1 */
	39	#define DDR_BASE 0x00000000
	40	#define PHYS_SDRAM_1 DDR_BASE
	41	#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
	42	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	43
	44	/* Console I/O Buffer Size */
	45	#define CONFIG_SYS_CBSIZE 256
	46	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	47	sizeof(CONFIG_SYS_PROMPT) + 16)
	48	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	49
c34a9275 AN	50	#define KSEG1_ATU_XLAT(x) (x)
	51
	52	/* HW REG ADDR */
	53	#define NI_READ_POLL_COUNT 1000
	54	#define CA_NI_MDIO_REG_BASE 0xF4338
	55	#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010
	56	#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014
	57	#define NI_HV_PT_BASE 0x400
	58	#define NI_HV_XRAM_BASE 0x820
	59	#define GLOBAL_BLOCK_RESET_OFFSET 0x04
	60	#define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20
	61	#define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c
	62
7d706a88	63	/* max command args */
7d706a88 AN	64	#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
7d706a88 AN	65
34a5addb KL	66	/* nand driver parameters */
34a5addb KL	67	#ifdef CONFIG_TARGET_PRESIDIO_ASIC
34a5addb	68	#define CONFIG_SYS_MAX_NAND_DEVICE 1
34a5addb KL	69	#define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
	70	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	71	#endif
	72
7d706a88	73	#endif /* __PRESIDIO_ASIC_H */