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70a2047f WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * Copied from lubbock.h | |
10 | * | |
11 | * (C) Copyright 2004 | |
12 | * BEC Systems <http://bec-systems.com> | |
13 | * Cliff Brake <cliff.brake@gmail.com> | |
14 | * Configuation settings for the Accelent/Vibren PXA255 IDP | |
15 | * | |
3765b3e7 | 16 | * SPDX-License-Identifier: GPL-2.0+ |
70a2047f WD |
17 | */ |
18 | ||
19 | #ifndef __CONFIG_H | |
20 | #define __CONFIG_H | |
21 | ||
22 | #include <asm/arch/pxa-regs.h> | |
23 | ||
24 | /* | |
2a4741d9 | 25 | * If we are developing, we might want to start U-Boot from RAM |
70a2047f WD |
26 | * so we MUST NOT initialize critical regs like mem-timing ... |
27 | */ | |
2a4741d9 | 28 | #undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ |
65bd6a90 | 29 | #define CONFIG_SYS_TEXT_BASE 0x0 |
70a2047f WD |
30 | |
31 | /* | |
32 | * define the following to enable debug blinks. A debug blink function | |
33 | * must be defined in memsetup.S | |
34 | */ | |
35 | #undef DEBUG_BLINK_ENABLE | |
36 | #undef DEBUG_BLINKC_ENABLE | |
37 | ||
38 | /* | |
39 | * High Level Configuration Options | |
40 | * (easy to change) | |
41 | */ | |
abc20aba | 42 | #define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ |
70a2047f WD |
43 | |
44 | #undef CONFIG_LCD | |
45 | #ifdef CONFIG_LCD | |
0698095a | 46 | #define CONFIG_PXA_LCD |
70a2047f WD |
47 | #define CONFIG_SHARP_LM8V31 |
48 | #endif | |
49 | ||
50 | #define CONFIG_MMC 1 | |
2a4741d9 | 51 | #define CONFIG_DOS_PARTITION 1 |
9660e442 | 52 | #define CONFIG_BOARD_LATE_INIT |
70a2047f | 53 | |
b3acb6cd | 54 | /* we will never enable dcache, because we have to setup MMU first */ |
e47f2db5 | 55 | #define CONFIG_SYS_DCACHE_OFF |
b3acb6cd | 56 | |
70a2047f WD |
57 | /* |
58 | * Size of malloc() pool | |
59 | */ | |
6d0f6bcf | 60 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
70a2047f WD |
61 | |
62 | /* | |
63 | * PXA250 IDP memory map information | |
64 | */ | |
65 | ||
66 | #define IDP_CS5_ETH_OFFSET 0x03400000 | |
67 | ||
68 | ||
69 | /* | |
70 | * Hardware drivers | |
71 | */ | |
7194ab80 | 72 | #define CONFIG_SMC91111 |
70a2047f WD |
73 | #define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) |
74 | #define CONFIG_SMC_USE_32_BIT 1 | |
75 | /* #define CONFIG_SMC_USE_IOFUNCS */ | |
76 | ||
77 | /* the following has to be set high -- suspect something is wrong with | |
78 | * with the tftp timeout routines. FIXME!!! | |
79 | */ | |
80 | #define CONFIG_NET_RETRY_COUNT 100 | |
81 | ||
82 | /* | |
83 | * select serial console configuration | |
84 | */ | |
379be585 | 85 | #define CONFIG_PXA_SERIAL |
70a2047f | 86 | #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ |
ce6971cd | 87 | #define CONFIG_CONS_INDEX 3 |
70a2047f WD |
88 | |
89 | /* allow to overwrite serial and ethaddr */ | |
90 | #define CONFIG_ENV_OVERWRITE | |
91 | ||
92 | #define CONFIG_BAUDRATE 115200 | |
93 | ||
70a2047f | 94 | |
079a136c JL |
95 | /* |
96 | * BOOTP options | |
97 | */ | |
98 | #define CONFIG_BOOTP_BOOTFILESIZE | |
99 | #define CONFIG_BOOTP_BOOTPATH | |
100 | #define CONFIG_BOOTP_GATEWAY | |
101 | #define CONFIG_BOOTP_HOSTNAME | |
102 | ||
103 | ||
26a34560 JL |
104 | /* |
105 | * Command line configuration. | |
106 | */ | |
107 | #include <config_cmd_default.h> | |
108 | ||
26a34560 JL |
109 | #define CONFIG_CMD_FAT |
110 | #define CONFIG_CMD_DHCP | |
111 | ||
70a2047f WD |
112 | #define CONFIG_BOOTDELAY 3 |
113 | #define CONFIG_BOOTCOMMAND "bootm 40000" | |
114 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" | |
25dbe98a WD |
115 | |
116 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
117 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
118 | /* #define CONFIG_INITRD_TAG 1 */ | |
70a2047f WD |
119 | |
120 | /* | |
121 | * Current memory map for Vibren supplied Linux images: | |
122 | * | |
123 | * Flash: | |
124 | * 0 - 0x3ffff (size = 0x40000): bootloader | |
125 | * 0x40000 - 0x13ffff (size = 0x100000): kernel | |
126 | * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs | |
127 | * | |
128 | * RAM: | |
129 | * 0xa0008000 - kernel is loaded | |
130 | * 0xa3000000 - Uboot runs (48MB into RAM) | |
131 | * | |
132 | */ | |
133 | ||
134 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
135 | "prog_boot_mmc=" \ | |
136 | "mw.b 0xa0000000 0xff 0x40000; " \ | |
137 | "if mmcinit && " \ | |
138 | "fatload mmc 0 0xa0000000 u-boot.bin; " \ | |
139 | "then " \ | |
140 | "protect off 0x0 0x3ffff; " \ | |
141 | "erase 0x0 0x3ffff; " \ | |
142 | "cp.b 0xa0000000 0x0 0x40000; " \ | |
143 | "reset;" \ | |
144 | "fi\0" \ | |
145 | "prog_uzImage_mmc=" \ | |
146 | "mw.b 0xa0000000 0xff 0x100000; " \ | |
147 | "if mmcinit && " \ | |
148 | "fatload mmc 0 0xa0000000 uzImage; " \ | |
149 | "then " \ | |
150 | "protect off 0x40000 0xfffff; " \ | |
151 | "erase 0x40000 0xfffff; " \ | |
152 | "cp.b 0xa0000000 0x40000 0x100000; " \ | |
153 | "fi\0" \ | |
154 | "prog_jffs_mmc=" \ | |
155 | "mw.b 0xa0000000 0xff 0x1e00000; " \ | |
156 | "if mmcinit && " \ | |
157 | "fatload mmc 0 0xa0000000 root.jffs; " \ | |
158 | "then " \ | |
159 | "protect off 0x140000 0x1f3ffff; " \ | |
160 | "erase 0x140000 0x1f3ffff; " \ | |
161 | "cp.b 0xa0000000 0x140000 0x1e00000; " \ | |
162 | "fi\0" \ | |
163 | "boot_mmc=" \ | |
164 | "if mmcinit && " \ | |
165 | "fatload mmc 0 0xa1000000 uzImage && " \ | |
166 | "then " \ | |
167 | "bootm 0xa1000000; " \ | |
168 | "fi\0" \ | |
169 | "prog_boot_net=" \ | |
170 | "mw.b 0xa0000000 0xff 0x100000; " \ | |
171 | "if bootp 0xa0000000 u-boot.bin; " \ | |
172 | "then " \ | |
173 | "protect off 0x0 0x3ffff; " \ | |
174 | "erase 0x0 0x3ffff; " \ | |
175 | "cp.b 0xa0000000 0x0 0x40000; " \ | |
176 | "reset; " \ | |
177 | "fi\0" \ | |
178 | "prog_uzImage_net=" \ | |
179 | "mw.b 0xa0000000 0xff 0x100000; " \ | |
180 | "if bootp 0xa0000000 uzImage; " \ | |
181 | "then " \ | |
182 | "protect off 0x40000 0xfffff; " \ | |
183 | "erase 0x40000 0xfffff; " \ | |
184 | "cp.b 0xa0000000 0x40000 0x100000; " \ | |
185 | "fi\0" \ | |
186 | "prog_jffs_net=" \ | |
187 | "mw.b 0xa0000000 0xff 0x1e00000; " \ | |
188 | "if bootp 0xa0000000 root.jffs; " \ | |
189 | "then " \ | |
190 | "protect off 0x140000 0x1f3ffff; " \ | |
191 | "erase 0x140000 0x1f3ffff; " \ | |
192 | "cp.b 0xa0000000 0x140000 0x1e00000; " \ | |
193 | "fi\0" | |
194 | ||
195 | ||
196 | /* "erase_env=" */ | |
197 | /* "protect off" */ | |
198 | ||
199 | ||
26a34560 | 200 | #if defined(CONFIG_CMD_KGDB) |
70a2047f | 201 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
70a2047f WD |
202 | #endif |
203 | ||
204 | /* | |
205 | * Miscellaneous configurable options | |
206 | */ | |
6d0f6bcf | 207 | #define CONFIG_SYS_HUSH_PARSER 1 |
70a2047f | 208 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
210 | #ifdef CONFIG_SYS_HUSH_PARSER | |
211 | #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ | |
70a2047f | 212 | #else |
70a2047f | 213 | #endif |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
215 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
216 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
217 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
218 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
70a2047f | 219 | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
221 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
70a2047f | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ |
70a2047f | 224 | |
6d0f6bcf | 225 | #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ |
70a2047f WD |
226 | |
227 | #define RTC 1 /* enable 32KHz osc */ | |
228 | ||
b03d92e5 | 229 | #ifdef CONFIG_MMC |
831f849f MV |
230 | #define CONFIG_GENERIC_MMC |
231 | #define CONFIG_PXA_MMC_GENERIC | |
b03d92e5 | 232 | #define CONFIG_CMD_MMC |
6d0f6bcf | 233 | #define CONFIG_SYS_MMC_BASE 0xF0000000 |
b03d92e5 | 234 | #endif |
70a2047f | 235 | |
70a2047f WD |
236 | /* |
237 | * Physical Memory Map | |
238 | */ | |
65bd6a90 | 239 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
70a2047f WD |
240 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
241 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
242 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
243 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
244 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
245 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
246 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
247 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
248 | ||
249 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
250 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ | |
251 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
252 | #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ | |
253 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | |
254 | ||
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
256 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | |
70a2047f | 257 | |
6d0f6bcf | 258 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
70a2047f | 259 | |
6ef6eb91 | 260 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
00d5ec93 | 261 | #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 |
6ef6eb91 | 262 | |
70a2047f WD |
263 | /* |
264 | * GPIO settings | |
265 | */ | |
266 | ||
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_GAFR0_L_VAL 0x80001005 |
268 | #define CONFIG_SYS_GAFR0_U_VAL 0xa5128012 | |
269 | #define CONFIG_SYS_GAFR1_L_VAL 0x699a9558 | |
270 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a | |
271 | #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa | |
272 | #define CONFIG_SYS_GAFR2_U_VAL 0x2 | |
273 | #define CONFIG_SYS_GPCR0_VAL 0x1800400 | |
274 | #define CONFIG_SYS_GPCR1_VAL 0x0 | |
275 | #define CONFIG_SYS_GPCR2_VAL 0x0 | |
276 | #define CONFIG_SYS_GPDR0_VAL 0xc1818440 | |
277 | #define CONFIG_SYS_GPDR1_VAL 0xfcffab82 | |
278 | #define CONFIG_SYS_GPDR2_VAL 0x1ffff | |
279 | #define CONFIG_SYS_GPSR0_VAL 0x8000 | |
280 | #define CONFIG_SYS_GPSR1_VAL 0x3f0002 | |
281 | #define CONFIG_SYS_GPSR2_VAL 0x1c000 | |
282 | ||
283 | #define CONFIG_SYS_PSSR_VAL 0x20 | |
70a2047f | 284 | |
65bd6a90 MV |
285 | #define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 |
286 | #define CONFIG_SYS_CKEN 0x0 | |
287 | ||
70a2047f WD |
288 | /* |
289 | * Memory settings | |
290 | */ | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_MSC0_VAL 0x29DCA4D2 |
292 | #define CONFIG_SYS_MSC1_VAL 0x43AC494C | |
293 | #define CONFIG_SYS_MSC2_VAL 0x39D449D4 | |
294 | #define CONFIG_SYS_MDCNFG_VAL 0x090009C9 | |
295 | #define CONFIG_SYS_MDREFR_VAL 0x0085C017 | |
296 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 | |
65bd6a90 MV |
297 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
298 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 | |
70a2047f WD |
299 | |
300 | /* | |
301 | * PCMCIA and CF Interfaces | |
302 | */ | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_MECR_VAL 0x00000003 |
304 | #define CONFIG_SYS_MCMEM0_VAL 0x00014405 | |
305 | #define CONFIG_SYS_MCMEM1_VAL 0x00014405 | |
306 | #define CONFIG_SYS_MCATT0_VAL 0x00014405 | |
307 | #define CONFIG_SYS_MCATT1_VAL 0x00014405 | |
308 | #define CONFIG_SYS_MCIO0_VAL 0x00014405 | |
309 | #define CONFIG_SYS_MCIO1_VAL 0x00014405 | |
70a2047f WD |
310 | |
311 | /* | |
312 | * FLASH and environment organization | |
313 | */ | |
6d0f6bcf | 314 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 315 | #define CONFIG_FLASH_CFI_DRIVER 1 |
70a2047f | 316 | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_MONITOR_BASE 0 |
318 | #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE | |
70a2047f | 319 | |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
321 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
70a2047f | 322 | |
6d0f6bcf | 323 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
70a2047f WD |
324 | |
325 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
327 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
70a2047f WD |
328 | |
329 | /* put cfg at end of flash for now */ | |
5a1aceb0 | 330 | #define CONFIG_ENV_IS_IN_FLASH 1 |
70a2047f | 331 | /* Addr of Environment Sector */ |
0e8d1586 JCPV |
332 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) |
333 | #define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ | |
334 | #define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16) | |
70a2047f WD |
335 | |
336 | #endif /* __CONFIG_H */ |