[people/ms/u-boot.git] / include / configs / qong.h

/*
 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
 *
 * Configuration settings for the Dave/DENX QongEVB-LITE board.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

/* High Level Configuration Options */
#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
#define CONFIG_MX31			/* in a mx31 */
#define CONFIG_QONG

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_TEXT_BASE 0xa0000000

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1536 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

#define CONFIG_MXC_GPIO
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG

#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13XXX

#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	0
#define CONFIG_FSL_PMIC_CLK	100000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN	32

/* FPGA */
#define CONFIG_FPGA
#define CONFIG_QONG_FPGA
#define CONFIG_FPGA_BASE	(CS1_BASE)
#define CONFIG_FPGA_LATTICE
#define CONFIG_FPGA_COUNT	1

#ifdef CONFIG_QONG_FPGA
/* Ethernet */
#define CONFIG_DNET
#define CONFIG_DNET_BASE	(CS1_BASE + QONG_FPGA_PERIPH_SIZE)

/* Framebuffer and LCD */
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MX3
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)

/* USB */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT	2
#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* CONFIG_CMD_USB */

/*
 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
 * initial TFTP transfer, should the user wish one, significantly.
 */
#define CONFIG_ARP_TIMEOUT	200UL

#endif /* CONFIG_QONG_FPGA */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI
#define CONFIG_CMD_UNZIP

#define CONFIG_BOARD_LATE_INIT

#define CONFIG_BOOTDELAY	5

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"uboot_addr=A0000000\0"						\
	"kernel_addr=A00C0000\0"					\
	"ramdisk_addr=A0300000\0"					\
	"u-boot=qong/u-boot.bin\0"					\
	"kernel_addr_r=80800000\0"					\
	"hostname=qong\0"						\
	"bootfile=qong/uImage\0"					\
	"rootpath=/opt/eldk-4.2-arm/armVFP\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm\0"						\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
		" +${filesize};cp.b ${fileaddr} "			\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
	"upd=run load update\0"						\
	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,"	\
		"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,"	\
		"vmode:0\0"						\

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
		sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* memtest works on first 255MB of RAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0xff000000)

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_SYS_HZ			1000

#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */

#define CONFIG_MISC_INIT_R

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	0x10000000	/* 256 MB */

/*
 * NAND driver
 */

#ifndef __ASSEMBLY__
extern void qong_nand_plat_init(void *chip);
extern int qong_nand_rdy(void *chip);
#endif
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_MAX_NAND_DEVICE     1
#define CONFIG_SYS_NAND_BASE	CS3_BASE
#define NAND_PLAT_INIT() qong_nand_plat_init(nand)

#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
#define QONG_NAND_WRITE(addr, cmd) \
	do { \
		__REG8(addr) = cmd; \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip)      (qong_nand_rdy(chip))

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	1024
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */

#define	CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x80000)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* Flash memory is CFI compliant */
#define CONFIG_SYS_FLASH_CFI
/* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_CFI_DRIVER
/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* Use hardware sector protection */
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * Filesystem
 */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,"		\
				"nand0=gen_nand"
#define MTDPARTS_DEFAULT	\
	"mtdparts=physmap-flash.0:"				\
			"512k(U-Boot),128k(env1),128k(env2),"	\
			"2304k(kernel),13m(ramdisk),-(user);"	\
		"gen_nand:"					\
			"128m(nand)"

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)

#define CONFIG_BOARD_EARLY_INIT_F

#endif /* __CONFIG_H */
Commit	Line	Data
0d19f6c8 IY	1	/*
	2	* Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
	3	*
	4	* Configuration settings for the Dave/DENX QongEVB-LITE board.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#ifndef __CONFIG_H
	23	#define __CONFIG_H
	24
86271115	25	#include <asm/arch/imx-regs.h>
0d19f6c8	26
22a9ea97	27	/* High Level Configuration Options */
8a508e30 FE	28	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
	29	#define CONFIG_MX31 /* in a mx31 */
	30	#define CONFIG_QONG
0d19f6c8 IY	31
	32	#define CONFIG_DISPLAY_CPUINFO
	33	#define CONFIG_DISPLAY_BOARDINFO
	34
22a9ea97 SB	35	#define CONFIG_SYS_TEXT_BASE 0xa0000000
22a9ea97 SB	36
8a508e30 FE	37	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	38	#define CONFIG_SETUP_MEMORY_TAGS
	39	#define CONFIG_INITRD_TAG
0d19f6c8 IY	40
	41	/*
	42	* Size of malloc() pool
	43	*/
544aa66a	44	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
0d19f6c8 IY	45
	46	/*
	47	* Hardware drivers
	48	*/
	49
40f6fffe SB	50	#define CONFIG_MXC_UART
40f6fffe SB	51	#define CONFIG_MXC_UART_BASE UART1_BASE
0d19f6c8	52
c4ea1424	53	#define CONFIG_MXC_GPIO
8640c984	54	#define CONFIG_HW_WATCHDOG
abbab703	55	#define CONFIG_IMX_WATCHDOG
45997e0a	56
e98ecd71 SB	57	#define CONFIG_MXC_SPI
e98ecd71 SB	58	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	59	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
4e8b7544	60	#define CONFIG_RTC_MC13XXX
e98ecd71	61
be3b51aa ŁM	62	#define CONFIG_POWER
	63	#define CONFIG_POWER_SPI
	64	#define CONFIG_POWER_FSL
e98ecd71 SB	65	#define CONFIG_FSL_PMIC_BUS 1
	66	#define CONFIG_FSL_PMIC_CS 0
	67	#define CONFIG_FSL_PMIC_CLK 100000
9f481e95	68	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
f33bd087	69	#define CONFIG_FSL_PMIC_BITLEN 32
e98ecd71	70
0d19f6c8	71	/* FPGA */
b9eb3fdf	72	#define CONFIG_FPGA
8a508e30	73	#define CONFIG_QONG_FPGA
0d19f6c8	74	#define CONFIG_FPGA_BASE (CS1_BASE)
b9eb3fdf SB	75	#define CONFIG_FPGA_LATTICE
b9eb3fdf SB	76	#define CONFIG_FPGA_COUNT 1
0d19f6c8 IY	77
	78	#ifdef CONFIG_QONG_FPGA
	79	/* Ethernet */
8a508e30	80	#define CONFIG_DNET
0d19f6c8	81	#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
0d19f6c8	82
7c8cf0d0	83	/* Framebuffer and LCD */
62a22dca HR	84	#define CONFIG_VIDEO
62a22dca HR	85	#define CONFIG_CFB_CONSOLE
7c8cf0d0	86	#define CONFIG_VIDEO_MX3
62a22dca HR	87	#define CONFIG_VIDEO_LOGO
	88	#define CONFIG_VIDEO_SW_CURSOR
	89	#define CONFIG_VGA_AS_SINGLE_DEVICE
7c8cf0d0	90	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
62a22dca	91	#define CONFIG_SPLASH_SCREEN
7c8cf0d0 SB	92	#define CONFIG_CMD_BMP
7c8cf0d0 SB	93	#define CONFIG_BMP_16BPP
544aa66a WD	94	#define CONFIG_VIDEO_BMP_GZIP
544aa66a WD	95	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
7c8cf0d0	96
d7dc464b SB	97	/* USB */
	98	#define CONFIG_CMD_USB
	99	#ifdef CONFIG_CMD_USB
	100	#define CONFIG_USB_EHCI /* Enable EHCI USB support */
	101	#define CONFIG_USB_EHCI_MXC
	102	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	103	#define CONFIG_MXC_USB_PORT 2
	104	#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI \| MXC_EHCI_UTMI_8BIT)
	105	#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
	106	#define CONFIG_EHCI_IS_TDI
	107	#define CONFIG_USB_STORAGE
	108	#define CONFIG_DOS_PARTITION
	109	#define CONFIG_SUPPORT_VFAT
b952c24a	110	#define CONFIG_CMD_EXT2
d7dc464b SB	111	#define CONFIG_CMD_FAT
	112	#endif /* CONFIG_CMD_USB */
	113
0d19f6c8 IY	114	/*
	115	* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
	116	* initial TFTP transfer, should the user wish one, significantly.
	117	*/
	118	#define CONFIG_ARP_TIMEOUT 200UL
	119
	120	#endif /* CONFIG_QONG_FPGA */
	121
	122	#define CONFIG_CONS_INDEX 1
	123	#define CONFIG_BAUDRATE 115200
0d19f6c8 IY	124
	125	/***********************************************************
	126	* Command definition
	127	***********************************************************/
	128
	129	#include <config_cmd_default.h>
	130
7e4a9e6d	131	#define CONFIG_CMD_CACHE
b952c24a	132	#define CONFIG_CMD_DATE
0d19f6c8	133	#define CONFIG_CMD_DHCP
0d19f6c8	134	#define CONFIG_CMD_MII
45997e0a	135	#define CONFIG_CMD_NAND
b952c24a WD	136	#define CONFIG_CMD_NET
	137	#define CONFIG_CMD_PING
	138	#define CONFIG_CMD_SETEXPR
e98ecd71	139	#define CONFIG_CMD_SPI
544aa66a	140	#define CONFIG_CMD_UNZIP
0d19f6c8	141
9660e442	142	#define CONFIG_BOARD_LATE_INIT
0d19f6c8 IY	143
	144	#define CONFIG_BOOTDELAY 5
	145
	146	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	147
0d19f6c8 IY	148	#define CONFIG_EXTRA_ENV_SETTINGS \
	149	"netdev=eth0\0" \
	150	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	151	"nfsroot=${serverip}:${rootpath}\0" \
	152	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	153	"addip=setenv bootargs ${bootargs} " \
	154	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	155	":${hostname}:${netdev}:off panic=1\0" \
	156	"addtty=setenv bootargs ${bootargs}" \
	157	" console=ttymxc0,${baudrate}\0" \
b4e85d0f	158	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
0d19f6c8	159	"addmisc=setenv bootargs ${bootargs}\0" \
8a1cdaa9	160	"uboot_addr=A0000000\0" \
b952c24a	161	"kernel_addr=A00C0000\0" \
8a1cdaa9	162	"ramdisk_addr=A0300000\0" \
b4e85d0f	163	"u-boot=qong/u-boot.bin\0" \
0d19f6c8 IY	164	"kernel_addr_r=80800000\0" \
	165	"hostname=qong\0" \
	166	"bootfile=qong/uImage\0" \
	167	"rootpath=/opt/eldk-4.2-arm/armVFP\0" \
b4e85d0f	168	"flash_self=run ramargs addip addtty addmtd addmisc;" \
0d19f6c8	169	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
b4e85d0f	170	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8 IY	171	"bootm ${kernel_addr}\0" \
0d19f6c8 IY	172	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
b4e85d0f	173	"run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8	174	"bootm\0" \
b4e85d0f IY	175	"bootcmd=run flash_self\0" \
b4e85d0f IY	176	"load=tftp ${loadaddr} ${u-boot}\0" \
93ea89f0 MV	177	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
93ea89f0 MV	178	" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
0d19f6c8	179	" +${filesize};cp.b ${fileaddr} " \
93ea89f0	180	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
0d19f6c8	181	"upd=run load update\0" \
62a22dca HR	182	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
	183	"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
	184	"vmode:0\0" \
0d19f6c8 IY	185
	186	/*
	187	* Miscellaneous configurable options
	188	*/
	189	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	190	#define CONFIG_SYS_PROMPT "=> "
b4e85d0f	191	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
0d19f6c8 IY	192	/* Print Buffer Size */
	193	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	194	sizeof(CONFIG_SYS_PROMPT) + 16)
	195	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	196	/* Boot Argument Buffer Size */
	197	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	198
	199	/* memtest works on first 255MB of RAM */
	200	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	201	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
	202
	203	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	204
	205	#define CONFIG_SYS_HZ 1000
	206
8a508e30 FE	207	#define CONFIG_CMDLINE_EDITING
8a508e30 FE	208	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
0d19f6c8	209
8a508e30	210	#define CONFIG_MISC_INIT_R
0d19f6c8 IY	211
	212	/*-----------------------------------------------------------------------
	213	* Physical Memory Map
	214	*/
	215	#define CONFIG_NR_DRAM_BANKS 1
	216	#define PHYS_SDRAM_1 CSD0_BASE
	217	#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
	218
45997e0a SB	219	/*
	220	* NAND driver
	221	*/
	222
	223	#ifndef __ASSEMBLY__
	224	extern void qong_nand_plat_init(void *chip);
	225	extern int qong_nand_rdy(void *chip);
	226	#endif
	227	#define CONFIG_NAND_PLAT
	228	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	229	#define CONFIG_SYS_NAND_BASE CS3_BASE
	230	#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
	231
	232	#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 24))
	233	#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 23))
	234	#define QONG_NAND_WRITE(addr, cmd) \
	235	do { \
	236	__REG8(addr) = cmd; \
	237	} while (0)
	238
	239	#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
	240	#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
	241	#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
	242
0d19f6c8 IY	243	/*-----------------------------------------------------------------------
	244	* FLASH and environment organization
	245	*/
	246	#define CONFIG_SYS_FLASH_BASE CS0_BASE
	247	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	248	/* max number of sectors on one chip */
	249	#define CONFIG_SYS_MAX_FLASH_SECT 1024
	250	/* Monitor at beginning of flash */
	251	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	252	#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
	253
8a508e30	254	#define CONFIG_ENV_IS_IN_FLASH
0d19f6c8 IY	255	#define CONFIG_ENV_SECT_SIZE 0x20000
0d19f6c8 IY	256	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
d7dc464b	257	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
0d19f6c8 IY	258
	259	/* Address and size of Redundant Environment Sector */
	260	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	261	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	262
	263	/*-----------------------------------------------------------------------
	264	* CFI FLASH driver setup
	265	*/
	266	/* Flash memory is CFI compliant */
8a508e30	267	#define CONFIG_SYS_FLASH_CFI
0d19f6c8	268	/* Use drivers/cfi_flash.c */
8a508e30	269	#define CONFIG_FLASH_CFI_DRIVER
0d19f6c8	270	/* Use buffered writes (~10x faster) */
8a508e30	271	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
0d19f6c8	272	/* Use hardware sector protection */
8a508e30	273	#define CONFIG_SYS_FLASH_PROTECTION
0d19f6c8 IY	274
0d19f6c8 IY	275	/*
c9d944d3	276	* Filesystem
0d19f6c8	277	*/
c9d944d3 SB	278	#define CONFIG_CMD_JFFS2
	279	#define CONFIG_CMD_UBI
	280	#define CONFIG_CMD_UBIFS
	281	#define CONFIG_RBTREE
	282	#define CONFIG_MTD_PARTITIONS
68d7d651	283	#define CONFIG_CMD_MTDPARTS
c9d944d3	284	#define CONFIG_LZO
942556a9 SR	285	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	286	#define CONFIG_FLASH_CFI_MTD
b952c24a WD	287	#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
b952c24a WD	288	"nand0=gen_nand"
b4e85d0f	289	#define MTDPARTS_DEFAULT \
b952c24a WD	290	"mtdparts=physmap-flash.0:" \
	291	"512k(U-Boot),128k(env1),128k(env2)," \
	292	"2304k(kernel),13m(ramdisk),-(user);" \
	293	"gen_nand:" \
	294	"128m(nand)"
0d19f6c8	295
a784c01a	296	/* additions for new relocation code, must be added to all boards */
e48b7c0a HS	297	#define CONFIG_SYS_SDRAM_BASE 0x80000000
e48b7c0a HS	298	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
553f0982	299	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
25ddd1fb	300	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
e48b7c0a HS	301	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
e48b7c0a HS	302
8a508e30	303	#define CONFIG_BOARD_EARLY_INIT_F
e48b7c0a	304
0d19f6c8	305	#endif /* __CONFIG_H */