[people/ms/u-boot.git] / include / configs / qong.h

/*
 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
 *
 * Configuration settings for the Dave/DENX QongEVB-LITE board.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

/* High Level Configuration Options */
#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
#define CONFIG_MX31			/* in a mx31 */
#define CONFIG_QONG
#define CONFIG_MX31_HCLK_FREQ	26000000	/* 26MHz */
#define CONFIG_MX31_CLK32	32768

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_TEXT_BASE 0xa0000000

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1536 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

#define CONFIG_MXC_GPIO
#define CONFIG_HW_WATCHDOG

#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13XXX

#define CONFIG_PMIC
#define CONFIG_PMIC_SPI
#define CONFIG_PMIC_FSL
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	0
#define CONFIG_FSL_PMIC_CLK	100000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN	32

/* FPGA */
#define CONFIG_FPGA
#define CONFIG_QONG_FPGA
#define CONFIG_FPGA_BASE	(CS1_BASE)
#define CONFIG_FPGA_LATTICE
#define CONFIG_FPGA_COUNT	1

#ifdef CONFIG_QONG_FPGA
/* Ethernet */
#define CONFIG_DNET
#define CONFIG_DNET_BASE	(CS1_BASE + QONG_FPGA_PERIPH_SIZE)

/* Framebuffer and LCD */
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MX3
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)

/* USB */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT	2
#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* CONFIG_CMD_USB */

/*
 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
 * initial TFTP transfer, should the user wish one, significantly.
 */
#define CONFIG_ARP_TIMEOUT	200UL

#endif /* CONFIG_QONG_FPGA */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI
#define CONFIG_CMD_UNZIP

#define CONFIG_BOARD_LATE_INIT

#define CONFIG_BOOTDELAY	5

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

#define xstr(s)	str(s)
#define str(s)	#s

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"uboot_addr=A0000000\0"						\
	"kernel_addr=A00C0000\0"					\
	"ramdisk_addr=A0300000\0"					\
	"u-boot=qong/u-boot.bin\0"					\
	"kernel_addr_r=80800000\0"					\
	"hostname=qong\0"						\
	"bootfile=qong/uImage\0"					\
	"rootpath=/opt/eldk-4.2-arm/armVFP\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm\0"						\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};cp.b ${fileaddr} "			\
		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
	"upd=run load update\0"						\
	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,"	\
		"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,"	\
		"vmode:0\0"						\

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
		sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* memtest works on first 255MB of RAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0xff000000)

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_SYS_HZ			1000

#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */

#define CONFIG_MISC_INIT_R
/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	0x10000000	/* 256 MB */

/*
 * NAND driver
 */

#ifndef __ASSEMBLY__
extern void qong_nand_plat_init(void *chip);
extern int qong_nand_rdy(void *chip);
#endif
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_MAX_NAND_DEVICE     1
#define CONFIG_SYS_NAND_BASE	CS3_BASE
#define NAND_PLAT_INIT() qong_nand_plat_init(nand)

#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
#define QONG_NAND_WRITE(addr, cmd) \
	do { \
		__REG8(addr) = cmd; \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip)      (qong_nand_rdy(chip))

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	1024
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */

#define	CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x80000)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* Flash memory is CFI compliant */
#define CONFIG_SYS_FLASH_CFI
/* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_CFI_DRIVER
/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* Use hardware sector protection */
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * Filesystem
 */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,"		\
				"nand0=gen_nand"
#define MTDPARTS_DEFAULT	\
	"mtdparts=physmap-flash.0:"				\
			"512k(U-Boot),128k(env1),128k(env2),"	\
			"2304k(kernel),13m(ramdisk),-(user);"	\
		"gen_nand:"					\
			"128m(nand)"

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)

#define CONFIG_BOARD_EARLY_INIT_F

#endif /* __CONFIG_H */
Commit	Line	Data
0d19f6c8 IY	1	/*
	2	* Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
	3	*
	4	* Configuration settings for the Dave/DENX QongEVB-LITE board.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#ifndef __CONFIG_H
	23	#define __CONFIG_H
	24
86271115	25	#include <asm/arch/imx-regs.h>
0d19f6c8	26
22a9ea97	27	/* High Level Configuration Options */
8a508e30 FE	28	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
	29	#define CONFIG_MX31 /* in a mx31 */
	30	#define CONFIG_QONG
0d19f6c8 IY	31	#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
	32	#define CONFIG_MX31_CLK32 32768
	33
	34	#define CONFIG_DISPLAY_CPUINFO
	35	#define CONFIG_DISPLAY_BOARDINFO
	36
22a9ea97 SB	37	#define CONFIG_SYS_TEXT_BASE 0xa0000000
22a9ea97 SB	38
8a508e30 FE	39	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	40	#define CONFIG_SETUP_MEMORY_TAGS
	41	#define CONFIG_INITRD_TAG
0d19f6c8 IY	42
	43	/*
	44	* Size of malloc() pool
	45	*/
544aa66a	46	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
0d19f6c8 IY	47
	48	/*
	49	* Hardware drivers
	50	*/
	51
40f6fffe SB	52	#define CONFIG_MXC_UART
40f6fffe SB	53	#define CONFIG_MXC_UART_BASE UART1_BASE
0d19f6c8	54
c4ea1424	55	#define CONFIG_MXC_GPIO
8640c984	56	#define CONFIG_HW_WATCHDOG
45997e0a	57
e98ecd71 SB	58	#define CONFIG_MXC_SPI
e98ecd71 SB	59	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	60	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
4e8b7544	61	#define CONFIG_RTC_MC13XXX
e98ecd71	62
f33bd087 SB	63	#define CONFIG_PMIC
	64	#define CONFIG_PMIC_SPI
	65	#define CONFIG_PMIC_FSL
e98ecd71 SB	66	#define CONFIG_FSL_PMIC_BUS 1
	67	#define CONFIG_FSL_PMIC_CS 0
	68	#define CONFIG_FSL_PMIC_CLK 100000
9f481e95	69	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
f33bd087	70	#define CONFIG_FSL_PMIC_BITLEN 32
e98ecd71	71
0d19f6c8	72	/* FPGA */
b9eb3fdf	73	#define CONFIG_FPGA
8a508e30	74	#define CONFIG_QONG_FPGA
0d19f6c8	75	#define CONFIG_FPGA_BASE (CS1_BASE)
b9eb3fdf SB	76	#define CONFIG_FPGA_LATTICE
b9eb3fdf SB	77	#define CONFIG_FPGA_COUNT 1
0d19f6c8 IY	78
	79	#ifdef CONFIG_QONG_FPGA
	80	/* Ethernet */
8a508e30	81	#define CONFIG_DNET
0d19f6c8	82	#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
0d19f6c8	83
7c8cf0d0	84	/* Framebuffer and LCD */
62a22dca HR	85	#define CONFIG_VIDEO
62a22dca HR	86	#define CONFIG_CFB_CONSOLE
7c8cf0d0	87	#define CONFIG_VIDEO_MX3
62a22dca HR	88	#define CONFIG_VIDEO_LOGO
	89	#define CONFIG_VIDEO_SW_CURSOR
	90	#define CONFIG_VGA_AS_SINGLE_DEVICE
7c8cf0d0	91	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
62a22dca	92	#define CONFIG_SPLASH_SCREEN
7c8cf0d0 SB	93	#define CONFIG_CMD_BMP
7c8cf0d0 SB	94	#define CONFIG_BMP_16BPP
544aa66a WD	95	#define CONFIG_VIDEO_BMP_GZIP
544aa66a WD	96	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
7c8cf0d0	97
d7dc464b SB	98	/* USB */
	99	#define CONFIG_CMD_USB
	100	#ifdef CONFIG_CMD_USB
	101	#define CONFIG_USB_EHCI /* Enable EHCI USB support */
	102	#define CONFIG_USB_EHCI_MXC
	103	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	104	#define CONFIG_MXC_USB_PORT 2
	105	#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI \| MXC_EHCI_UTMI_8BIT)
	106	#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
	107	#define CONFIG_EHCI_IS_TDI
	108	#define CONFIG_USB_STORAGE
	109	#define CONFIG_DOS_PARTITION
	110	#define CONFIG_SUPPORT_VFAT
b952c24a	111	#define CONFIG_CMD_EXT2
d7dc464b SB	112	#define CONFIG_CMD_FAT
	113	#endif /* CONFIG_CMD_USB */
	114
0d19f6c8 IY	115	/*
	116	* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
	117	* initial TFTP transfer, should the user wish one, significantly.
	118	*/
	119	#define CONFIG_ARP_TIMEOUT 200UL
	120
	121	#endif /* CONFIG_QONG_FPGA */
	122
	123	#define CONFIG_CONS_INDEX 1
	124	#define CONFIG_BAUDRATE 115200
0d19f6c8 IY	125
	126	/***********************************************************
	127	* Command definition
	128	***********************************************************/
	129
	130	#include <config_cmd_default.h>
	131
7e4a9e6d	132	#define CONFIG_CMD_CACHE
b952c24a	133	#define CONFIG_CMD_DATE
0d19f6c8	134	#define CONFIG_CMD_DHCP
0d19f6c8	135	#define CONFIG_CMD_MII
45997e0a	136	#define CONFIG_CMD_NAND
b952c24a WD	137	#define CONFIG_CMD_NET
	138	#define CONFIG_CMD_PING
	139	#define CONFIG_CMD_SETEXPR
e98ecd71	140	#define CONFIG_CMD_SPI
544aa66a	141	#define CONFIG_CMD_UNZIP
0d19f6c8	142
9660e442	143	#define CONFIG_BOARD_LATE_INIT
0d19f6c8 IY	144
	145	#define CONFIG_BOOTDELAY 5
	146
	147	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	148
	149	#define xstr(s) str(s)
	150	#define str(s) #s
	151
	152	#define CONFIG_EXTRA_ENV_SETTINGS \
	153	"netdev=eth0\0" \
	154	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	155	"nfsroot=${serverip}:${rootpath}\0" \
	156	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	157	"addip=setenv bootargs ${bootargs} " \
	158	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	159	":${hostname}:${netdev}:off panic=1\0" \
	160	"addtty=setenv bootargs ${bootargs}" \
	161	" console=ttymxc0,${baudrate}\0" \
b4e85d0f	162	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
0d19f6c8	163	"addmisc=setenv bootargs ${bootargs}\0" \
8a1cdaa9	164	"uboot_addr=A0000000\0" \
b952c24a	165	"kernel_addr=A00C0000\0" \
8a1cdaa9	166	"ramdisk_addr=A0300000\0" \
b4e85d0f	167	"u-boot=qong/u-boot.bin\0" \
0d19f6c8 IY	168	"kernel_addr_r=80800000\0" \
	169	"hostname=qong\0" \
	170	"bootfile=qong/uImage\0" \
	171	"rootpath=/opt/eldk-4.2-arm/armVFP\0" \
b4e85d0f	172	"flash_self=run ramargs addip addtty addmtd addmisc;" \
0d19f6c8	173	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
b4e85d0f	174	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8 IY	175	"bootm ${kernel_addr}\0" \
0d19f6c8 IY	176	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
b4e85d0f	177	"run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8	178	"bootm\0" \
b4e85d0f IY	179	"bootcmd=run flash_self\0" \
b4e85d0f IY	180	"load=tftp ${loadaddr} ${u-boot}\0" \
0d19f6c8 IY	181	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
	182	" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
	183	" +${filesize};cp.b ${fileaddr} " \
b4e85d0f	184	xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
0d19f6c8	185	"upd=run load update\0" \
62a22dca HR	186	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
	187	"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
	188	"vmode:0\0" \
0d19f6c8 IY	189
	190	/*
	191	* Miscellaneous configurable options
	192	*/
	193	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	194	#define CONFIG_SYS_PROMPT "=> "
b4e85d0f	195	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
0d19f6c8 IY	196	/* Print Buffer Size */
	197	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	198	sizeof(CONFIG_SYS_PROMPT) + 16)
	199	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	200	/* Boot Argument Buffer Size */
	201	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	202
	203	/* memtest works on first 255MB of RAM */
	204	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	205	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
	206
	207	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	208
	209	#define CONFIG_SYS_HZ 1000
	210
8a508e30 FE	211	#define CONFIG_CMDLINE_EDITING
8a508e30 FE	212	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
0d19f6c8	213
8a508e30	214	#define CONFIG_MISC_INIT_R
0d19f6c8 IY	215	/*-----------------------------------------------------------------------
	216	* Stack sizes
	217	*
	218	* The stack sizes are set up in start.S using the settings below
	219	*/
	220	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	221
	222	/*-----------------------------------------------------------------------
	223	* Physical Memory Map
	224	*/
	225	#define CONFIG_NR_DRAM_BANKS 1
	226	#define PHYS_SDRAM_1 CSD0_BASE
	227	#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
	228
45997e0a SB	229	/*
	230	* NAND driver
	231	*/
	232
	233	#ifndef __ASSEMBLY__
	234	extern void qong_nand_plat_init(void *chip);
	235	extern int qong_nand_rdy(void *chip);
	236	#endif
	237	#define CONFIG_NAND_PLAT
	238	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	239	#define CONFIG_SYS_NAND_BASE CS3_BASE
	240	#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
	241
	242	#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 24))
	243	#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 23))
	244	#define QONG_NAND_WRITE(addr, cmd) \
	245	do { \
	246	__REG8(addr) = cmd; \
	247	} while (0)
	248
	249	#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
	250	#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
	251	#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
	252
0d19f6c8 IY	253	/*-----------------------------------------------------------------------
	254	* FLASH and environment organization
	255	*/
	256	#define CONFIG_SYS_FLASH_BASE CS0_BASE
	257	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	258	/* max number of sectors on one chip */
	259	#define CONFIG_SYS_MAX_FLASH_SECT 1024
	260	/* Monitor at beginning of flash */
	261	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	262	#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
	263
8a508e30	264	#define CONFIG_ENV_IS_IN_FLASH
0d19f6c8 IY	265	#define CONFIG_ENV_SECT_SIZE 0x20000
0d19f6c8 IY	266	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
d7dc464b	267	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
0d19f6c8 IY	268
	269	/* Address and size of Redundant Environment Sector */
	270	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	271	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	272
	273	/*-----------------------------------------------------------------------
	274	* CFI FLASH driver setup
	275	*/
	276	/* Flash memory is CFI compliant */
8a508e30	277	#define CONFIG_SYS_FLASH_CFI
0d19f6c8	278	/* Use drivers/cfi_flash.c */
8a508e30	279	#define CONFIG_FLASH_CFI_DRIVER
0d19f6c8	280	/* Use buffered writes (~10x faster) */
8a508e30	281	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
0d19f6c8	282	/* Use hardware sector protection */
8a508e30	283	#define CONFIG_SYS_FLASH_PROTECTION
0d19f6c8 IY	284
0d19f6c8 IY	285	/*
c9d944d3	286	* Filesystem
0d19f6c8	287	*/
c9d944d3 SB	288	#define CONFIG_CMD_JFFS2
	289	#define CONFIG_CMD_UBI
	290	#define CONFIG_CMD_UBIFS
	291	#define CONFIG_RBTREE
	292	#define CONFIG_MTD_PARTITIONS
68d7d651	293	#define CONFIG_CMD_MTDPARTS
c9d944d3	294	#define CONFIG_LZO
942556a9 SR	295	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	296	#define CONFIG_FLASH_CFI_MTD
b952c24a WD	297	#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
b952c24a WD	298	"nand0=gen_nand"
b4e85d0f	299	#define MTDPARTS_DEFAULT \
b952c24a WD	300	"mtdparts=physmap-flash.0:" \
	301	"512k(U-Boot),128k(env1),128k(env2)," \
	302	"2304k(kernel),13m(ramdisk),-(user);" \
	303	"gen_nand:" \
	304	"128m(nand)"
0d19f6c8	305
a784c01a	306	/* additions for new relocation code, must be added to all boards */
e48b7c0a HS	307	#define CONFIG_SYS_SDRAM_BASE 0x80000000
e48b7c0a HS	308	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
553f0982	309	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
25ddd1fb	310	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
e48b7c0a HS	311	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
e48b7c0a HS	312
8a508e30	313	#define CONFIG_BOARD_EARLY_INIT_F
e48b7c0a	314
0d19f6c8	315	#endif /* __CONFIG_H */