[u-boot.git] / include / configs / qong.h

/*
 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
 *
 * Configuration settings for the Dave/DENX QongEVB-LITE board.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/mx31-regs.h>

 /* High Level Configuration Options */
#define CONFIG_ARM1136		1	/* This is an arm1136 CPU core */
#define CONFIG_MX31		1	/* in a mx31 */
#define CONFIG_QONG		1
#define CONFIG_MX31_HCLK_FREQ	26000000	/* 26MHz */
#define CONFIG_MX31_CLK32	32768

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	128

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART	1
#define CONFIG_SYS_MX31_UART1	1

#define CONFIG_MXC_GPIO

#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783

#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	0
#define CONFIG_FSL_PMIC_CLK	100000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

/* FPGA */
#define CONFIG_FPGA
#define CONFIG_QONG_FPGA	1
#define CONFIG_FPGA_BASE	(CS1_BASE)
#define CONFIG_FPGA_LATTICE
#define CONFIG_FPGA_COUNT	1

#ifdef CONFIG_QONG_FPGA
/* Ethernet */
#define CONFIG_DNET		1
#define CONFIG_DNET_BASE	(CS1_BASE + QONG_FPGA_PERIPH_SIZE)
#define CONFIG_NET_MULTI	1

/* Framebuffer and LCD */
#define CONFIG_LCD
#define CONFIG_VIDEO_MX3
#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define LCD_BPP		LCD_COLOR16
#define	CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_DISPLAY_COM57H5M10XRC

/* USB */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT	2
#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* CONFIG_CMD_USB */

/*
 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
 * initial TFTP transfer, should the user wish one, significantly.
 */
#define CONFIG_ARP_TIMEOUT	200UL

#endif /* CONFIG_QONG_FPGA */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI

#define BOARD_LATE_INIT

#define CONFIG_BOOTDELAY	5

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

#define xstr(s)	str(s)
#define str(s)	#s

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"uboot_addr=A0000000\0"						\
	"kernel_addr=A00C0000\0"					\
	"ramdisk_addr=A0300000\0"					\
	"u-boot=qong/u-boot.bin\0"					\
	"kernel_addr_r=80800000\0"					\
	"hostname=qong\0"						\
	"bootfile=qong/uImage\0"					\
	"rootpath=/opt/eldk-4.2-arm/armVFP\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm\0"						\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};cp.b ${fileaddr} "			\
		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
	"upd=run load update\0"						\

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
		sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* memtest works on first 255MB of RAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0xff000000)

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_SYS_HZ			1000

#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif

#define CONFIG_MISC_INIT_R	1
/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	0x10000000	/* 256 MB */

/*
 * NAND driver
 */

#ifndef __ASSEMBLY__
extern void qong_nand_plat_init(void *chip);
extern int qong_nand_rdy(void *chip);
#endif
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_MAX_NAND_DEVICE     1
#define CONFIG_SYS_NAND_BASE	CS3_BASE
#define NAND_PLAT_INIT() qong_nand_plat_init(nand)

#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
#define QONG_NAND_WRITE(addr, cmd) \
	do { \
		__REG8(addr) = cmd; \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip)      (qong_nand_rdy(chip))

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	1024
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x80000)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* Flash memory is CFI compliant */
#define CONFIG_SYS_FLASH_CFI			1
/* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_CFI_DRIVER			1
/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
/* Use hardware sector protection */
#define CONFIG_SYS_FLASH_PROTECTION		1

/*
 * Filesystem
 */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,"		\
				"nand0=gen_nand"
#define MTDPARTS_DEFAULT	\
	"mtdparts=physmap-flash.0:"				\
			"512k(U-Boot),128k(env1),128k(env2),"	\
			"2304k(kernel),13m(ramdisk),-(user);"	\
		"gen_nand:"					\
			"128m(nand)"

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)

#define CONFIG_BOARD_EARLY_INIT_F	1

#endif /* __CONFIG_H */
Commit	Line	Data
0d19f6c8 IY	1	/*
	2	* Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
	3	*
	4	* Configuration settings for the Dave/DENX QongEVB-LITE board.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#ifndef __CONFIG_H
	23	#define __CONFIG_H
	24
	25	#include <asm/arch/mx31-regs.h>
	26
	27	/* High Level Configuration Options */
	28	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	29	#define CONFIG_MX31 1 /* in a mx31 */
	30	#define CONFIG_QONG 1
	31	#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
	32	#define CONFIG_MX31_CLK32 32768
	33
	34	#define CONFIG_DISPLAY_CPUINFO
	35	#define CONFIG_DISPLAY_BOARDINFO
	36
	37	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	38	#define CONFIG_SETUP_MEMORY_TAGS 1
	39	#define CONFIG_INITRD_TAG 1
	40
	41	/*
	42	* Size of malloc() pool
	43	*/
c9d944d3	44	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
0d19f6c8 IY	45	/* size in bytes reserved for initial data */
	46	#define CONFIG_SYS_GBL_DATA_SIZE 128
	47
	48	/*
	49	* Hardware drivers
	50	*/
	51
47d19da4	52	#define CONFIG_MXC_UART 1
0d19f6c8 IY	53	#define CONFIG_SYS_MX31_UART1 1
0d19f6c8 IY	54
c4ea1424	55	#define CONFIG_MXC_GPIO
45997e0a	56
e98ecd71 SB	57	#define CONFIG_MXC_SPI
e98ecd71 SB	58	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	59	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
e98ecd71 SB	60	#define CONFIG_RTC_MC13783
	61
	62	#define CONFIG_FSL_PMIC
	63	#define CONFIG_FSL_PMIC_BUS 1
	64	#define CONFIG_FSL_PMIC_CS 0
	65	#define CONFIG_FSL_PMIC_CLK 100000
9f481e95	66	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
e98ecd71	67
0d19f6c8	68	/* FPGA */
b9eb3fdf	69	#define CONFIG_FPGA
0d19f6c8 IY	70	#define CONFIG_QONG_FPGA 1
0d19f6c8 IY	71	#define CONFIG_FPGA_BASE (CS1_BASE)
b9eb3fdf SB	72	#define CONFIG_FPGA_LATTICE
b9eb3fdf SB	73	#define CONFIG_FPGA_COUNT 1
0d19f6c8 IY	74
	75	#ifdef CONFIG_QONG_FPGA
	76	/* Ethernet */
	77	#define CONFIG_DNET 1
	78	#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
	79	#define CONFIG_NET_MULTI 1
	80
7c8cf0d0 SB	81	/* Framebuffer and LCD */
	82	#define CONFIG_LCD
	83	#define CONFIG_VIDEO_MX3
	84	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
	85	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	86	#define LCD_BPP LCD_COLOR16
	87	#define CONFIG_SPLASH_SCREEN
	88	#define CONFIG_CMD_BMP
	89	#define CONFIG_BMP_16BPP
03af5abd	90	#define CONFIG_DISPLAY_COM57H5M10XRC
7c8cf0d0	91
d7dc464b SB	92	/* USB */
	93	#define CONFIG_CMD_USB
	94	#ifdef CONFIG_CMD_USB
	95	#define CONFIG_USB_EHCI /* Enable EHCI USB support */
	96	#define CONFIG_USB_EHCI_MXC
	97	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	98	#define CONFIG_MXC_USB_PORT 2
	99	#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI \| MXC_EHCI_UTMI_8BIT)
	100	#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
	101	#define CONFIG_EHCI_IS_TDI
	102	#define CONFIG_USB_STORAGE
	103	#define CONFIG_DOS_PARTITION
	104	#define CONFIG_SUPPORT_VFAT
b952c24a	105	#define CONFIG_CMD_EXT2
d7dc464b SB	106	#define CONFIG_CMD_FAT
	107	#endif /* CONFIG_CMD_USB */
	108
0d19f6c8 IY	109	/*
	110	* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
	111	* initial TFTP transfer, should the user wish one, significantly.
	112	*/
	113	#define CONFIG_ARP_TIMEOUT 200UL
	114
	115	#endif /* CONFIG_QONG_FPGA */
	116
	117	#define CONFIG_CONS_INDEX 1
	118	#define CONFIG_BAUDRATE 115200
	119	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
	120
	121	/***********************************************************
	122	* Command definition
	123	***********************************************************/
	124
	125	#include <config_cmd_default.h>
	126
7e4a9e6d	127	#define CONFIG_CMD_CACHE
b952c24a	128	#define CONFIG_CMD_DATE
0d19f6c8	129	#define CONFIG_CMD_DHCP
0d19f6c8	130	#define CONFIG_CMD_MII
45997e0a	131	#define CONFIG_CMD_NAND
b952c24a WD	132	#define CONFIG_CMD_NET
	133	#define CONFIG_CMD_PING
	134	#define CONFIG_CMD_SETEXPR
e98ecd71	135	#define CONFIG_CMD_SPI
0d19f6c8	136
b952c24a	137	#define BOARD_LATE_INIT
0d19f6c8 IY	138
	139	#define CONFIG_BOOTDELAY 5
	140
	141	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	142
	143	#define xstr(s) str(s)
	144	#define str(s) #s
	145
	146	#define CONFIG_EXTRA_ENV_SETTINGS \
	147	"netdev=eth0\0" \
	148	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	149	"nfsroot=${serverip}:${rootpath}\0" \
	150	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	151	"addip=setenv bootargs ${bootargs} " \
	152	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	153	":${hostname}:${netdev}:off panic=1\0" \
	154	"addtty=setenv bootargs ${bootargs}" \
	155	" console=ttymxc0,${baudrate}\0" \
b4e85d0f	156	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
0d19f6c8	157	"addmisc=setenv bootargs ${bootargs}\0" \
8a1cdaa9	158	"uboot_addr=A0000000\0" \
b952c24a	159	"kernel_addr=A00C0000\0" \
8a1cdaa9	160	"ramdisk_addr=A0300000\0" \
b4e85d0f	161	"u-boot=qong/u-boot.bin\0" \
0d19f6c8 IY	162	"kernel_addr_r=80800000\0" \
	163	"hostname=qong\0" \
	164	"bootfile=qong/uImage\0" \
	165	"rootpath=/opt/eldk-4.2-arm/armVFP\0" \
b4e85d0f	166	"flash_self=run ramargs addip addtty addmtd addmisc;" \
0d19f6c8	167	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
b4e85d0f	168	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8 IY	169	"bootm ${kernel_addr}\0" \
0d19f6c8 IY	170	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
b4e85d0f	171	"run nfsargs addip addtty addmtd addmisc;" \
0d19f6c8	172	"bootm\0" \
b4e85d0f IY	173	"bootcmd=run flash_self\0" \
b4e85d0f IY	174	"load=tftp ${loadaddr} ${u-boot}\0" \
0d19f6c8 IY	175	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
	176	" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
	177	" +${filesize};cp.b ${fileaddr} " \
b4e85d0f	178	xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
0d19f6c8 IY	179	"upd=run load update\0" \
	180
	181	/*
	182	* Miscellaneous configurable options
	183	*/
	184	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	185	#define CONFIG_SYS_PROMPT "=> "
b4e85d0f	186	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
0d19f6c8 IY	187	/* Print Buffer Size */
	188	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	189	sizeof(CONFIG_SYS_PROMPT) + 16)
	190	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	191	/* Boot Argument Buffer Size */
	192	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	193
	194	/* memtest works on first 255MB of RAM */
	195	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	196	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
	197
	198	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	199
	200	#define CONFIG_SYS_HZ 1000
	201
	202	#define CONFIG_CMDLINE_EDITING 1
8a1cdaa9 WD	203	#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
	204	#ifdef CONFIG_SYS_HUSH_PARSER
	205	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	206	#endif
0d19f6c8 IY	207
	208	#define CONFIG_MISC_INIT_R 1
	209	/*-----------------------------------------------------------------------
	210	* Stack sizes
	211	*
	212	* The stack sizes are set up in start.S using the settings below
	213	*/
	214	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	215
	216	/*-----------------------------------------------------------------------
	217	* Physical Memory Map
	218	*/
	219	#define CONFIG_NR_DRAM_BANKS 1
	220	#define PHYS_SDRAM_1 CSD0_BASE
	221	#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
	222
45997e0a SB	223	/*
	224	* NAND driver
	225	*/
	226
	227	#ifndef __ASSEMBLY__
	228	extern void qong_nand_plat_init(void *chip);
	229	extern int qong_nand_rdy(void *chip);
	230	#endif
	231	#define CONFIG_NAND_PLAT
	232	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	233	#define CONFIG_SYS_NAND_BASE CS3_BASE
	234	#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
	235
	236	#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 24))
	237	#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 23))
	238	#define QONG_NAND_WRITE(addr, cmd) \
	239	do { \
	240	__REG8(addr) = cmd; \
	241	} while (0)
	242
	243	#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
	244	#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
	245	#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
	246
0d19f6c8 IY	247	/*-----------------------------------------------------------------------
	248	* FLASH and environment organization
	249	*/
	250	#define CONFIG_SYS_FLASH_BASE CS0_BASE
	251	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	252	/* max number of sectors on one chip */
	253	#define CONFIG_SYS_MAX_FLASH_SECT 1024
	254	/* Monitor at beginning of flash */
	255	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	256	#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
	257
	258	#define CONFIG_ENV_IS_IN_FLASH 1
	259	#define CONFIG_ENV_SECT_SIZE 0x20000
	260	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
d7dc464b	261	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
0d19f6c8 IY	262
	263	/* Address and size of Redundant Environment Sector */
	264	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	265	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	266
	267	/*-----------------------------------------------------------------------
	268	* CFI FLASH driver setup
	269	*/
	270	/* Flash memory is CFI compliant */
	271	#define CONFIG_SYS_FLASH_CFI 1
	272	/* Use drivers/cfi_flash.c */
	273	#define CONFIG_FLASH_CFI_DRIVER 1
	274	/* Use buffered writes (~10x faster) */
	275	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	276	/* Use hardware sector protection */
	277	#define CONFIG_SYS_FLASH_PROTECTION 1
	278
	279	/*
c9d944d3	280	* Filesystem
0d19f6c8	281	*/
c9d944d3 SB	282	#define CONFIG_CMD_JFFS2
	283	#define CONFIG_CMD_UBI
	284	#define CONFIG_CMD_UBIFS
	285	#define CONFIG_RBTREE
	286	#define CONFIG_MTD_PARTITIONS
68d7d651	287	#define CONFIG_CMD_MTDPARTS
c9d944d3	288	#define CONFIG_LZO
942556a9 SR	289	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	290	#define CONFIG_FLASH_CFI_MTD
b952c24a WD	291	#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
b952c24a WD	292	"nand0=gen_nand"
b4e85d0f	293	#define MTDPARTS_DEFAULT \
b952c24a WD	294	"mtdparts=physmap-flash.0:" \
	295	"512k(U-Boot),128k(env1),128k(env2)," \
	296	"2304k(kernel),13m(ramdisk),-(user);" \
	297	"gen_nand:" \
	298	"128m(nand)"
0d19f6c8	299
a784c01a	300	/* additions for new relocation code, must be added to all boards */
e48b7c0a HS	301	#define CONFIG_SYS_SDRAM_BASE 0x80000000
e48b7c0a HS	302	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
553f0982 WD	303	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
553f0982 WD	304	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
e48b7c0a HS	305	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
	306
	307	#define CONFIG_BOARD_EARLY_INIT_F 1
	308
0d19f6c8	309	#endif /* __CONFIG_H */