[people/ms/u-boot.git] / include / configs / quad100hd.h

/*
 * (C) Copyright 2008
 * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************
 * quad100hd.h - configuration for Quad100hd board
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_QUAD100HD	1		/* Board is Quad100hd	*/
#define CONFIG_405EP		1		/* Specifc 405EP support*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */

#define PLLMR0_DEFAULT		PLLMR0_266_133_66 /* no PCI */
#define PLLMR1_DEFAULT		PLLMR1_266_133_66 /* no PCI */

/* the environment is in the EEPROM by default */
#define CONFIG_ENV_IS_IN_EEPROM
#undef CONFIG_ENV_IS_IN_FLASH

#define CONFIG_PPC4xx_EMAC
#define CONFIG_HAS_ETH1		1
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
#define CONFIG_PHY_RESET	1
#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_ASKENV
#undef CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*-----------------------------------------------------------------------
 * SDRAM
 *----------------------------------------------------------------------*/
/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0  1

/* FIX! SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL            3       /* CAS latency */
#define CONFIG_SYS_SDRAM_tRP           20      /* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
#define CONFIG_SYS_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC          66      /* Auto refresh period */

/*
 * JFFS2
 */
#define CONFIG_SYS_JFFS2_FIRST_BANK    0
#ifdef  CONFIG_SYS_KERNEL_IN_JFFS2
#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
#else /* kernel not in JFFS */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
#endif
#define CONFIG_SYS_JFFS2_NUM_BANKS     1

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
#define CONFIG_SYS_BASE_BAUD		691200
#define CONFIG_BAUDRATE		115200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2		/* bytes of address */

#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 8 byte write page size */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
#define CONFIG_SYS_EEPROM_SIZE			0x2000

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFC00000
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define	CONFIG_FLASH_CFI_DRIVER

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
#define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank         */

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
/* the environment is located before u-boot */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#endif

#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE		0x400		/* Size of Environment vars */
#define CONFIG_ENV_OFFSET		0x00000000
#define CONFIG_SYS_ENABLE_CRC_16	1       /* Intrinsyc formatting used crc16 */
#endif

/* partly from PPCBoot */
/* NAND */
#define CONFIG_NAND
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_BASE   0x60000000
#define CONFIG_SYS_NAND_CS	10   /* our CS is GPIO10 */
#define CONFIG_SYS_NAND_RDY	23   /* our RDY is GPIO23 */
#define CONFIG_SYS_NAND_CE	24   /* our CE is GPIO24  */
#define CONFIG_SYS_NAND_CLE	31   /* our CLE is GPIO31 */
#define CONFIG_SYS_NAND_ALE	30   /* our ALE is GPIO30 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#endif

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
/* see ./arch/powerpc/cpu/ppc4xx/start.S */
#define CONFIG_SYS_TEMP_STACK_OCM	1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 * Taken from PPCBoot board/icecube/icecube.h
 */

/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
#define CONFIG_SYS_EBC_PB0AP		0x04002480
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000
#define CONFIG_SYS_EBC_PB1AP           0x04005480
#define CONFIG_SYS_EBC_PB1CR           0x60018000
#define CONFIG_SYS_EBC_PB2AP           0x00000000
#define CONFIG_SYS_EBC_PB2CR           0x00000000
#define CONFIG_SYS_EBC_PB3AP           0x00000000
#define CONFIG_SYS_EBC_PB3CR           0x00000000
#define CONFIG_SYS_EBC_PB4AP           0x00000000
#define CONFIG_SYS_EBC_PB4CR           0x00000000

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * Taken in part from PPCBoot board/icecube/icecube.h
 */
/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CONFIG_SYS_GPIO0_OSRL		0x55555550
#define CONFIG_SYS_GPIO0_OSRH		0x00000110
#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
#define CONFIG_SYS_GPIO0_TSRL		0x00000000
#define CONFIG_SYS_GPIO0_TSRH		0x00000000
#define CONFIG_SYS_GPIO0_TCR		0xFFFF8097
#define CONFIG_SYS_GPIO0_ODR		0x00000000

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#endif

/* ENVIRONMENT VARS */

#define CONFIG_IPADDR		192.168.1.67
#define CONFIG_SERVERIP		192.168.1.50
#define CONFIG_GATEWAYIP	192.168.1.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_LOADADDR		300000
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1

#endif	/* __CONFIG_H */
Commit	Line	Data
73ccb341 GJ	1	/*
	2	* (C) Copyright 2008
	3	* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
73ccb341 GJ	6	*/
	7
	8	/************************************************************************
	9	* quad100hd.h - configuration for Quad100hd board
	10	***********************************************************************/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*-----------------------------------------------------------------------
	15	* High Level Configuration Options
	16	----------------------------------------------------------------------/
	17	#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
73ccb341 GJ	18	#define CONFIG_405EP 1 /* Specifc 405EP support*/
73ccb341 GJ	19
2ae18241 WD	20	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	21
73ccb341 GJ	22	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	23
	24	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	25
	26	#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
	27	#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
	28
0c11935c	29	/* the environment is in the EEPROM by default */
bb1f8b4f	30	#define CONFIG_ENV_IS_IN_EEPROM
5a1aceb0	31	#undef CONFIG_ENV_IS_IN_FLASH
73ccb341	32
96e21f86	33	#define CONFIG_PPC4xx_EMAC
73ccb341 GJ	34	#define CONFIG_HAS_ETH1 1
	35	#define CONFIG_MII 1 /* MII PHY management */
	36	#define CONFIG_PHY_ADDR 0x01 /* PHY address */
6d0f6bcf	37	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
73ccb341 GJ	38	#define CONFIG_PHY_RESET 1
	39	#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
	40
	41	/*
	42	* Command line configuration.
	43	*/
	44	#include <config_cmd_default.h>
	45
	46	#undef CONFIG_CMD_ASKENV
	47	#undef CONFIG_CMD_CACHE
	48	#define CONFIG_CMD_DHCP
	49	#undef CONFIG_CMD_DIAG
	50	#define CONFIG_CMD_EEPROM
	51	#undef CONFIG_CMD_ELF
	52	#define CONFIG_CMD_I2C
	53	#undef CONFIG_CMD_IRQ
	54	#define CONFIG_CMD_JFFS2
73ccb341 GJ	55	#undef CONFIG_CMD_MII
	56	#define CONFIG_CMD_NAND
	57	#undef CONFIG_CMD_PING
	58	#define CONFIG_CMD_REGINFO
	59
	60	#undef CONFIG_WATCHDOG /* watchdog disabled */
	61
	62	/*-----------------------------------------------------------------------
	63	* SDRAM
	64	----------------------------------------------------------------------/
	65	/*
	66	* SDRAM configuration (please see cpu/ppc/sdram.[ch])
	67	*/
	68	#define CONFIG_SDRAM_BANK0 1
73ccb341 GJ	69
73ccb341 GJ	70	/* FIX! SDRAM timings used in datasheet */
6d0f6bcf JCPV	71	#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
	72	#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
	73	#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
	74	#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
	75	#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
73ccb341 GJ	76
	77	/*
	78	* JFFS2
	79	*/
6d0f6bcf JCPV	80	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	81	#ifdef CONFIG_SYS_KERNEL_IN_JFFS2
	82	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
73ccb341	83	#else /* kernel not in JFFS */
6d0f6bcf	84	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
73ccb341	85	#endif
6d0f6bcf	86	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
73ccb341 GJ	87
	88	/*-----------------------------------------------------------------------
	89	* Serial Port
	90	----------------------------------------------------------------------/
550650dd SR	91	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	92	#define CONFIG_SYS_NS16550
	93	#define CONFIG_SYS_NS16550_SERIAL
	94	#define CONFIG_SYS_NS16550_REG_SIZE 1
	95	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
6d0f6bcf JCPV	96	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
6d0f6bcf JCPV	97	#define CONFIG_SYS_BASE_BAUD 691200
73ccb341	98	#define CONFIG_BAUDRATE 115200
73ccb341 GJ	99
73ccb341 GJ	100	/* The following table includes the supported baudrates */
6d0f6bcf	101	#define CONFIG_SYS_BAUDRATE_TABLE \
73ccb341 GJ	102	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	103
	104	/*-----------------------------------------------------------------------
	105	* Miscellaneous configurable options
	106	----------------------------------------------------------------------/
6d0f6bcf	107	#define CONFIG_SYS_LONGHELP /* undef to save memory */
73ccb341	108	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	109	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
73ccb341	110	#else
6d0f6bcf	111	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
73ccb341	112	#endif
6d0f6bcf JCPV	113	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	114	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	115	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
73ccb341	116
6d0f6bcf JCPV	117	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	118	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
73ccb341	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	121	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
73ccb341	122
73ccb341	123	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	124	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
73ccb341 GJ	125
	126	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	127	#define CONFIG_LOOPW 1 /* enable loopw command */
	128	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	129	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	130	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	131
	132	/*-----------------------------------------------------------------------
	133	* I2C
	134	----------------------------------------------------------------------/
880540de DE	135	#define CONFIG_SYS_I2C
	136	#define CONFIG_SYS_I2C_PPC4XX
	137	#define CONFIG_SYS_I2C_PPC4XX_CH0
	138	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	139	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
73ccb341	140
6d0f6bcf JCPV	141	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
6d0f6bcf JCPV	142	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
73ccb341	143
6d0f6bcf JCPV	144	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
	145	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	146	#define CONFIG_SYS_EEPROM_SIZE 0x2000
73ccb341 GJ	147
	148	/*-----------------------------------------------------------------------
	149	* Start addresses for the final memory configuration
	150	* (Set up by the startup code)
6d0f6bcf	151	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
73ccb341	152	*/
6d0f6bcf JCPV	153	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	154	#define CONFIG_SYS_FLASH_BASE 0xFFC00000
	155	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	156	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
14d0a02a	157	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
73ccb341 GJ	158
	159	/*
	160	* For booting Linux, the board info and command line data
	161	* have to be in the first 8 MB of memory, since this is
	162	* the maximum mapped by the Linux kernel during initialization.
	163	*/
6d0f6bcf	164	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
73ccb341 GJ	165
	166	/*-----------------------------------------------------------------------
	167	* FLASH organization
	168	*/
6d0f6bcf	169	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	170	#define CONFIG_FLASH_CFI_DRIVER
73ccb341	171
6d0f6bcf	172	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
73ccb341	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	175	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
73ccb341	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
73ccb341	179
6d0f6bcf JCPV	180	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
6d0f6bcf JCPV	181	#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
73ccb341	182
6d0f6bcf JCPV	183	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	184	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
73ccb341	185
5a1aceb0	186	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	187	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
0c11935c	188	/* the environment is located before u-boot */
14d0a02a	189	#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
0c11935c GJ	190
0c11935c GJ	191	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	192	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	193	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
73ccb341 GJ	194	#endif
73ccb341 GJ	195
bb1f8b4f	196	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586 JCPV	197	#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
0e8d1586 JCPV	198	#define CONFIG_ENV_OFFSET 0x00000000
6d0f6bcf	199	#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
73ccb341 GJ	200	#endif
	201
	202	/* partly from PPCBoot */
	203	/* NAND */
	204	#define CONFIG_NAND
	205	#ifdef CONFIG_NAND
6d0f6bcf JCPV	206	#define CONFIG_SYS_NAND_BASE 0x60000000
	207	#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
	208	#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
	209	#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
	210	#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
	211	#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
6d0f6bcf	212	#define CONFIG_SYS_MAX_NAND_DEVICE 1
170c1972	213
73ccb341 GJ	214	#endif
	215
	216	/*-----------------------------------------------------------------------
	217	* Definitions for initial stack pointer and data area (in data cache)
	218	*/
	219	/* use on chip memory (OCM) for temperary stack until sdram is tested */
a47a12be	220	/* see ./arch/powerpc/cpu/ppc4xx/start.S */
6d0f6bcf	221	#define CONFIG_SYS_TEMP_STACK_OCM 1
73ccb341 GJ	222
73ccb341 GJ	223	/* On Chip Memory location */
6d0f6bcf JCPV	224	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	225	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	226	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
553f0982	227	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
73ccb341	228
25ddd1fb	229	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	230	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
73ccb341 GJ	231
	232	/*-----------------------------------------------------------------------
	233	* External Bus Controller (EBC) Setup
	234	* Taken from PPCBoot board/icecube/icecube.h
	235	*/
	236
a47a12be	237	/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
6d0f6bcf	238	#define CONFIG_SYS_EBC_PB0AP 0x04002480
73ccb341	239	/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
6d0f6bcf JCPV	240	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
	241	#define CONFIG_SYS_EBC_PB1AP 0x04005480
	242	#define CONFIG_SYS_EBC_PB1CR 0x60018000
	243	#define CONFIG_SYS_EBC_PB2AP 0x00000000
	244	#define CONFIG_SYS_EBC_PB2CR 0x00000000
	245	#define CONFIG_SYS_EBC_PB3AP 0x00000000
	246	#define CONFIG_SYS_EBC_PB3CR 0x00000000
	247	#define CONFIG_SYS_EBC_PB4AP 0x00000000
	248	#define CONFIG_SYS_EBC_PB4CR 0x00000000
73ccb341 GJ	249
	250	/*-----------------------------------------------------------------------
	251	* Definitions for GPIO setup (PPC405EP specific)
	252	*
	253	* Taken in part from PPCBoot board/icecube/icecube.h
	254	*/
a47a12be	255	/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
afabb498 SR	256	#define CONFIG_SYS_GPIO0_OSRL 0x55555550
	257	#define CONFIG_SYS_GPIO0_OSRH 0x00000110
	258	#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
	259	#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
6d0f6bcf	260	#define CONFIG_SYS_GPIO0_TSRL 0x00000000
afabb498	261	#define CONFIG_SYS_GPIO0_TSRH 0x00000000
6d0f6bcf JCPV	262	#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
6d0f6bcf JCPV	263	#define CONFIG_SYS_GPIO0_ODR 0x00000000
73ccb341 GJ	264
	265	#if defined(CONFIG_CMD_KGDB)
	266	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
73ccb341 GJ	267	#endif
	268
	269	/* ENVIRONMENT VARS */
	270
	271	#define CONFIG_IPADDR 192.168.1.67
	272	#define CONFIG_SERVERIP 192.168.1.50
	273	#define CONFIG_GATEWAYIP 192.168.1.1
	274	#define CONFIG_NETMASK 255.255.255.0
	275	#define CONFIG_LOADADDR 300000
	276	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	277
	278	/* pass open firmware flat tree */
	279	#define CONFIG_OF_LIBFDT 1
	280
	281	#endif /* __CONFIG_H */