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da93ed81 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2003-2005 |
da93ed81 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | * changes for 16M board | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
32 | /* | |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | ||
37 | #undef CONFIG_MPC860 | |
38 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
39 | #define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ | |
40 | #define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ | |
41 | ||
42 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
43 | #undef CONFIG_8xx_CONS_SMC2 | |
44 | #undef CONFIG_8xx_CONS_NONE | |
45 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ | |
46 | #if 0 | |
47 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
48 | #else | |
49 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
50 | #endif | |
51 | ||
52 | /* default developmenmt environment */ | |
53 | ||
da93ed81 WD |
54 | #define CONFIG_ETHADDR 00:0B:17:00:00:00 |
55 | ||
56 | #define CONFIG_IPADDR 10.10.69.10 | |
57 | #define CONFIG_SERVERIP 10.10.69.49 | |
58 | #define CONFIG_NETMASK 255.255.255.0 | |
59 | #define CONFIG_HOSTNAME QUANTUM | |
60 | #define CONFIG_ROOTPATH /opt/eldk/pcc_8xx | |
61 | ||
62 | #define CONFIG_BOOTARGS "root=/dev/ram rw" | |
63 | ||
64 | #define CONFIG_BOOTCOMMAND "bootm ff000000" | |
65 | ||
66 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
67 | "serial#=12345\0" \ | |
fe126d8b | 68 | "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ |
da93ed81 | 69 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b | 70 | "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" |
da93ed81 WD |
71 | |
72 | /* | |
73 | * Select the more full-featured memory test (Barr embedded systems) | |
74 | */ | |
6d0f6bcf | 75 | #define CONFIG_SYS_ALT_MEMTEST |
da93ed81 WD |
76 | |
77 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 78 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
da93ed81 WD |
79 | |
80 | ||
81 | /* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ | |
82 | #define CONFIG_RTC_M48T35A 1 | |
83 | ||
84 | #if 0 | |
85 | #define CONFIG_WATCHDOG 1 /* watchdog enabled */ | |
86 | #else | |
87 | #undef CONFIG_WATCHDOG | |
88 | #endif | |
89 | ||
90 | /* NVRAM and RTC */ | |
6d0f6bcf JCPV |
91 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000 |
92 | #define CONFIG_SYS_NVRAM_SIZE 2048 | |
da93ed81 WD |
93 | |
94 | ||
90cc3eb6 JL |
95 | /* |
96 | * Command line configuration. | |
97 | */ | |
98 | #include <config_cmd_default.h> | |
da93ed81 | 99 | |
90cc3eb6 JL |
100 | #define CONFIG_CMD_DATE |
101 | #define CONFIG_CMD_DHCP | |
102 | #define CONFIG_CMD_NFS | |
103 | #define CONFIG_CMD_PING | |
104 | #define CONFIG_CMD_REGINFO | |
105 | #define CONFIG_CMD_SNTP | |
da93ed81 | 106 | |
90cc3eb6 | 107 | |
d3b8c1a7 JL |
108 | /* |
109 | * BOOTP options | |
110 | */ | |
111 | #define CONFIG_BOOTP_SUBNETMASK | |
112 | #define CONFIG_BOOTP_GATEWAY | |
113 | #define CONFIG_BOOTP_HOSTNAME | |
114 | #define CONFIG_BOOTP_BOOTPATH | |
115 | #define CONFIG_BOOTP_BOOTFILESIZE | |
116 | ||
da93ed81 WD |
117 | |
118 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ | |
c37207d7 WD |
119 | #define CONFIG_AUTOBOOT_PROMPT \ |
120 | "\nEnter password - autoboot in %d sec...\n", bootdelay | |
da93ed81 WD |
121 | #define CONFIG_AUTOBOOT_DELAY_STR "system" |
122 | /* | |
123 | * Miscellaneous configurable options | |
124 | */ | |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
126 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
90cc3eb6 | 127 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 128 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
da93ed81 | 129 | #else |
6d0f6bcf | 130 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
da93ed81 | 131 | #endif |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
133 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
134 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
da93ed81 | 135 | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */ |
137 | #define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ | |
da93ed81 | 138 | |
6d0f6bcf | 139 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
da93ed81 | 140 | |
6d0f6bcf | 141 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
da93ed81 | 142 | |
6d0f6bcf | 143 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
da93ed81 WD |
144 | |
145 | /* | |
146 | * Low Level Configuration Settings | |
147 | * (address mappings, register initial values, etc.) | |
148 | * You should know what you are doing if you make changes here. | |
149 | */ | |
150 | /*----------------------------------------------------------------------- | |
151 | * Internal Memory Mapped Register | |
152 | */ | |
6d0f6bcf | 153 | #define CONFIG_SYS_IMMR 0xFA200000 |
da93ed81 WD |
154 | |
155 | /*----------------------------------------------------------------------- | |
156 | * Definitions for initial stack pointer and data area (in DPRAM) | |
157 | */ | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
159 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
160 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
161 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
162 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
da93ed81 WD |
163 | |
164 | /*----------------------------------------------------------------------- | |
165 | * Start addresses for the final memory configuration | |
166 | * (Set up by the startup code) | |
6d0f6bcf | 167 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
da93ed81 | 168 | */ |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
170 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
da93ed81 WD |
171 | |
172 | #if 1 | |
00b1883a | 173 | #define CONFIG_FLASH_CFI_DRIVER |
da93ed81 | 174 | #else |
00b1883a | 175 | #undef CONFIG_FLASH_CFI_DRIVER |
da93ed81 WD |
176 | #endif |
177 | ||
178 | ||
00b1883a | 179 | #ifdef CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_FLASH_CFI 1 |
181 | #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
182 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
da93ed81 WD |
183 | #endif |
184 | ||
6d0f6bcf | 185 | /*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */ |
90cc3eb6 | 186 | #if defined(DEBUG) || defined(CONFIG_CMD_IDE) |
6d0f6bcf | 187 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
da93ed81 | 188 | #else |
6d0f6bcf | 189 | #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
da93ed81 | 190 | #endif |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_MONITOR_BASE 0xFFF00000 |
192 | /*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ | |
193 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
da93ed81 WD |
194 | |
195 | /* | |
196 | * For booting Linux, the board info and command line data | |
197 | * have to be in the first 8 MB of memory, since this is | |
198 | * the maximum mapped by the Linux kernel during initialization. | |
199 | */ | |
6d0f6bcf | 200 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
da93ed81 WD |
201 | |
202 | /*----------------------------------------------------------------------- | |
203 | * FLASH organization | |
204 | */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
206 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
da93ed81 | 207 | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
209 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
da93ed81 | 210 | |
5a1aceb0 | 211 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
212 | #define CONFIG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/ |
213 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
214 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
6d0f6bcf | 215 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
da93ed81 WD |
216 | |
217 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
218 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
219 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
da93ed81 WD |
220 | |
221 | /* FPGA */ | |
222 | #define CONFIG_MISC_INIT_R | |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_FPGA_SPARTAN2 |
224 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK | |
da93ed81 WD |
225 | |
226 | ||
227 | /*----------------------------------------------------------------------- | |
228 | * Reset address | |
229 | */ | |
6d0f6bcf | 230 | #define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) |
da93ed81 WD |
231 | |
232 | /*----------------------------------------------------------------------- | |
233 | * Cache Configuration | |
234 | */ | |
6d0f6bcf | 235 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
90cc3eb6 | 236 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 237 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
da93ed81 WD |
238 | #endif |
239 | ||
240 | /*----------------------------------------------------------------------- | |
241 | * SYPCR - System Protection Control 11-9 | |
242 | * SYPCR can only be written once after reset! | |
243 | *----------------------------------------------------------------------- | |
244 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
245 | */ | |
246 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 247 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
da93ed81 WD |
248 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
249 | #else | |
6d0f6bcf | 250 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
da93ed81 WD |
251 | #endif |
252 | ||
253 | /*----------------------------------------------------------------------- | |
254 | * SIUMCR - SIU Module Configuration 11-6 | |
255 | *----------------------------------------------------------------------- | |
256 | * PCMCIA config., multi-function pin tri-state | |
257 | */ | |
6d0f6bcf | 258 | #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) |
da93ed81 WD |
259 | |
260 | /*----------------------------------------------------------------------- | |
261 | * TBSCR - Time Base Status and Control 11-26 | |
262 | *----------------------------------------------------------------------- | |
263 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
264 | */ | |
6d0f6bcf | 265 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
da93ed81 WD |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
269 | *----------------------------------------------------------------------- | |
270 | */ | |
6d0f6bcf JCPV |
271 | /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ |
272 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) | |
da93ed81 WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
276 | *----------------------------------------------------------------------- | |
277 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
278 | */ | |
6d0f6bcf | 279 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
da93ed81 WD |
280 | |
281 | /*----------------------------------------------------------------------- | |
282 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
283 | *----------------------------------------------------------------------- | |
284 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
285 | * interrupt status bit | |
286 | * | |
287 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
288 | */ | |
289 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) |
da93ed81 WD |
291 | |
292 | /*----------------------------------------------------------------------- | |
293 | * SCCR - System Clock and reset Control Register 15-27 | |
294 | *----------------------------------------------------------------------- | |
295 | * Set clock output, timebase and RTC source and divider, | |
296 | * power management and some other internal clocks | |
297 | */ | |
298 | #define SCCR_MASK SCCR_EBDF00 | |
299 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 300 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) |
da93ed81 WD |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * PCMCIA stuff | |
304 | *----------------------------------------------------------------------- | |
305 | * | |
306 | */ | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
308 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
309 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
310 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
311 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
312 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
313 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
314 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
da93ed81 WD |
315 | |
316 | /*----------------------------------------------------------------------- | |
317 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
318 | *----------------------------------------------------------------------- | |
319 | */ | |
320 | ||
321 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
322 | ||
323 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
324 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
325 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
326 | ||
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
328 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
da93ed81 | 329 | |
6d0f6bcf | 330 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
da93ed81 | 331 | |
6d0f6bcf | 332 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
da93ed81 WD |
333 | |
334 | /* Offset for data I/O */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
da93ed81 WD |
336 | |
337 | /* Offset for normal register accesses */ | |
6d0f6bcf | 338 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
da93ed81 WD |
339 | |
340 | /* Offset for alternate registers */ | |
6d0f6bcf | 341 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
da93ed81 WD |
342 | |
343 | /*----------------------------------------------------------------------- | |
344 | * | |
345 | *----------------------------------------------------------------------- | |
346 | * | |
347 | */ | |
6d0f6bcf JCPV |
348 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
349 | #define CONFIG_SYS_DER 0 | |
da93ed81 WD |
350 | |
351 | /* | |
352 | * Init Memory Controller: | |
353 | * | |
354 | * BR0 and OR0 (FLASH) | |
355 | */ | |
356 | ||
357 | #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ | |
6d0f6bcf | 358 | #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ |
da93ed81 WD |
359 | |
360 | /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ | |
6d0f6bcf | 361 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) |
da93ed81 | 362 | |
6d0f6bcf JCPV |
363 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
364 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) | |
da93ed81 WD |
365 | |
366 | /* | |
367 | * BR1 and OR1 (SDRAM) | |
368 | * | |
369 | */ | |
370 | #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ | |
371 | #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ | |
372 | ||
373 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 374 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 |
da93ed81 | 375 | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */ |
377 | #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
da93ed81 WD |
378 | |
379 | /* RPXLITE mem setting */ | |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */ |
381 | #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 | |
da93ed81 | 382 | |
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ |
384 | #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 | |
da93ed81 WD |
385 | |
386 | /* | |
387 | * Memory Periodic Timer Prescaler | |
388 | */ | |
389 | ||
390 | /* periodic timer for refresh */ | |
6d0f6bcf | 391 | #define CONFIG_SYS_MAMR_PTA 20 |
da93ed81 WD |
392 | |
393 | /* | |
394 | * Refresh clock Prescalar | |
395 | */ | |
6d0f6bcf | 396 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 |
da93ed81 WD |
397 | |
398 | /* | |
399 | * MAMR settings for SDRAM | |
400 | */ | |
401 | ||
402 | /* 9 column SDRAM */ | |
6d0f6bcf | 403 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
da93ed81 WD |
404 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
405 | MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) | |
406 | ||
407 | /* | |
408 | * Internal Definitions | |
409 | * | |
410 | * Boot Flags | |
411 | */ | |
412 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
413 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
414 | ||
415 | /* | |
416 | * BCSRx | |
417 | * | |
418 | * Board Status and Control Registers | |
419 | * | |
420 | */ | |
421 | ||
422 | #define BCSR0 0xFA400000 | |
423 | #define BCSR1 0xFA400001 | |
424 | #define BCSR2 0xFA400002 | |
425 | #define BCSR3 0xFA400003 | |
426 | ||
427 | #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ | |
428 | #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ | |
429 | #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ | |
430 | #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ | |
431 | #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ | |
432 | #define BCSR0_COLTEST 0x20 | |
433 | #define BCSR0_ETHLPBK 0x40 | |
434 | #define BCSR0_ETHEN 0x80 | |
435 | ||
436 | #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ | |
437 | #define BCSR1_PCVCTL6 0x02 | |
438 | #define BCSR1_PCVCTL5 0x04 | |
439 | #define BCSR1_PCVCTL4 0x08 | |
440 | #define BCSR1_IPB5SEL 0x10 | |
441 | ||
442 | #define BCSR2_ENPA5HDR 0x08 /* USB Control */ | |
443 | #define BCSR2_ENUSBCLK 0x10 | |
444 | #define BCSR2_USBPWREN 0x20 | |
445 | #define BCSR2_USBSPD 0x40 | |
446 | #define BCSR2_USBSUSP 0x80 | |
447 | ||
448 | #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ | |
449 | #define BCSR3_BWNVR 0x02 /* NVRAM Battery */ | |
450 | #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ | |
451 | #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ | |
452 | #define BCSR3_D27 0x10 /* Dip Switch settings */ | |
453 | #define BCSR3_D26 0x20 | |
454 | #define BCSR3_D25 0x40 | |
455 | #define BCSR3_D24 0x80 | |
456 | ||
457 | #endif /* __CONFIG_H */ |