[u-boot.git] / include / configs / r0p7734.h

/*
 * Configuation settings for the Renesas Solutions r0p7734 board
 *
 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __R0P7734_H
#define __R0P7734_H

#define CONFIG_CPU_SH7734	1
#define CONFIG_400MHZ_MODE	1

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
#define CONFIG_PHY_SMSC 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

/* undef to save memory	*/
#define CONFIG_SYS_LONGHELP
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF			1
#define CONFIG_CONS_SCIF3	1

/* Suppress display of console information at boot */

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
/* Enable alternate, more extensive, memory test */
#undef  CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH

/* Enable temporary baudrate change while serial download */
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

/*
 * Use hardware flash sectors protection instead
 * of U-Boot software protection
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* ENV setting */
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
#if defined(CONFIG_400MHZ_MODE)
#define CONFIG_SYS_CLK_FREQ 50000000
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV      4

#endif	/* __R0P7734_H */
Commit	Line	Data
8ca805e1 NI	1	/*
	2	* Configuation settings for the Renesas Solutions r0p7734 board
	3	*
	4	* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
8ca805e1 NI	7	*/
	8
	9	#ifndef __R0P7734_H
	10	#define __R0P7734_H
	11
8ca805e1	12	#define CONFIG_CPU_SH7734 1
8ca805e1	13	#define CONFIG_400MHZ_MODE 1
8ca805e1	14
18a40e84	15	#define CONFIG_DISPLAY_BOARDINFO
8ca805e1 NI	16	#undef CONFIG_SHOW_BOOT_PROGRESS
	17
	18	/* Ether */
8ca805e1 NI	19	#define CONFIG_SH_ETHER_USE_PORT (0)
8ca805e1 NI	20	#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
8ca805e1 NI	21	#define CONFIG_PHY_SMSC 1
	22	#define CONFIG_BITBANGMII
	23	#define CONFIG_BITBANGMII_MULTI
a80a6619 NI	24	#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
a80a6619 NI	25	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
8ca805e1 NI	26
	27	/* undef to save memory */
	28	#define CONFIG_SYS_LONGHELP
8ca805e1 NI	29	/* List of legal baudrate settings for this board */
	30	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	31
	32	/* SCIF */
8ca805e1 NI	33	#define CONFIG_SCIF 1
	34	#define CONFIG_CONS_SCIF3 1
	35
	36	/* Suppress display of console information at boot */
8ca805e1 NI	37
	38	/* SDRAM */
	39	#define CONFIG_SYS_SDRAM_BASE (0x88000000)
	40	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
	41	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
	42
	43	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
	44	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
	45	/* Enable alternate, more extensive, memory test */
	46	#undef CONFIG_SYS_ALT_MEMTEST
	47	/* Scratch address used by the alternate memory test */
	48	#undef CONFIG_SYS_MEMTEST_SCRATCH
	49
	50	/* Enable temporary baudrate change while serial download */
	51	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	52
	53	/* FLASH */
	54	#define CONFIG_FLASH_CFI_DRIVER 1
	55	#define CONFIG_SYS_FLASH_CFI
	56	#undef CONFIG_SYS_FLASH_QUIET_TEST
	57	#define CONFIG_SYS_FLASH_EMPTY_INFO
	58	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	59	#define CONFIG_SYS_MAX_FLASH_SECT 512
	60
	61	/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
	62	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	63	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	64
	65	/* Timeout for Flash erase operations (in ms) */
	66	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	67	/* Timeout for Flash write operations (in ms) */
	68	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	69	/* Timeout for Flash set sector lock bit operations (in ms) */
	70	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	71	/* Timeout for Flash clear lock bit operations (in ms) */
	72	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
	73
	74	/*
	75	* Use hardware flash sectors protection instead
	76	* of U-Boot software protection
	77	*/
	78	#undef CONFIG_SYS_FLASH_PROTECTION
	79	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
	80
	81	/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
	82	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
	83	/* Monitor size */
	84	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	85	/* Size of DRAM reserved for malloc() use */
	86	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
8ca805e1 NI	87	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	88
	89	/* ENV setting */
8ca805e1 NI	90	#define CONFIG_ENV_OVERWRITE 1
	91	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	92	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	93	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	94	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	95	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
	96	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	97
	98	/* Board Clock */
	99	#if defined(CONFIG_400MHZ_MODE)
	100	#define CONFIG_SYS_CLK_FREQ 50000000
	101	#else
	102	#define CONFIG_SYS_CLK_FREQ 44444444
	103	#endif
684a501e NI	104	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	105	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8ca805e1	106	#define CONFIG_SYS_TMU_CLK_DIV 4
8ca805e1 NI	107
8ca805e1 NI	108	#endif /* __R0P7734_H */