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Commit | Line | Data |
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f5e2466f NI |
1 | #ifndef __CONFIG_H |
2 | #define __CONFIG_H | |
3 | ||
4 | #undef DEBUG | |
5 | ||
f5e2466f NI |
6 | #define CONFIG_CPU_SH7751 1 |
7 | #define CONFIG_CPU_SH_TYPE_R 1 | |
8 | #define CONFIG_R2DPLUS 1 | |
9 | #define __LITTLE_ENDIAN__ 1 | |
10 | ||
11 | /* | |
12 | * Command line configuration. | |
13 | */ | |
14 | #include <config_cmd_default.h> | |
15 | ||
f5e2466f NI |
16 | #define CONFIG_CMD_CACHE |
17 | #define CONFIG_CMD_FLASH | |
18 | #define CONFIG_CMD_PCI | |
19 | #define CONFIG_CMD_NET | |
20 | #define CONFIG_CMD_PING | |
21 | #define CONFIG_CMD_IDE | |
22 | #define CONFIG_CMD_EXT2 | |
23 | #define CONFIG_DOS_PARTITION | |
c8d47279 | 24 | #define CONFIG_CMD_SH_ZIMAGEBOOT |
f5e2466f NI |
25 | |
26 | /* SCIF */ | |
6c58a030 | 27 | #define CONFIG_SCIF_CONSOLE 1 |
f5e2466f NI |
28 | #define CONFIG_BAUDRATE 115200 |
29 | #define CONFIG_CONS_SCIF1 1 | |
9660e442 | 30 | #define CONFIG_BOARD_LATE_INIT |
f5e2466f NI |
31 | |
32 | #define CONFIG_BOOTDELAY -1 | |
33 | #define CONFIG_BOOTARGS "console=ttySC0,115200" | |
34 | #define CONFIG_ENV_OVERWRITE 1 | |
35 | ||
f5e2466f | 36 | /* SDRAM */ |
6d0f6bcf JCPV |
37 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
38 | #define CONFIG_SYS_SDRAM_SIZE (0x04000000) | |
39 | ||
653f985b | 40 | #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 |
6d0f6bcf | 41 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
42 | #define CONFIG_SYS_CBSIZE 256 |
43 | #define CONFIG_SYS_PBSIZE 256 | |
44 | #define CONFIG_SYS_MAXARGS 16 | |
45 | #define CONFIG_SYS_BARGSIZE 512 | |
f5e2466f | 46 | |
6d0f6bcf | 47 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 48 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
f5e2466f | 49 | |
6d0f6bcf | 50 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
f5e2466f | 51 | /* Address of u-boot image in Flash */ |
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
53 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
f5e2466f | 54 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 55 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
6d0f6bcf | 56 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
f5e2466f NI |
57 | |
58 | /* | |
873d97aa | 59 | * NOR Flash ( Spantion S29GL256P ) |
f5e2466f | 60 | */ |
6d0f6bcf | 61 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 62 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
63 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
64 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
65 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
66 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
f5e2466f | 67 | |
5a1aceb0 | 68 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
69 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
70 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf | 71 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
f5e2466f NI |
72 | |
73 | /* | |
74 | * SuperH Clock setting | |
75 | */ | |
76 | #define CONFIG_SYS_CLK_FREQ 60000000 | |
684a501e NI |
77 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
78 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 79 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
6d0f6bcf | 80 | #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ |
f5e2466f NI |
81 | |
82 | /* | |
83 | * IDE support | |
84 | */ | |
85 | #define CONFIG_IDE_RESET 1 | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_PIO_MODE 1 |
87 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
88 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
89 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
90 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
91 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
92 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
93 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
f2a37fcd | 94 | #define CONFIG_IDE_SWAP_IO |
f5e2466f NI |
95 | |
96 | /* | |
97 | * SuperH PCI Bridge Configration | |
98 | */ | |
99 | #define CONFIG_PCI | |
100 | #define CONFIG_SH4_PCI | |
101 | #define CONFIG_SH7751_PCI | |
102 | #define CONFIG_PCI_PNP | |
103 | #define CONFIG_PCI_SCAN_SHOW 1 | |
104 | #define __io | |
105 | #define __mem_pci | |
106 | ||
107 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
108 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
109 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
110 | #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ | |
111 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
112 | #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ | |
2db0e127 YS |
113 | #define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) |
114 | #define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) | |
115 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE | |
f5e2466f NI |
116 | |
117 | /* | |
118 | * Network device (RTL8139) support | |
119 | */ | |
f5e2466f | 120 | #define CONFIG_RTL8139 |
f5e2466f NI |
121 | |
122 | #endif /* __CONFIG_H */ |