[people/ms/u-boot.git] / include / configs / r2dplus.h

#ifndef __CONFIG_H
#define __CONFIG_H

#undef DEBUG

#define CONFIG_SH		1
#define CONFIG_SH4		1
#define CONFIG_CPU_SH7751	1
#define CONFIG_CPU_SH_TYPE_R	1
#define CONFIG_R2DPLUS		1
#define __LITTLE_ENDIAN__	1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DFL
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_CONS_SCIF1	1
#define BOARD_LATE_INIT		1

#define CONFIG_BOOTDELAY	-1
#define CONFIG_BOOTARGS		"console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE	1

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(0x04000000)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }

#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(TEXT_BASE - 0x100000)

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	(256)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/*
 * NOR Flash ( Spantion S29GL256P )
 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
#define CONFIG_SYS_MAX_FLASH_SECT  256
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)

/*
 * SuperH Clock setting
 */
#define CONFIG_SYS_CLK_FREQ	60000000
#define TMU_CLK_DIVIDER		4
#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
#define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */

/*
 * IDE support
 */
#define CONFIG_IDE_RESET	1
#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1 /* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
#define CONFIG_SYS_ATA_STRIDE		2 /* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */

/*
 * SuperH PCI Bridge Configration
 */
#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7751_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW	1
#define __io
#define __mem_pci

#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
#define CONFIG_PCI_IO_BUS	0xFE240000	/* IO space base address */
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x00040000	/* Size of IO window */

/*
 * Network device (RTL8139) support
 */
#define CONFIG_NET_MULTI
#define CONFIG_RTL8139
#define _IO_BASE		0x00000000
#define KSEG1ADDR(x)		(x)

#endif /* __CONFIG_H */
Commit	Line	Data
f5e2466f NI	1	#ifndef __CONFIG_H
	2	#define __CONFIG_H
	3
	4	#undef DEBUG
	5
	6	#define CONFIG_SH 1
	7	#define CONFIG_SH4 1
	8	#define CONFIG_CPU_SH7751 1
	9	#define CONFIG_CPU_SH_TYPE_R 1
	10	#define CONFIG_R2DPLUS 1
	11	#define __LITTLE_ENDIAN__ 1
	12
	13	/*
	14	* Command line configuration.
	15	*/
	16	#include <config_cmd_default.h>
	17
	18	#define CONFIG_CMD_DFL
	19	#define CONFIG_CMD_CACHE
	20	#define CONFIG_CMD_FLASH
	21	#define CONFIG_CMD_PCI
	22	#define CONFIG_CMD_NET
	23	#define CONFIG_CMD_PING
	24	#define CONFIG_CMD_IDE
	25	#define CONFIG_CMD_EXT2
	26	#define CONFIG_DOS_PARTITION
	27
	28	/* SCIF */
6c58a030	29	#define CONFIG_SCIF_CONSOLE 1
f5e2466f NI	30	#define CONFIG_BAUDRATE 115200
	31	#define CONFIG_CONS_SCIF1 1
	32	#define BOARD_LATE_INIT 1
	33
	34	#define CONFIG_BOOTDELAY -1
	35	#define CONFIG_BOOTARGS "console=ttySC0,115200"
	36	#define CONFIG_ENV_OVERWRITE 1
	37
f5e2466f	38	/* SDRAM */
6d0f6bcf JCPV	39	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	40	#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
	41
	42	#define CONFIG_SYS_LONGHELP
	43	#define CONFIG_SYS_PROMPT "=> "
	44	#define CONFIG_SYS_CBSIZE 256
	45	#define CONFIG_SYS_PBSIZE 256
	46	#define CONFIG_SYS_MAXARGS 16
	47	#define CONFIG_SYS_BARGSIZE 512
f5e2466f	48	/* List of legal baudrate settings for this board */
6d0f6bcf	49	#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
f5e2466f	50
6d0f6bcf JCPV	51	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
6d0f6bcf JCPV	52	#define CONFIG_SYS_MEMTEST_END (TEXT_BASE - 0x100000)
f5e2466f	53
6d0f6bcf	54	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
f5e2466f	55	/* Address of u-boot image in Flash */
6d0f6bcf JCPV	56	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	57	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
f5e2466f	58	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	59	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
f5e2466f	60	/* size in bytes reserved for initial data */
6d0f6bcf JCPV	61	#define CONFIG_SYS_GBL_DATA_SIZE (256)
6d0f6bcf JCPV	62	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
f5e2466f NI	63
f5e2466f NI	64	/*
873d97aa	65	* NOR Flash ( Spantion S29GL256P )
f5e2466f	66	*/
6d0f6bcf	67	#define CONFIG_SYS_FLASH_CFI
00b1883a	68	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	69	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	70	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	71	#define CONFIG_SYS_MAX_FLASH_SECT 256
	72	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
f5e2466f	73
5a1aceb0	74	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	75	#define CONFIG_ENV_SECT_SIZE 0x40000
0e8d1586 JCPV	76	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf	77	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
f5e2466f NI	78
	79	/*
	80	* SuperH Clock setting
	81	*/
	82	#define CONFIG_SYS_CLK_FREQ 60000000
	83	#define TMU_CLK_DIVIDER 4
6d0f6bcf JCPV	84	#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
6d0f6bcf JCPV	85	#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
f5e2466f NI	86
	87	/*
	88	* IDE support
	89	*/
	90	#define CONFIG_IDE_RESET 1
6d0f6bcf JCPV	91	#define CONFIG_SYS_PIO_MODE 1
	92	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
	93	#define CONFIG_SYS_IDE_MAXDEVICE 1
	94	#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
	95	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
	96	#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
	97	#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
	98	#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
f5e2466f NI	99
	100	/*
	101	* SuperH PCI Bridge Configration
	102	*/
	103	#define CONFIG_PCI
	104	#define CONFIG_SH4_PCI
	105	#define CONFIG_SH7751_PCI
	106	#define CONFIG_PCI_PNP
	107	#define CONFIG_PCI_SCAN_SHOW 1
	108	#define __io
	109	#define __mem_pci
	110
	111	#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
	112	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	113	#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
	114	#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
	115	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	116	#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
	117
	118	/*
	119	* Network device (RTL8139) support
	120	*/
	121	#define CONFIG_NET_MULTI
	122	#define CONFIG_RTL8139
	123	#define _IO_BASE 0x00000000
	124	#define KSEG1ADDR(x) (x)
	125
	126	#endif /* __CONFIG_H */