[people/ms/u-boot.git] / include / configs / r2dplus.h

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_CPU_SH7751	1
#define CONFIG_CPU_SH_TYPE_R	1
#define CONFIG_R2DPLUS		1
#define __LITTLE_ENDIAN__	1

#define CONFIG_DISPLAY_BOARDINFO

/*
 * Command line configuration.
 */
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SH_ZIMAGEBOOT

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF1	1

#define CONFIG_BOOTARGS		"console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE	1

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		0x8C000000
#define CONFIG_SYS_SDRAM_SIZE		0x04000000

#define CONFIG_SYS_TEXT_BASE		0x8FE00000
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512

#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/*
 * NOR Flash ( Spantion S29GL256P )
 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
#define CONFIG_SYS_MAX_FLASH_SECT  256
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)

/*
 * SuperH Clock setting
 */
#define CONFIG_SYS_CLK_FREQ	60000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4
#define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */

/*
 * IDE support
 */
#define CONFIG_IDE_RESET	1
#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1 /* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
#define CONFIG_SYS_ATA_STRIDE		2 /* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */
#define CONFIG_IDE_SWAP_IO

/*
 * SuperH PCI Bridge Configration
 */
#define CONFIG_SH4_PCI
#define CONFIG_SH7751_PCI
#define CONFIG_PCI_SCAN_SHOW	1
#define __mem_pci

#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
#define CONFIG_PCI_IO_BUS	0xFE240000	/* IO space base address */
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x00040000	/* Size of IO window */
#define CONFIG_PCI_SYS_BUS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_PHYS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE	CONFIG_SYS_SDRAM_SIZE

#endif /* __CONFIG_H */
Commit	Line	Data
f5e2466f NI	1	#ifndef __CONFIG_H
	2	#define __CONFIG_H
	3
f5e2466f NI	4	#define CONFIG_CPU_SH7751 1
	5	#define CONFIG_CPU_SH_TYPE_R 1
	6	#define CONFIG_R2DPLUS 1
	7	#define __LITTLE_ENDIAN__ 1
	8
18a40e84 VZ	9	#define CONFIG_DISPLAY_BOARDINFO
18a40e84 VZ	10
f5e2466f NI	11	/*
	12	* Command line configuration.
	13	*/
f5e2466f	14	#define CONFIG_CMD_PCI
c8d47279	15	#define CONFIG_CMD_SH_ZIMAGEBOOT
f5e2466f NI	16
f5e2466f NI	17	/* SCIF */
6c58a030	18	#define CONFIG_SCIF_CONSOLE 1
f5e2466f	19	#define CONFIG_CONS_SCIF1 1
f5e2466f	20
f5e2466f NI	21	#define CONFIG_BOOTARGS "console=ttySC0,115200"
	22	#define CONFIG_ENV_OVERWRITE 1
	23
f5e2466f	24	/* SDRAM */
76527047 VZ	25	#define CONFIG_SYS_SDRAM_BASE 0x8C000000
76527047 VZ	26	#define CONFIG_SYS_SDRAM_SIZE 0x04000000
6d0f6bcf	27
47c5705d	28	#define CONFIG_SYS_TEXT_BASE 0x8FE00000
6d0f6bcf	29	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	30	#define CONFIG_SYS_CBSIZE 256
	31	#define CONFIG_SYS_PBSIZE 256
	32	#define CONFIG_SYS_MAXARGS 16
	33	#define CONFIG_SYS_BARGSIZE 512
f5e2466f	34
6d0f6bcf	35	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
14d0a02a	36	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
f5e2466f	37
6d0f6bcf	38	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
f5e2466f	39	/* Address of u-boot image in Flash */
6d0f6bcf JCPV	40	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	41	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
f5e2466f	42	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	43	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
6d0f6bcf	44	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
f5e2466f NI	45
f5e2466f NI	46	/*
873d97aa	47	* NOR Flash ( Spantion S29GL256P )
f5e2466f	48	*/
6d0f6bcf	49	#define CONFIG_SYS_FLASH_CFI
00b1883a	50	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	51	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	52	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	53	#define CONFIG_SYS_MAX_FLASH_SECT 256
	54	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
f5e2466f	55
5a1aceb0	56	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	57	#define CONFIG_ENV_SECT_SIZE 0x40000
0e8d1586 JCPV	58	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf	59	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
f5e2466f NI	60
	61	/*
	62	* SuperH Clock setting
	63	*/
	64	#define CONFIG_SYS_CLK_FREQ 60000000
684a501e NI	65	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	66	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	67	#define CONFIG_SYS_TMU_CLK_DIV 4
6d0f6bcf	68	#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
f5e2466f NI	69
	70	/*
	71	* IDE support
	72	*/
	73	#define CONFIG_IDE_RESET 1
6d0f6bcf JCPV	74	#define CONFIG_SYS_PIO_MODE 1
	75	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
	76	#define CONFIG_SYS_IDE_MAXDEVICE 1
	77	#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
	78	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
	79	#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
	80	#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
	81	#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
f2a37fcd	82	#define CONFIG_IDE_SWAP_IO
f5e2466f NI	83
	84	/*
	85	* SuperH PCI Bridge Configration
	86	*/
f5e2466f NI	87	#define CONFIG_SH4_PCI
f5e2466f NI	88	#define CONFIG_SH7751_PCI
f5e2466f	89	#define CONFIG_PCI_SCAN_SHOW 1
f5e2466f NI	90	#define __mem_pci
	91
	92	#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
	93	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	94	#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
	95	#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
	96	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	97	#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
76527047 VZ	98	#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
76527047 VZ	99	#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
2db0e127	100	#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
f5e2466f	101
f5e2466f	102	#endif /* __CONFIG_H */