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Commit | Line | Data |
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f5e2466f NI |
1 | #ifndef __CONFIG_H |
2 | #define __CONFIG_H | |
3 | ||
4 | #undef DEBUG | |
5 | ||
f5e2466f NI |
6 | #define CONFIG_CPU_SH7751 1 |
7 | #define CONFIG_CPU_SH_TYPE_R 1 | |
8 | #define CONFIG_R2DPLUS 1 | |
9 | #define __LITTLE_ENDIAN__ 1 | |
10 | ||
11 | /* | |
12 | * Command line configuration. | |
13 | */ | |
f5e2466f | 14 | #define CONFIG_CMD_CACHE |
f5e2466f | 15 | #define CONFIG_CMD_PCI |
f5e2466f NI |
16 | #define CONFIG_CMD_PING |
17 | #define CONFIG_CMD_IDE | |
18 | #define CONFIG_CMD_EXT2 | |
19 | #define CONFIG_DOS_PARTITION | |
c8d47279 | 20 | #define CONFIG_CMD_SH_ZIMAGEBOOT |
f5e2466f NI |
21 | |
22 | /* SCIF */ | |
6c58a030 | 23 | #define CONFIG_SCIF_CONSOLE 1 |
f5e2466f NI |
24 | #define CONFIG_BAUDRATE 115200 |
25 | #define CONFIG_CONS_SCIF1 1 | |
9660e442 | 26 | #define CONFIG_BOARD_LATE_INIT |
f5e2466f NI |
27 | |
28 | #define CONFIG_BOOTDELAY -1 | |
29 | #define CONFIG_BOOTARGS "console=ttySC0,115200" | |
30 | #define CONFIG_ENV_OVERWRITE 1 | |
31 | ||
f5e2466f | 32 | /* SDRAM */ |
6d0f6bcf JCPV |
33 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
34 | #define CONFIG_SYS_SDRAM_SIZE (0x04000000) | |
35 | ||
653f985b | 36 | #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 |
6d0f6bcf | 37 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
38 | #define CONFIG_SYS_CBSIZE 256 |
39 | #define CONFIG_SYS_PBSIZE 256 | |
40 | #define CONFIG_SYS_MAXARGS 16 | |
41 | #define CONFIG_SYS_BARGSIZE 512 | |
f5e2466f | 42 | |
6d0f6bcf | 43 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 44 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
f5e2466f | 45 | |
6d0f6bcf | 46 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
f5e2466f | 47 | /* Address of u-boot image in Flash */ |
6d0f6bcf JCPV |
48 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
49 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
f5e2466f | 50 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 51 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
6d0f6bcf | 52 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
f5e2466f NI |
53 | |
54 | /* | |
873d97aa | 55 | * NOR Flash ( Spantion S29GL256P ) |
f5e2466f | 56 | */ |
6d0f6bcf | 57 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 58 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
59 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
60 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
61 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
62 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
f5e2466f | 63 | |
5a1aceb0 | 64 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
65 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
66 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf | 67 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
f5e2466f NI |
68 | |
69 | /* | |
70 | * SuperH Clock setting | |
71 | */ | |
72 | #define CONFIG_SYS_CLK_FREQ 60000000 | |
684a501e NI |
73 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
74 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 75 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
6d0f6bcf | 76 | #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ |
f5e2466f NI |
77 | |
78 | /* | |
79 | * IDE support | |
80 | */ | |
81 | #define CONFIG_IDE_RESET 1 | |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_PIO_MODE 1 |
83 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
84 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
85 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
86 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
87 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
88 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
89 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
f2a37fcd | 90 | #define CONFIG_IDE_SWAP_IO |
f5e2466f NI |
91 | |
92 | /* | |
93 | * SuperH PCI Bridge Configration | |
94 | */ | |
95 | #define CONFIG_PCI | |
96 | #define CONFIG_SH4_PCI | |
97 | #define CONFIG_SH7751_PCI | |
98 | #define CONFIG_PCI_PNP | |
99 | #define CONFIG_PCI_SCAN_SHOW 1 | |
100 | #define __io | |
101 | #define __mem_pci | |
102 | ||
103 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
104 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
105 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
106 | #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ | |
107 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
108 | #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ | |
2db0e127 YS |
109 | #define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) |
110 | #define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) | |
111 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE | |
f5e2466f NI |
112 | |
113 | /* | |
114 | * Network device (RTL8139) support | |
115 | */ | |
f5e2466f | 116 | #define CONFIG_RTL8139 |
f5e2466f NI |
117 | |
118 | #endif /* __CONFIG_H */ |