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73a8b27c | 1 | /* |
414eec35 | 2 | * (C) Copyright 2003-2005 |
73a8b27c WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | ||
32 | /* | |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | ||
37 | #undef CONFIG_MPC860 | |
38 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
39 | #define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */ | |
40 | #define CONFIG_RMU 1 | |
41 | ||
42 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
43 | #undef CONFIG_8xx_CONS_SMC2 | |
44 | #undef CONFIG_8xx_CONS_NONE | |
45 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ | |
46 | #if 0 | |
47 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
48 | #else | |
49 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
50 | #endif | |
51 | ||
73a8b27c WD |
52 | #undef CONFIG_BOOTARGS |
53 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
54 | "bootp; " \ |
55 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
56 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
73a8b27c WD |
57 | "bootm" |
58 | ||
59 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 60 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
73a8b27c | 61 | |
ca75adde WD |
62 | /* enable I2C and select the hardware/software driver */ |
63 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
64 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
65 | ||
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */ |
67 | #define CONFIG_SYS_I2C_SLAVE 0xFE | |
ca75adde WD |
68 | |
69 | /* Software (bit-bang) I2C driver configuration */ | |
70 | #define PB_SCL 0x00000020 /* PB 26 */ | |
71 | #define PB_SDA 0x00000010 /* PB 27 */ | |
72 | ||
73 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
74 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
75 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
76 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
77 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
78 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
79 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
80 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
81 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
82 | ||
83 | /* M41T11 Serial Access Timekeeper(R) SRAM */ | |
84 | #define CONFIG_RTC_M41T11 1 | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
86 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ | |
ca75adde | 87 | |
73a8b27c WD |
88 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
89 | ||
ca75adde | 90 | |
90cc3eb6 JL |
91 | /* |
92 | * Command line configuration. | |
93 | */ | |
94 | #include <config_cmd_default.h> | |
73a8b27c | 95 | |
90cc3eb6 JL |
96 | #define CONFIG_CMD_DATE |
97 | #define CONFIG_CMD_DHCP | |
98 | #define CONFIG_CMD_I2C | |
99 | #define CONFIG_CMD_NFS | |
100 | #define CONFIG_CMD_SNTP | |
101 | ||
102 | ||
d3b8c1a7 JL |
103 | /* |
104 | * BOOTP options | |
105 | */ | |
106 | #define CONFIG_BOOTP_SUBNETMASK | |
107 | #define CONFIG_BOOTP_GATEWAY | |
108 | #define CONFIG_BOOTP_HOSTNAME | |
109 | #define CONFIG_BOOTP_BOOTPATH | |
110 | #define CONFIG_BOOTP_BOOTFILESIZE | |
111 | ||
73a8b27c | 112 | |
af6d1dfc | 113 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ |
f2302d44 SR |
114 | #define CONFIG_AUTOBOOT_PROMPT \ |
115 | "\nEnter password - autoboot in %d sec...\n", bootdelay | |
af6d1dfc WD |
116 | #define CONFIG_AUTOBOOT_DELAY_STR "system" |
117 | ||
73a8b27c WD |
118 | /* |
119 | * Miscellaneous configurable options | |
120 | */ | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
122 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
90cc3eb6 | 123 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 124 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
73a8b27c | 125 | #else |
6d0f6bcf | 126 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
73a8b27c | 127 | #endif |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
129 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
130 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
73a8b27c | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ |
133 | #define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ | |
73a8b27c | 134 | |
6d0f6bcf | 135 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
73a8b27c | 136 | |
6d0f6bcf | 137 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
73a8b27c | 138 | |
6d0f6bcf | 139 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
73a8b27c WD |
140 | |
141 | /* | |
142 | * Low Level Configuration Settings | |
143 | * (address mappings, register initial values, etc.) | |
144 | * You should know what you are doing if you make changes here. | |
145 | */ | |
146 | /*----------------------------------------------------------------------- | |
147 | * Internal Memory Mapped Register | |
148 | */ | |
6d0f6bcf | 149 | #define CONFIG_SYS_IMMR 0xFA200000 |
73a8b27c WD |
150 | |
151 | /*----------------------------------------------------------------------- | |
152 | * Definitions for initial stack pointer and data area (in DPRAM) | |
153 | */ | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
155 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
156 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
157 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
158 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
73a8b27c WD |
159 | |
160 | /*----------------------------------------------------------------------- | |
161 | * Start addresses for the final memory configuration | |
162 | * (Set up by the startup code) | |
6d0f6bcf | 163 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
73a8b27c | 164 | */ |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
166 | #define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */ | |
90cc3eb6 | 167 | #if defined(DEBUG) || defined(CONFIG_CMD_IDE) |
6d0f6bcf | 168 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
73a8b27c | 169 | #else |
6d0f6bcf | 170 | #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
73a8b27c | 171 | #endif |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
173 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
73a8b27c WD |
174 | |
175 | /* | |
176 | * For booting Linux, the board info and command line data | |
177 | * have to be in the first 8 MB of memory, since this is | |
178 | * the maximum mapped by the Linux kernel during initialization. | |
179 | */ | |
6d0f6bcf | 180 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
73a8b27c WD |
181 | |
182 | /*----------------------------------------------------------------------- | |
183 | * FLASH organization | |
184 | */ | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
186 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
73a8b27c | 187 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
189 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
73a8b27c | 190 | |
5a1aceb0 | 191 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 192 | #define CONFIG_ENV_ADDR ((TEXT_BASE) + 0x40000) |
3a76ab5c WD |
193 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ |
194 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Used size for environment */ | |
73a8b27c WD |
195 | |
196 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
197 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) |
198 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
73a8b27c | 199 | |
ca75adde WD |
200 | /*----------------------------------------------------------------------- |
201 | * Reset address | |
202 | */ | |
6d0f6bcf | 203 | #define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) |
ca75adde | 204 | |
73a8b27c WD |
205 | /*----------------------------------------------------------------------- |
206 | * Cache Configuration | |
207 | */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
90cc3eb6 | 209 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 210 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
73a8b27c WD |
211 | #endif |
212 | ||
213 | /*----------------------------------------------------------------------- | |
214 | * SYPCR - System Protection Control 11-9 | |
215 | * SYPCR can only be written once after reset! | |
216 | *----------------------------------------------------------------------- | |
217 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
218 | */ | |
219 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 220 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
73a8b27c WD |
221 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
222 | #else | |
6d0f6bcf | 223 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
73a8b27c WD |
224 | #endif |
225 | ||
226 | /*----------------------------------------------------------------------- | |
227 | * SIUMCR - SIU Module Configuration 11-6 | |
228 | *----------------------------------------------------------------------- | |
229 | * PCMCIA config., multi-function pin tri-state | |
230 | */ | |
6d0f6bcf | 231 | #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) |
73a8b27c WD |
232 | |
233 | /*----------------------------------------------------------------------- | |
234 | * TBSCR - Time Base Status and Control 11-26 | |
235 | *----------------------------------------------------------------------- | |
236 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
237 | */ | |
6d0f6bcf | 238 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
73a8b27c WD |
239 | |
240 | /*----------------------------------------------------------------------- | |
241 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
242 | *----------------------------------------------------------------------- | |
243 | */ | |
6d0f6bcf JCPV |
244 | /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ |
245 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) | |
73a8b27c WD |
246 | |
247 | /*----------------------------------------------------------------------- | |
248 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
249 | *----------------------------------------------------------------------- | |
250 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
251 | */ | |
6d0f6bcf | 252 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
73a8b27c WD |
253 | |
254 | /*----------------------------------------------------------------------- | |
255 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
256 | *----------------------------------------------------------------------- | |
257 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
258 | * interrupt status bit | |
259 | * | |
260 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
261 | */ | |
262 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 263 | #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) |
73a8b27c WD |
264 | |
265 | /*----------------------------------------------------------------------- | |
266 | * SCCR - System Clock and reset Control Register 15-27 | |
267 | *----------------------------------------------------------------------- | |
268 | * Set clock output, timebase and RTC source and divider, | |
269 | * power management and some other internal clocks | |
270 | */ | |
271 | #define SCCR_MASK SCCR_EBDF00 | |
272 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 273 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) |
73a8b27c WD |
274 | |
275 | /*----------------------------------------------------------------------- | |
276 | * PCMCIA stuff | |
277 | *----------------------------------------------------------------------- | |
278 | * | |
279 | */ | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
281 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
282 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
283 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
284 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
285 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
286 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
287 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
73a8b27c WD |
288 | |
289 | /*----------------------------------------------------------------------- | |
290 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
291 | *----------------------------------------------------------------------- | |
292 | */ | |
293 | ||
294 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
295 | ||
296 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
297 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
298 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
299 | ||
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
301 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
73a8b27c | 302 | |
6d0f6bcf | 303 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
73a8b27c | 304 | |
6d0f6bcf | 305 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
73a8b27c WD |
306 | |
307 | /* Offset for data I/O */ | |
6d0f6bcf | 308 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
73a8b27c WD |
309 | |
310 | /* Offset for normal register accesses */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
73a8b27c WD |
312 | |
313 | /* Offset for alternate registers */ | |
6d0f6bcf | 314 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
73a8b27c WD |
315 | |
316 | /*----------------------------------------------------------------------- | |
317 | * | |
318 | *----------------------------------------------------------------------- | |
319 | * | |
320 | */ | |
6d0f6bcf JCPV |
321 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
322 | #define CONFIG_SYS_DER 0 | |
73a8b27c WD |
323 | |
324 | /* | |
325 | * Init Memory Controller: | |
326 | * | |
327 | * BR0 and OR0 (FLASH) | |
328 | */ | |
329 | ||
7e780369 | 330 | #define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */ |
6d0f6bcf | 331 | #define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */ |
73a8b27c WD |
332 | |
333 | /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ | |
6d0f6bcf | 334 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) |
73a8b27c | 335 | |
6d0f6bcf JCPV |
336 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
337 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) | |
73a8b27c WD |
338 | |
339 | /* | |
340 | * BR1 and OR1 (SDRAM) | |
341 | * | |
342 | */ | |
343 | #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ | |
d94f92cb | 344 | #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ |
73a8b27c WD |
345 | |
346 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 347 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 |
73a8b27c | 348 | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */ |
350 | #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
73a8b27c WD |
351 | |
352 | /* RPXLITE mem setting */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */ |
7e780369 | 354 | /* IMMR: 0xFA200000 IMMR base address - see above */ |
6d0f6bcf | 355 | #define CONFIG_SYS_BCSR_BASE 0xFA400000 /* BCSR base address */ |
7e780369 | 356 | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_BASE | BR_V) /* BCSR */ |
358 | #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 | |
359 | #define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */ | |
360 | #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 | |
73a8b27c WD |
361 | |
362 | /* | |
363 | * Memory Periodic Timer Prescaler | |
364 | */ | |
365 | ||
366 | /* periodic timer for refresh */ | |
6d0f6bcf | 367 | #define CONFIG_SYS_MAMR_PTA 20 |
73a8b27c WD |
368 | |
369 | /* | |
370 | * Refresh clock Prescalar | |
371 | */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 |
73a8b27c WD |
373 | |
374 | /* | |
375 | * MAMR settings for SDRAM | |
376 | */ | |
377 | ||
d94f92cb | 378 | /* 9 column SDRAM */ |
6d0f6bcf | 379 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
73a8b27c WD |
380 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
381 | MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) | |
382 | ||
383 | /* | |
384 | * Internal Definitions | |
385 | * | |
386 | * Boot Flags | |
387 | */ | |
388 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
389 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
390 | ||
391 | /* | |
392 | * BCSRx | |
393 | * | |
394 | * Board Status and Control Registers | |
395 | * | |
396 | */ | |
397 | ||
6d0f6bcf JCPV |
398 | #define BCSR0 (CONFIG_SYS_BCSR_BASE + 0) |
399 | #define BCSR1 (CONFIG_SYS_BCSR_BASE + 1) | |
400 | #define BCSR2 (CONFIG_SYS_BCSR_BASE + 2) | |
401 | #define BCSR3 (CONFIG_SYS_BCSR_BASE + 3) | |
73a8b27c WD |
402 | |
403 | #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ | |
53677ef1 | 404 | #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ |
73a8b27c WD |
405 | #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ |
406 | #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ | |
407 | #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ | |
408 | #define BCSR0_COLTEST 0x20 | |
409 | #define BCSR0_ETHLPBK 0x40 | |
410 | #define BCSR0_ETHEN 0x80 | |
411 | ||
412 | #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ | |
413 | #define BCSR1_PCVCTL6 0x02 | |
414 | #define BCSR1_PCVCTL5 0x04 | |
415 | #define BCSR1_PCVCTL4 0x08 | |
416 | #define BCSR1_IPB5SEL 0x10 | |
417 | ||
418 | #define BCSR2_ENPA5HDR 0x08 /* USB Control */ | |
419 | #define BCSR2_ENUSBCLK 0x10 | |
420 | #define BCSR2_USBPWREN 0x20 | |
421 | #define BCSR2_USBSPD 0x40 | |
422 | #define BCSR2_USBSUSP 0x80 | |
423 | ||
424 | #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ | |
425 | #define BCSR3_BWNVR 0x02 /* NVRAM Battery */ | |
426 | #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ | |
427 | #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ | |
428 | #define BCSR3_D27 0x10 /* Dip Switch settings */ | |
429 | #define BCSR3_D26 0x20 | |
430 | #define BCSR3_D25 0x40 | |
431 | #define BCSR3_D24 0x80 | |
432 | ||
433 | #endif /* __CONFIG_H */ |