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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
4 | * | |
5 | * (C) Copyright 2000 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * Configuation settings for the R&S Protocol Board board. | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
39 | #define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ | |
9c4c5ae3 | 40 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
e2211743 | 41 | |
2ae18241 WD |
42 | #define CONFIG_SYS_TEXT_BASE 0xff000000 |
43 | ||
c837dcb1 WD |
44 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
45 | ||
e2211743 WD |
46 | /* |
47 | * select serial console configuration | |
48 | * | |
49 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
50 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
51 | * for SCC). | |
52 | * | |
53 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
54 | * defined elsewhere. | |
55 | */ | |
56 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
57 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
53677ef1 | 58 | #undef CONFIG_CONS_NONE /* define if console on neither */ |
e2211743 WD |
59 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ |
60 | ||
61 | /* | |
62 | * select ethernet configuration | |
63 | * | |
64 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
65 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
66 | * for FCC) | |
67 | * | |
68 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 69 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
e2211743 WD |
70 | */ |
71 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ | |
72 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ | |
73 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
74 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
75 | ||
76 | #if (CONFIG_ETHER_INDEX == 2) | |
77 | ||
78 | /* | |
79 | * - Rx-CLK is CLK13 | |
80 | * - Tx-CLK is CLK14 | |
81 | * - Select bus for bd/buffers (see 28-13) | |
82 | * - Enable Full Duplex in FSMR | |
83 | */ | |
6d0f6bcf JCPV |
84 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
85 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
86 | # define CONFIG_SYS_CPMFCR_RAMTYPE (0) | |
87 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
e2211743 WD |
88 | |
89 | #endif /* CONFIG_ETHER_INDEX */ | |
90 | ||
91 | ||
92 | /* allow to overwrite serial and ethaddr */ | |
93 | #define CONFIG_ENV_OVERWRITE | |
94 | ||
95 | /* enable I2C */ | |
53677ef1 | 96 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ |
98 | #define CONFIG_SYS_I2C_SLAVE 0x30 | |
e2211743 WD |
99 | |
100 | ||
101 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
102 | #define CONFIG_8260_CLKIN 50000000 /* in Hz */ | |
103 | ||
104 | #define CONFIG_BAUDRATE 115200 | |
105 | ||
90cc3eb6 | 106 | |
079a136c JL |
107 | /* |
108 | * BOOTP options | |
109 | */ | |
110 | #define CONFIG_BOOTP_BOOTFILESIZE | |
111 | #define CONFIG_BOOTP_BOOTPATH | |
112 | #define CONFIG_BOOTP_GATEWAY | |
113 | #define CONFIG_BOOTP_HOSTNAME | |
114 | ||
115 | ||
90cc3eb6 JL |
116 | /* |
117 | * Command line configuration. | |
118 | */ | |
119 | #include <config_cmd_default.h> | |
120 | ||
121 | #undef CONFIG_CMD_KGDB | |
122 | ||
e2211743 WD |
123 | |
124 | /* Define this if you want to boot from 0x00000100. If you don't define | |
125 | * this, you will need to program the bootloader to 0xfff00000, and | |
126 | * get the hardware reset config words at 0xfe000000. The simplest | |
127 | * way to do that is to program the bootloader at both addresses. | |
128 | * It is suggested that you just let U-Boot live at 0x00000000. | |
129 | */ | |
6d0f6bcf | 130 | #define CONFIG_SYS_RSD_BOOT_LOW 1 |
e2211743 | 131 | |
e2211743 | 132 | #define CONFIG_BOOTDELAY 5 |
53677ef1 | 133 | #define CONFIG_BOOTARGS "devfs=mount root=ramfs" |
e2211743 WD |
134 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5a |
135 | #define CONFIG_NETMASK 255.255.0.0 | |
136 | ||
90cc3eb6 | 137 | #if defined(CONFIG_CMD_KGDB) |
e2211743 WD |
138 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
139 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
140 | #endif | |
141 | ||
142 | /* | |
143 | * Miscellaneous configurable options | |
144 | */ | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
146 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
90cc3eb6 | 147 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 148 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e2211743 | 149 | #else |
6d0f6bcf | 150 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 | 151 | #endif |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
153 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
154 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
e2211743 | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ |
157 | #define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ | |
e2211743 | 158 | |
6d0f6bcf | 159 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
e2211743 | 160 | |
6d0f6bcf | 161 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
e2211743 WD |
162 | |
163 | /* valid baudrates */ | |
6d0f6bcf | 164 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
e2211743 WD |
165 | |
166 | /* | |
167 | * Low Level Configuration Settings | |
168 | * (address mappings, register initial values, etc.) | |
169 | * You should know what you are doing if you make changes here. | |
170 | */ | |
171 | ||
172 | /*----------------------------------------------------------------------- | |
173 | * Physical Memory Map | |
174 | */ | |
175 | #define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ | |
176 | #define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ | |
177 | ||
178 | #define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ | |
179 | #define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ | |
180 | ||
53677ef1 WD |
181 | #define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ |
182 | #define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ | |
e2211743 WD |
183 | |
184 | /*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ | |
185 | /*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ | |
186 | ||
53677ef1 WD |
187 | #define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ |
188 | #define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ | |
e2211743 WD |
189 | |
190 | /*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ | |
191 | /*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ | |
192 | ||
193 | #define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ | |
194 | #define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 | |
195 | ||
196 | #define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ | |
197 | #define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ | |
198 | ||
199 | #define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ | |
200 | ||
201 | #define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ | |
202 | #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ | |
203 | ||
6d0f6bcf | 204 | #define CONFIG_SYS_IMMR PHYS_IMMR |
e2211743 WD |
205 | |
206 | /*----------------------------------------------------------------------- | |
207 | * Reset Address | |
208 | * | |
209 | * In order to reset the CPU, U-Boot jumps to a special address which | |
210 | * causes a machine check exception. The default address for this is | |
6d0f6bcf | 211 | * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when |
e2211743 WD |
212 | * testing the monitor in RAM using a JTAG debugger. |
213 | * | |
6d0f6bcf | 214 | * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to |
e2211743 WD |
215 | * cause a bus error on your hardware. |
216 | */ | |
6d0f6bcf | 217 | #define CONFIG_SYS_RESET_ADDRESS 0x20000000 |
e2211743 WD |
218 | |
219 | /*----------------------------------------------------------------------- | |
220 | * Hard Reset Configuration Words | |
221 | */ | |
222 | ||
6d0f6bcf JCPV |
223 | #if defined(CONFIG_SYS_RSD_BOOT_LOW) |
224 | # define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
e2211743 | 225 | #else |
6d0f6bcf JCPV |
226 | # define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0) |
227 | #endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */ | |
e2211743 | 228 | |
6d0f6bcf JCPV |
229 | /* get the HRCW ISB field from CONFIG_SYS_IMMR */ |
230 | #define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\ | |
231 | ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\ | |
232 | ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) | |
e2211743 | 233 | |
6d0f6bcf | 234 | #define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \ |
e2211743 | 235 | HRCW_DPPC11 | \ |
6d0f6bcf | 236 | CONFIG_SYS_RSD_HRCW_IMMR |\ |
8bde7f77 WD |
237 | HRCW_MMR00 | \ |
238 | HRCW_APPC10 | \ | |
239 | HRCW_CS10PC00 | \ | |
240 | HRCW_MODCK_H0000 |\ | |
6d0f6bcf | 241 | CONFIG_SYS_RSD_HRCW_BOOT_FLAGS) |
e2211743 WD |
242 | |
243 | /* no slaves */ | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
245 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
246 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
247 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
248 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
249 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
250 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
e2211743 WD |
251 | |
252 | /*----------------------------------------------------------------------- | |
253 | * Definitions for initial stack pointer and data area (in DPRAM) | |
254 | */ | |
6d0f6bcf | 255 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 256 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 257 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 258 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e2211743 WD |
259 | |
260 | /*----------------------------------------------------------------------- | |
261 | * Start addresses for the final memory configuration | |
262 | * (Set up by the startup code) | |
6d0f6bcf JCPV |
263 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
264 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend. | |
e2211743 | 265 | */ |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X |
267 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH | |
268 | /*#define CONFIG_SYS_MONITOR_BASE 0x200000 */ | |
269 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
270 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE | |
271 | #define CONFIG_SYS_RAMBOOT | |
e2211743 | 272 | #endif |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ |
274 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
e2211743 WD |
275 | |
276 | /* | |
277 | * For booting Linux, the board info and command line data | |
278 | * have to be in the first 8 MB of memory, since this is | |
279 | * the maximum mapped by the Linux kernel during initialization. | |
280 | */ | |
6d0f6bcf | 281 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e2211743 WD |
282 | |
283 | /*----------------------------------------------------------------------- | |
284 | * FLASH and environment organization | |
285 | */ | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
287 | #define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ | |
e2211743 | 288 | |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ |
290 | #define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ | |
e2211743 WD |
291 | |
292 | /* turn off NVRAM env feature */ | |
293 | #undef CONFIG_NVRAM_ENV | |
294 | ||
5a1aceb0 | 295 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
296 | #define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ |
297 | #define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ | |
e2211743 WD |
298 | |
299 | /*----------------------------------------------------------------------- | |
300 | * Cache Configuration | |
301 | */ | |
6d0f6bcf | 302 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
90cc3eb6 | 303 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 304 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
e2211743 WD |
305 | #endif |
306 | ||
307 | /*----------------------------------------------------------------------- | |
308 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
309 | *----------------------------------------------------------------------- | |
310 | * HID0 also contains cache control - initially enable both caches and | |
311 | * invalidate contents, then the final state leaves only the instruction | |
312 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
313 | * but Soft reset does not. | |
314 | * | |
315 | * HID1 has only read-only information - nothing to set. | |
316 | */ | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) |
318 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) | |
319 | #define CONFIG_SYS_HID2 0 | |
e2211743 WD |
320 | |
321 | /*----------------------------------------------------------------------- | |
322 | * RMR - Reset Mode Register | |
323 | *----------------------------------------------------------------------- | |
324 | */ | |
6d0f6bcf | 325 | #define CONFIG_SYS_RMR 0 |
e2211743 WD |
326 | |
327 | /*----------------------------------------------------------------------- | |
328 | * BCR - Bus Configuration 4-25 | |
329 | *----------------------------------------------------------------------- | |
330 | */ | |
6d0f6bcf | 331 | #define CONFIG_SYS_BCR 0x100c0000 |
e2211743 WD |
332 | |
333 | /*----------------------------------------------------------------------- | |
334 | * SIUMCR - SIU Module Configuration 4-31 | |
335 | *----------------------------------------------------------------------- | |
336 | */ | |
337 | ||
6d0f6bcf | 338 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ |
e2211743 WD |
339 | SIUMCR_CS10PC01 | SIUMCR_BCTLC01) |
340 | ||
341 | /*----------------------------------------------------------------------- | |
342 | * SYPCR - System Protection Control 11-9 | |
343 | * SYPCR can only be written once after reset! | |
344 | *----------------------------------------------------------------------- | |
345 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
346 | */ | |
6d0f6bcf | 347 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ |
e2211743 WD |
348 | SYPCR_SWRI | SYPCR_SWP) |
349 | ||
350 | /*----------------------------------------------------------------------- | |
351 | * TMCNTSC - Time Counter Status and Control 4-40 | |
352 | *----------------------------------------------------------------------- | |
353 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
354 | * and enable Time Counter | |
355 | */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) |
e2211743 WD |
357 | |
358 | /*----------------------------------------------------------------------- | |
359 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
360 | *----------------------------------------------------------------------- | |
361 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
362 | * Periodic timer | |
363 | */ | |
6d0f6bcf | 364 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
e2211743 WD |
365 | |
366 | /*----------------------------------------------------------------------- | |
367 | * SCCR - System Clock Control 9-8 | |
368 | *----------------------------------------------------------------------- | |
369 | */ | |
6d0f6bcf | 370 | #define CONFIG_SYS_SCCR 0x00000000 |
e2211743 WD |
371 | |
372 | /*----------------------------------------------------------------------- | |
373 | * RCCR - RISC Controller Configuration 13-7 | |
374 | *----------------------------------------------------------------------- | |
375 | */ | |
6d0f6bcf | 376 | #define CONFIG_SYS_RCCR 0 |
e2211743 WD |
377 | |
378 | /* | |
379 | * Init Memory Controller: | |
380 | */ | |
381 | ||
6d0f6bcf JCPV |
382 | #define CONFIG_SYS_PSDMR 0x494D2452 |
383 | #define CONFIG_SYS_LSDMR 0x49492552 | |
e2211743 WD |
384 | |
385 | /* Flash */ | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V) |
387 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ | |
e2211743 WD |
388 | ORxG_BCTLD | \ |
389 | ORxG_SCY_5_CLK) | |
390 | ||
391 | /* DPRAM to the PCI BUS on the protocol board */ | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) |
393 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ | |
e2211743 WD |
394 | ORxG_ACS_DIV4) |
395 | ||
396 | /* 60x Bus SDRAM */ | |
6d0f6bcf JCPV |
397 | #define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) |
398 | #define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ | |
e2211743 WD |
399 | ORxS_BPD_4 | \ |
400 | ORxS_ROWST_PBI1_A2 | \ | |
401 | ORxS_NUMR_13 | \ | |
402 | ORxS_IBID) | |
403 | ||
404 | /* Virtex-FPGA - Register */ | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) |
406 | #define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ | |
8bde7f77 WD |
407 | ORxG_SCY_1_CLK | \ |
408 | ORxG_ACS_DIV2 | \ | |
409 | ORxG_CSNT ) | |
e2211743 WD |
410 | |
411 | /* local bus SDRAM */ | |
6d0f6bcf JCPV |
412 | #define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) |
413 | #define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ | |
e2211743 WD |
414 | ORxS_BPD_4 | \ |
415 | ORxS_ROWST_PBI1_A4 | \ | |
416 | ORxS_NUMR_13) | |
417 | ||
418 | /* DPRAM to the Sharc-Bus on the protocol board */ | |
6d0f6bcf JCPV |
419 | #define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) |
420 | #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ | |
e2211743 WD |
421 | ORxG_ACS_DIV4) |
422 | ||
e2211743 | 423 | #endif /* __CONFIG_H */ |