[people/ms/u-boot.git] / include / configs / rsk7269.h

/*
 * Configuation settings for the Renesas RSK2+SH7269 board
 *
 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
 * Copyright (C) 2012 Phil Edworthy
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __RSK7269_H
#define __RSK7269_H

#define CONFIG_CPU_SH7269	1

#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }

#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
#define CONFIG_SYS_PBSIZE	256	/* Print Buffer Size */

/* Serial */
#define CONFIG_CONS_SCIF7

/* Memory */
/* u-boot relocated to top 256KB of ram */
#define CONFIG_SYS_TEXT_BASE		0x0DFC0000
#define CONFIG_SYS_SDRAM_BASE		0x0C000000
#define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4*1024*1024)

/* NOR Flash */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BASE		0x20000000 /* Non-cached */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	512

#define CONFIG_ENV_OFFSET	(128 * 1024)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	66125000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)

#endif	/* __RSK7269_H */
Commit	Line	Data
99744b7e PE	1	/*
	2	* Configuation settings for the Renesas RSK2+SH7269 board
	3	*
	4	* Copyright (C) 2012 Renesas Electronics Europe Ltd.
	5	* Copyright (C) 2012 Phil Edworthy
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
99744b7e PE	8	*/
	9
	10	#ifndef __RSK7269_H
	11	#define __RSK7269_H
	12
99744b7e	13	#define CONFIG_CPU_SH7269 1
99744b7e	14
18a40e84 VZ	15	#define CONFIG_DISPLAY_BOARDINFO
18a40e84 VZ	16
99744b7e PE	17	#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	18
	19	#define CONFIG_SYS_LONGHELP /* undef to save memory */
99744b7e	20	#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
99744b7e PE	21
99744b7e PE	22	/* Serial */
99744b7e PE	23	#define CONFIG_CONS_SCIF7
	24
	25	/* Memory */
	26	/* u-boot relocated to top 256KB of ram */
	27	#define CONFIG_SYS_TEXT_BASE 0x0DFC0000
	28	#define CONFIG_SYS_SDRAM_BASE 0x0C000000
	29	#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
	30
	31	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	32	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
	33	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
	34	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	35	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 410241024)
	36
	37	/* NOR Flash */
	38	#define CONFIG_FLASH_CFI_DRIVER
	39	#define CONFIG_SYS_FLASH_CFI
	40	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	41	#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
	42	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	43	#define CONFIG_SYS_MAX_FLASH_SECT 512
	44
99744b7e PE	45	#define CONFIG_ENV_OFFSET (128 * 1024)
	46	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	47	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	48	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	49
	50	/* Board Clock */
	51	#define CONFIG_SYS_CLK_FREQ 66125000
684a501e NI	52	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	53	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
99744b7e	54	#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
8f0960e8	55	#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
99744b7e	56
99744b7e	57	#endif /* __RSK7269_H */