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c0dcece7 HS |
1 | /* |
2 | * siemens rut | |
3 | * (C) Copyright 2013 Siemens Schweiz AG | |
4 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
5 | * | |
6 | * Based on: | |
7 | * U-Boot file:/include/configs/am335x_evm.h | |
8 | * | |
9 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
10 | * | |
11 | * SPDX-License-Identifier: GPL-2.0+ | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_RUT_H | |
15 | #define __CONFIG_RUT_H | |
16 | ||
17 | #define CONFIG_SIEMENS_RUT | |
18 | #define MACH_TYPE_RUT 4316 | |
19 | #define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT | |
20 | ||
21 | #include "siemens-am33x-common.h" | |
22 | ||
23 | #define CONFIG_SYS_MPUCLK 600 | |
24 | #define RUT_IOCTRL_VAL 0x18b | |
25 | #define DDR_PLL_FREQ 303 | |
26 | ||
27 | /* Physical Memory Map */ | |
28 | #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ | |
29 | ||
30 | /* I2C Configuration */ | |
31 | #define CONFIG_SYS_I2C_SPEED 100000 | |
32 | ||
33 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
34 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
35 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
36 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
37 | ||
38 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 | |
39 | ||
40 | #undef CONFIG_SPL_NET_SUPPORT | |
41 | #undef CONFIG_SPL_NET_VCI_STRING | |
42 | #undef CONFIG_SPL_ETH_SUPPORT | |
43 | ||
c0dcece7 HS |
44 | #define CONFIG_PHY_NATSEMI |
45 | ||
46 | #define CONFIG_FACTORYSET | |
47 | ||
48 | /* UBI Support */ | |
49 | #ifndef CONFIG_SPL_BUILD | |
50 | #define CONFIG_CMD_MTDPARTS | |
51 | #define CONFIG_MTD_PARTITIONS | |
52 | #define CONFIG_MTD_DEVICE | |
53 | #define CONFIG_RBTREE | |
54 | #define CONFIG_LZO | |
55 | #define CONFIG_CMD_UBI | |
56 | #define CONFIG_CMD_UBIFS | |
57 | #endif | |
58 | ||
59 | /* Watchdog */ | |
60 | #define WATCHDOG_TRIGGER_GPIO 14 | |
61 | ||
62 | #ifndef CONFIG_SPL_BUILD | |
63 | ||
64 | /* Default env settings */ | |
65 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
66 | "hostname=rut\0" \ | |
56eb3da4 SE |
67 | "nand_img_size=0x500000\0" \ |
68 | "splashpos=m,m\0" \ | |
c0dcece7 HS |
69 | "optargs=fixrtc --no-log consoleblank=0 \0" \ |
70 | CONFIG_COMMON_ENV_SETTINGS \ | |
71 | "mmc_dev=0\0" \ | |
72 | "mmc_root=/dev/mmcblk0p2 rw\0" \ | |
73 | "mmc_root_fs_type=ext4 rootwait\0" \ | |
74 | "mmc_load_uimage=" \ | |
75 | "mmc rescan; " \ | |
76 | "setenv bootfile uImage;" \ | |
77 | "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ | |
78 | "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ | |
79 | "importbootenv=echo Importing environment from mmc ...; " \ | |
80 | "env import -t $loadaddr $filesize\0" \ | |
81 | "mmc_args=run bootargs_defaults;" \ | |
82 | "mtdparts default;" \ | |
83 | "setenv bootargs ${bootargs} " \ | |
84 | "root=${mmc_root} ${mtdparts}" \ | |
85 | "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ | |
86 | "eth=${ethaddr} " \ | |
87 | "\0" \ | |
88 | "mmc_boot=run mmc_args; " \ | |
89 | "run mmc_load_uimage; " \ | |
90 | "bootm ${kloadaddr}\0" \ | |
91 | "" | |
92 | ||
93 | #ifndef CONFIG_RESTORE_FLASH | |
94 | /* set to negative value for no autoboot */ | |
95 | #define CONFIG_BOOTDELAY 3 | |
96 | ||
97 | #define CONFIG_BOOTCOMMAND \ | |
98 | "if mmc rescan; then " \ | |
99 | "echo SD/MMC found on device ${mmc_dev};" \ | |
100 | "if run loadbootenv; then " \ | |
101 | "echo Loaded environment from ${bootenv};" \ | |
102 | "run importbootenv;" \ | |
103 | "fi;" \ | |
104 | "if test -n $uenvcmd; then " \ | |
105 | "echo Running uenvcmd ...;" \ | |
106 | "run uenvcmd;" \ | |
107 | "fi;" \ | |
108 | "if run mmc_load_uimage; then " \ | |
109 | "run mmc_args;" \ | |
110 | "bootm ${kloadaddr};" \ | |
111 | "fi;" \ | |
112 | "fi;" \ | |
113 | "run nand_boot;" \ | |
56eb3da4 | 114 | "reset;" |
c0dcece7 HS |
115 | |
116 | #else | |
117 | #define CONFIG_BOOTDELAY 0 | |
118 | ||
119 | #define CONFIG_BOOTCOMMAND \ | |
120 | "setenv autoload no; " \ | |
121 | "dhcp; " \ | |
122 | "if tftp 80000000 debrick.scr; then " \ | |
123 | "source 80000000; " \ | |
124 | "fi" | |
125 | #endif | |
126 | ||
127 | #endif /* CONFIG_SPL_BUILD */ | |
128 | ||
129 | #ifdef CONFIG_SPL_BUILD | |
130 | #undef CONFIG_HW_WATCHDOG | |
131 | #endif | |
132 | ||
133 | #define CONFIG_VIDEO | |
134 | #if defined(CONFIG_VIDEO) | |
135 | #define CONFIG_VIDEO_DA8XX | |
136 | #define CONFIG_CFB_CONSOLE | |
137 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
138 | #define CONFIG_SPLASH_SCREEN | |
139 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
140 | #define CONFIG_VIDEO_LOGO | |
141 | #define CONFIG_VIDEO_BMP_RLE8 | |
142 | #define CONFIG_VIDEO_BMP_LOGO | |
143 | #define CONFIG_CMD_BMP | |
144 | #define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE | |
145 | ||
146 | #define CONFIG_SPI | |
147 | #define CONFIG_OMAP3_SPI | |
148 | ||
149 | #define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ | |
150 | #define CONFIG_ARCH_EARLY_INIT_R | |
151 | #define CONFIG_FORMIKE | |
56eb3da4 SE |
152 | #define DISPL_PLL_SPREAD_SPECTRUM |
153 | #define CONFIG_SYS_CONSOLE_BG_COL 0xff | |
154 | #define CONFIG_SYS_CONSOLE_FG_COL 0x00 | |
c0dcece7 HS |
155 | #endif |
156 | ||
0c331ebc HS |
157 | #ifndef CONFIG_SPL_BUILD |
158 | #define CONFIG_FIT | |
159 | #endif | |
160 | ||
c0dcece7 | 161 | #endif /* ! __CONFIG_RUT_H */ |