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2c1e11dd AY |
1 | /* |
2 | * (C) Copyright 2016 Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | #ifndef __CONFIG_RV1108_COMMON_H | |
7 | #define __CONFIG_RV1108_COMMON_H | |
8 | ||
9 | #include <asm/arch/hardware.h> | |
10 | #include "rockchip-common.h" | |
11 | ||
2c1e11dd AY |
12 | #define CONFIG_SYS_MALLOC_LEN (32 << 20) |
13 | #define CONFIG_SYS_CBSIZE 1024 | |
14 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
15 | ||
16 | #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) | |
17 | /* TIMER1,initialized by ddr initialize code */ | |
18 | #define CONFIG_SYS_TIMER_BASE 0x10350020 | |
19 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) | |
20 | ||
21 | #define CONFIG_SYS_NS16550 | |
22 | #define CONFIG_SYS_NS16550_MEM32 | |
23 | ||
24 | #define CONFIG_SYS_SDRAM_BASE 0x60000000 | |
25 | #define CONFIG_NR_DRAM_BANKS 1 | |
2c1e11dd AY |
26 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) |
27 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) | |
28 | ||
cbeedafd WW |
29 | /* rockchip ohci host driver */ |
30 | #define CONFIG_USB_OHCI_NEW | |
31 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 | |
2c1e11dd | 32 | #endif |