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fe8c2806 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
4 | * | |
5 | * (C) Copyright 2000 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright 2001 | |
10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
12 | * | |
b30d41ca | 13 | * Configuration settings for the SACSng 8260 board. |
fe8c2806 WD |
14 | * |
15 | * See file CREDITS for list of people who contributed to this | |
16 | * project. | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License as | |
20 | * published by the Free Software Foundation; either version 2 of | |
21 | * the License, or (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
31 | * MA 02111-1307 USA | |
32 | */ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
2ae18241 WD |
37 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
38 | ||
fe8c2806 WD |
39 | #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ |
40 | ||
78137c3c WD |
41 | #undef CONFIG_LOGBUFFER /* External logbuffer support */ |
42 | ||
fe8c2806 WD |
43 | /***************************************************************************** |
44 | * | |
45 | * These settings must match the way _your_ board is set up | |
46 | * | |
47 | *****************************************************************************/ | |
48 | ||
49 | /* What is the oscillator's (UX2) frequency in Hz? */ | |
50 | #define CONFIG_8260_CLKIN 66666600 | |
51 | ||
52 | /*----------------------------------------------------------------------- | |
53 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
54 | *----------------------------------------------------------------------- | |
55 | * What should MODCK_H be? It is dependent on the oscillator | |
56 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
57 | * Here are some example values (all frequencies are in MHz): | |
58 | * | |
59 | * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 | |
60 | * ------- ---------- --- --- ---- ----- ----- ----- | |
61 | * 0x1 0x5 33 100 133 Open Close Open | |
62 | * 0x1 0x6 33 100 166 Open Open Close | |
63 | * 0x1 0x7 33 100 200 Open Open Open | |
64 | * | |
65 | * 0x2 0x2 33 133 133 Close Open Close | |
66 | * 0x2 0x3 33 133 166 Close Open Open | |
67 | * 0x2 0x4 33 133 200 Open Close Close | |
68 | * 0x2 0x5 33 133 233 Open Close Open | |
69 | * 0x2 0x6 33 133 266 Open Open Close | |
70 | * | |
71 | * 0x5 0x5 66 133 133 Open Close Open | |
72 | * 0x5 0x6 66 133 166 Open Open Close | |
73 | * 0x5 0x7 66 133 200 Open Open Open | |
74 | * 0x6 0x0 66 133 233 Close Close Close | |
75 | * 0x6 0x1 66 133 266 Close Close Open | |
76 | * 0x6 0x2 66 133 300 Close Open Close | |
77 | */ | |
6d0f6bcf | 78 | #define CONFIG_SYS_SBC_MODCK_H 0x05 |
fe8c2806 WD |
79 | |
80 | /* Define this if you want to boot from 0x00000100. If you don't define | |
81 | * this, you will need to program the bootloader to 0xfff00000, and | |
82 | * get the hardware reset config words at 0xfe000000. The simplest | |
83 | * way to do that is to program the bootloader at both addresses. | |
84 | * It is suggested that you just let U-Boot live at 0x00000000. | |
85 | */ | |
6d0f6bcf | 86 | #define CONFIG_SYS_SBC_BOOT_LOW 1 |
fe8c2806 WD |
87 | |
88 | /* What should the base address of the main FLASH be and how big is | |
14d0a02a | 89 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk |
fe8c2806 WD |
90 | * The main FLASH is whichever is connected to *CS0. |
91 | */ | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
93 | #define CONFIG_SYS_FLASH0_SIZE 2 | |
fe8c2806 WD |
94 | |
95 | /* What should the base address of the secondary FLASH be and how big | |
96 | * is it (in Mbytes)? The secondary FLASH is whichever is connected | |
97 | * to *CS6. | |
98 | */ | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_FLASH1_BASE 0x60000000 |
100 | #define CONFIG_SYS_FLASH1_SIZE 2 | |
fe8c2806 WD |
101 | |
102 | /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes | |
103 | */ | |
104 | #define CONFIG_VERY_BIG_RAM 1 | |
105 | ||
106 | /* What should be the base address of SDRAM DIMM and how big is | |
107 | * it (in Mbytes)? This will normally auto-configure via the SPD. | |
108 | */ | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_SDRAM0_BASE 0x00000000 |
110 | #define CONFIG_SYS_SDRAM0_SIZE 64 | |
fe8c2806 WD |
111 | |
112 | /* | |
113 | * Memory map example with 64 MB DIMM: | |
114 | * | |
115 | * 0x0000 0000 Exception Vector code, 8k | |
116 | * : | |
117 | * 0x0000 1FFF | |
118 | * 0x0000 2000 Free for Application Use | |
119 | * : | |
120 | * : | |
121 | * | |
122 | * : | |
123 | * : | |
124 | * 0x03F5 FF30 Monitor Stack (Growing downward) | |
125 | * Monitor Stack Buffer (0x80) | |
126 | * 0x03F5 FFB0 Board Info Data | |
127 | * 0x03F6 0000 Malloc Arena | |
0e8d1586 | 128 | * : CONFIG_ENV_SECT_SIZE, 16k |
6d0f6bcf | 129 | * : CONFIG_SYS_MALLOC_LEN, 128k |
fe8c2806 | 130 | * 0x03FC 0000 RAM Copy of Monitor Code |
6d0f6bcf JCPV |
131 | * : CONFIG_SYS_MONITOR_LEN, 256k |
132 | * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 | |
fe8c2806 WD |
133 | */ |
134 | ||
6d0f6bcf JCPV |
135 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
136 | CONFIG_SYS_POST_CPU) | |
fe8c2806 WD |
137 | |
138 | ||
139 | /* | |
140 | * select serial console configuration | |
141 | * | |
142 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
143 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
144 | * for SCC). | |
145 | * | |
146 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
147 | * defined elsewhere. | |
148 | */ | |
149 | #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ | |
150 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
151 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
152 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
153 | ||
154 | /* | |
155 | * select ethernet configuration | |
156 | * | |
157 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
158 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
159 | * for FCC) | |
160 | * | |
161 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 162 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
fe8c2806 WD |
163 | */ |
164 | ||
165 | #undef CONFIG_ETHER_ON_SCC | |
166 | #define CONFIG_ETHER_ON_FCC | |
167 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
168 | ||
169 | #ifdef CONFIG_ETHER_ON_SCC | |
170 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
171 | #endif /* CONFIG_ETHER_ON_SCC */ | |
172 | ||
173 | #ifdef CONFIG_ETHER_ON_FCC | |
174 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
78137c3c | 175 | #undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ |
fe8c2806 WD |
176 | #define CONFIG_MII /* MII PHY management */ |
177 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
178 | /* | |
179 | * Port pins used for bit-banged MII communictions (if applicable). | |
180 | */ | |
181 | ||
182 | #define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ | |
be225442 LCM |
183 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
184 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
185 | #define MDC_DECLARE MDIO_DECLARE | |
186 | ||
fe8c2806 WD |
187 | #define MDIO_ACTIVE (iop->pdir |= 0x40000000) |
188 | #define MDIO_TRISTATE (iop->pdir &= ~0x40000000) | |
189 | #define MDIO_READ ((iop->pdat & 0x40000000) != 0) | |
190 | ||
191 | #define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \ | |
192 | else iop->pdat &= ~0x40000000 | |
193 | ||
194 | #define MDC(bit) if(bit) iop->pdat |= 0x80000000; \ | |
195 | else iop->pdat &= ~0x80000000 | |
196 | ||
197 | #define MIIDELAY udelay(50) | |
198 | #endif /* CONFIG_ETHER_ON_FCC */ | |
199 | ||
200 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
201 | ||
202 | /* | |
203 | * - RX clk is CLK11 | |
204 | * - TX clk is CLK12 | |
205 | */ | |
d4590da4 | 206 | # define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
fe8c2806 WD |
207 | |
208 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
209 | ||
210 | /* | |
211 | * - Rx-CLK is CLK13 | |
212 | * - Tx-CLK is CLK14 | |
213 | * - Select bus for bd/buffers (see 28-13) | |
214 | * - Enable Full Duplex in FSMR | |
215 | */ | |
d4590da4 MF |
216 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
217 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
6d0f6bcf JCPV |
218 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
219 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
fe8c2806 WD |
220 | |
221 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
222 | ||
223 | #define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */ | |
224 | ||
225 | /* | |
226 | * Configure for RAM tests. | |
227 | */ | |
6d0f6bcf | 228 | #undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */ |
fe8c2806 WD |
229 | |
230 | ||
231 | /* | |
232 | * Status LED for power up status feedback. | |
233 | */ | |
234 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
235 | ||
236 | #define STATUS_LED_PAR im_ioport.iop_ppara | |
237 | #define STATUS_LED_DIR im_ioport.iop_pdira | |
238 | #define STATUS_LED_ODR im_ioport.iop_podra | |
239 | #define STATUS_LED_DAT im_ioport.iop_pdata | |
240 | ||
241 | #define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */ | |
6d0f6bcf | 242 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ) |
fe8c2806 WD |
243 | #define STATUS_LED_STATE STATUS_LED_OFF |
244 | #define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */ | |
6d0f6bcf | 245 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) |
fe8c2806 WD |
246 | #define STATUS_LED_STATE1 STATUS_LED_OFF |
247 | #define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */ | |
6d0f6bcf | 248 | #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2) |
fe8c2806 WD |
249 | #define STATUS_LED_STATE2 STATUS_LED_ON |
250 | ||
251 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
252 | ||
253 | #define STATUS_LED_YELLOW 0 | |
254 | #define STATUS_LED_GREEN 1 | |
255 | #define STATUS_LED_RED 2 | |
256 | #define STATUS_LED_BOOT 1 | |
257 | ||
258 | ||
259 | /* | |
1d0350ed | 260 | * Select SPI support configuration |
fe8c2806 | 261 | */ |
1d0350ed WD |
262 | #define CONFIG_SOFT_SPI /* Enable SPI driver */ |
263 | #define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */ | |
8bde7f77 WD |
264 | #undef DEBUG_SPI /* Disable SPI debugging */ |
265 | ||
fe8c2806 WD |
266 | /* |
267 | * Software (bit-bang) SPI driver configuration | |
268 | */ | |
269 | #ifdef CONFIG_SOFT_SPI | |
270 | ||
271 | /* | |
272 | * Software (bit-bang) SPI driver configuration | |
273 | */ | |
274 | #define I2C_SCLK 0x00002000 /* PD 18: Shift clock */ | |
275 | #define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */ | |
276 | #define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */ | |
277 | ||
278 | #undef SPI_INIT /* no port initialization needed */ | |
279 | #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) | |
ced209c5 WD |
280 | #define SPI_SDA(bit) do { \ |
281 | if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ | |
282 | else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \ | |
283 | } while (0) | |
284 | #define SPI_SCL(bit) do { \ | |
285 | if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ | |
286 | else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \ | |
287 | } while (0) | |
1d0350ed | 288 | #define SPI_DELAY /* No delay is needed */ |
fe8c2806 WD |
289 | #endif /* CONFIG_SOFT_SPI */ |
290 | ||
291 | ||
292 | /* | |
293 | * select I2C support configuration | |
294 | * | |
295 | * Supported configurations are {none, software, hardware} drivers. | |
296 | * If the software driver is chosen, there are some additional | |
297 | * configuration items that the driver uses to drive the port pins. | |
298 | */ | |
ea818dbb HS |
299 | #define CONFIG_SYS_I2C |
300 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
301 | #define CONFIG_SYS_I2C_SOFT_SPEED 400000 | |
302 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
fe8c2806 WD |
303 | /* |
304 | * Software (bit-bang) I2C driver configuration | |
305 | */ | |
fe8c2806 WD |
306 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
307 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
308 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
309 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
310 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
311 | else iop->pdat &= ~0x00010000 | |
312 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
313 | else iop->pdat &= ~0x00020000 | |
314 | #define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */ | |
fe8c2806 WD |
315 | |
316 | /* Define this to reserve an entire FLASH sector for | |
317 | * environment variables. Otherwise, the environment will be | |
318 | * put in the same sector as U-Boot, and changing variables | |
319 | * will erase U-Boot temporarily | |
320 | */ | |
0e8d1586 | 321 | #define CONFIG_ENV_IN_OWN_SECT 1 |
fe8c2806 WD |
322 | |
323 | /* Define this to contain any number of null terminated strings that | |
324 | * will be part of the default enviroment compiled into the boot image. | |
325 | */ | |
326 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
78137c3c WD |
327 | "quiet=0\0" \ |
328 | "serverip=192.168.123.205\0" \ | |
fe8c2806 WD |
329 | "ipaddr=192.168.123.203\0" \ |
330 | "checkhostname=VR8500\0" \ | |
331 | "reprog="\ | |
78137c3c | 332 | "bootp; " \ |
fe8c2806 WD |
333 | "tftpboot 0x140000 /bdi2000/u-boot.bin; " \ |
334 | "protect off 60000000 6003FFFF; " \ | |
335 | "erase 60000000 6003FFFF; " \ | |
fe126d8b | 336 | "cp.b 140000 60000000 ${filesize}; " \ |
fe8c2806 WD |
337 | "protect on 60000000 6003FFFF\0" \ |
338 | "copyenv="\ | |
339 | "protect off 60040000 6004FFFF; " \ | |
340 | "erase 60040000 6004FFFF; " \ | |
341 | "cp.b 40040000 60040000 10000; " \ | |
342 | "protect on 60040000 6004FFFF\0" \ | |
343 | "copyprog="\ | |
344 | "protect off 60000000 6003FFFF; " \ | |
345 | "erase 60000000 6003FFFF; " \ | |
346 | "cp.b 40000000 60000000 40000; " \ | |
347 | "protect on 60000000 6003FFFF\0" \ | |
348 | "zapenv="\ | |
349 | "protect off 40040000 4004FFFF; " \ | |
350 | "erase 40040000 4004FFFF; " \ | |
351 | "protect on 40040000 4004FFFF\0" \ | |
352 | "zapotherenv="\ | |
353 | "protect off 60040000 6004FFFF; " \ | |
354 | "erase 60040000 6004FFFF; " \ | |
355 | "protect on 60040000 6004FFFF\0" \ | |
356 | "root-on-initrd="\ | |
357 | "setenv bootcmd "\ | |
358 | "version\\;" \ | |
359 | "echo\\;" \ | |
360 | "bootp\\;" \ | |
361 | "setenv bootargs root=/dev/ram0 rw quiet " \ | |
fe126d8b | 362 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ |
fe8c2806 WD |
363 | "run boot-hook\\;" \ |
364 | "bootm\0" \ | |
365 | "root-on-initrd-debug="\ | |
366 | "setenv bootcmd "\ | |
367 | "version\\;" \ | |
368 | "echo\\;" \ | |
369 | "bootp\\;" \ | |
370 | "setenv bootargs root=/dev/ram0 rw debug " \ | |
fe126d8b | 371 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ |
fe8c2806 WD |
372 | "run debug-hook\\;" \ |
373 | "run boot-hook\\;" \ | |
374 | "bootm\0" \ | |
375 | "root-on-nfs="\ | |
376 | "setenv bootcmd "\ | |
377 | "version\\;" \ | |
378 | "echo\\;" \ | |
379 | "bootp\\;" \ | |
380 | "setenv bootargs root=/dev/nfs rw quiet " \ | |
fe126d8b WD |
381 | "nfsroot=\\${serverip}:\\${rootpath} " \ |
382 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ | |
fe8c2806 WD |
383 | "run boot-hook\\;" \ |
384 | "bootm\0" \ | |
385 | "root-on-nfs-debug="\ | |
386 | "setenv bootcmd "\ | |
387 | "version\\;" \ | |
388 | "echo\\;" \ | |
389 | "bootp\\;" \ | |
390 | "setenv bootargs root=/dev/nfs rw debug " \ | |
fe126d8b WD |
391 | "nfsroot=\\${serverip}:\\${rootpath} " \ |
392 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ | |
fe8c2806 WD |
393 | "run debug-hook\\;" \ |
394 | "run boot-hook\\;" \ | |
395 | "bootm\0" \ | |
396 | "debug-checkout="\ | |
397 | "setenv checkhostname;" \ | |
398 | "setenv ethaddr 00:09:70:00:00:01;" \ | |
399 | "bootp;" \ | |
fe126d8b WD |
400 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \ |
401 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
fe8c2806 WD |
402 | "run debug-hook;" \ |
403 | "run boot-hook;" \ | |
404 | "bootm\0" \ | |
405 | "debug-hook="\ | |
fe126d8b WD |
406 | "echo ipaddr ${ipaddr};" \ |
407 | "echo serverip ${serverip};" \ | |
408 | "echo gatewayip ${gatewayip};" \ | |
409 | "echo netmask ${netmask};" \ | |
410 | "echo hostname ${hostname}\0" \ | |
fe8c2806 WD |
411 | "ana=run adc ; run dac\0" \ |
412 | "adc=run adc-12 ; run adc-34\0" \ | |
0f89c54b PT |
413 | "adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \ |
414 | "adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \ | |
415 | "dac=echo ### DAC ; i2c md 11 81 5\0" \ | |
78137c3c | 416 | "boot-hook=echo\0" |
fe8c2806 WD |
417 | |
418 | /* What should the console's baud rate be? */ | |
419 | #define CONFIG_BAUDRATE 9600 | |
420 | ||
421 | /* Ethernet MAC address */ | |
422 | #define CONFIG_ETHADDR 00:09:70:00:00:00 | |
423 | ||
424 | /* The default Ethernet MAC address can be overwritten just once */ | |
425 | #ifdef CONFIG_ETHADDR | |
426 | #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 | |
427 | #endif | |
428 | ||
429 | /* | |
430 | * Define this to do some miscellaneous board-specific initialization. | |
431 | */ | |
432 | #define CONFIG_MISC_INIT_R | |
433 | ||
434 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
435 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ | |
436 | ||
437 | /* Be selective on what keys can delay or stop the autoboot process | |
438 | * To stop use: " " | |
439 | */ | |
440 | #define CONFIG_AUTOBOOT_KEYED | |
f2302d44 | 441 | #define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" |
fe8c2806 WD |
442 | #define CONFIG_AUTOBOOT_STOP_STR " " |
443 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
444 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
445 | #define DEBUG_BOOTKEYS 0 | |
446 | ||
447 | /* Define a command string that is automatically executed when no character | |
448 | * is read on the console interface withing "Boot Delay" after reset. | |
449 | */ | |
53677ef1 | 450 | #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ |
b79a11cc | 451 | #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ |
fe8c2806 | 452 | |
42dfe7a1 | 453 | #ifdef CONFIG_BOOT_ROOT_INITRD |
fe8c2806 WD |
454 | #define CONFIG_BOOTCOMMAND \ |
455 | "version;" \ | |
456 | "echo;" \ | |
457 | "bootp;" \ | |
458 | "setenv bootargs root=/dev/ram0 rw quiet " \ | |
fe126d8b | 459 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
fe8c2806 WD |
460 | "run boot-hook;" \ |
461 | "bootm" | |
462 | #endif /* CONFIG_BOOT_ROOT_INITRD */ | |
463 | ||
42dfe7a1 | 464 | #ifdef CONFIG_BOOT_ROOT_NFS |
fe8c2806 WD |
465 | #define CONFIG_BOOTCOMMAND \ |
466 | "version;" \ | |
467 | "echo;" \ | |
468 | "bootp;" \ | |
fe126d8b WD |
469 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \ |
470 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
fe8c2806 WD |
471 | "run boot-hook;" \ |
472 | "bootm" | |
473 | #endif /* CONFIG_BOOT_ROOT_NFS */ | |
474 | ||
475 | #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ | |
476 | ||
d3b8c1a7 JL |
477 | /* |
478 | * BOOTP options | |
fe8c2806 | 479 | */ |
d3b8c1a7 JL |
480 | #define CONFIG_BOOTP_SUBNETMASK |
481 | #define CONFIG_BOOTP_GATEWAY | |
482 | #define CONFIG_BOOTP_HOSTNAME | |
483 | #define CONFIG_BOOTP_BOOTPATH | |
484 | #define CONFIG_BOOTP_BOOTFILESIZE | |
485 | #define CONFIG_BOOTP_DNS | |
486 | #define CONFIG_BOOTP_DNS2 | |
487 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
488 | ||
fe8c2806 WD |
489 | |
490 | /* undef this to save memory */ | |
6d0f6bcf | 491 | #define CONFIG_SYS_LONGHELP |
fe8c2806 WD |
492 | |
493 | /* Monitor Command Prompt */ | |
6d0f6bcf | 494 | #define CONFIG_SYS_PROMPT "=> " |
fe8c2806 | 495 | |
6d0f6bcf JCPV |
496 | #undef CONFIG_SYS_HUSH_PARSER |
497 | #ifdef CONFIG_SYS_HUSH_PARSER | |
fe8c2806 WD |
498 | #endif |
499 | ||
1d0350ed WD |
500 | /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) |
501 | * of an image is printed by image commands like bootm or iminfo. | |
502 | */ | |
503 | #define CONFIG_TIMESTAMP | |
504 | ||
42d1f039 | 505 | /* If this variable is defined, an environment variable named "ver" |
78137c3c WD |
506 | * is created by U-Boot showing the U-Boot version. |
507 | */ | |
508 | #define CONFIG_VERSION_VARIABLE | |
509 | ||
46da1e96 JL |
510 | |
511 | /* | |
512 | * Command line configuration. | |
513 | */ | |
514 | #include <config_cmd_default.h> | |
515 | ||
516 | #define CONFIG_CMD_ELF | |
517 | #define CONFIG_CMD_ASKENV | |
518 | #define CONFIG_CMD_I2C | |
519 | #define CONFIG_CMD_SPI | |
520 | #define CONFIG_CMD_SDRAM | |
521 | #define CONFIG_CMD_REGINFO | |
522 | #define CONFIG_CMD_IMMAP | |
523 | #define CONFIG_CMD_IRQ | |
524 | #define CONFIG_CMD_PING | |
525 | ||
526 | #undef CONFIG_CMD_KGDB | |
527 | ||
fe8c2806 | 528 | #ifdef CONFIG_ETHER_ON_FCC |
46da1e96 JL |
529 | #define CONFIG_CMD_MII |
530 | #endif | |
531 | ||
fe8c2806 WD |
532 | |
533 | /* Where do the internal registers live? */ | |
6d0f6bcf | 534 | #define CONFIG_SYS_IMMR 0xF0000000 |
fe8c2806 | 535 | |
78137c3c WD |
536 | #undef CONFIG_WATCHDOG /* disable the watchdog */ |
537 | ||
fe8c2806 WD |
538 | /***************************************************************************** |
539 | * | |
540 | * You should not have to modify any of the following settings | |
541 | * | |
542 | *****************************************************************************/ | |
543 | ||
544 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
fe8c2806 | 545 | #define CONFIG_SACSng 1 /* munged for the SACSng */ |
9c4c5ae3 | 546 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
fe8c2806 | 547 | |
fe8c2806 WD |
548 | /* |
549 | * Miscellaneous configurable options | |
550 | */ | |
6d0f6bcf | 551 | #define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */ |
42d1f039 | 552 | /* in the bootm command. */ |
6d0f6bcf | 553 | #define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */ |
42d1f039 | 554 | /* "## <message>" from the bootm cmd */ |
6d0f6bcf | 555 | #define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */ |
42d1f039 WD |
556 | /* defined, then the hostname param */ |
557 | /* validated against checkhostname. */ | |
6d0f6bcf JCPV |
558 | #define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */ |
559 | #define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */ | |
42d1f039 | 560 | /* (limited to maximum of 1024 msec) */ |
6d0f6bcf | 561 | #define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1 |
42d1f039 WD |
562 | /* Check for abort key presses */ |
563 | /* at least once in dependent of the */ | |
564 | /* CONFIG_BOOTDELAY value. */ | |
6d0f6bcf JCPV |
565 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */ |
566 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */ | |
42d1f039 | 567 | /* state to the fault LED. */ |
6d0f6bcf | 568 | #define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */ |
42d1f039 | 569 | /* the Ethernet link state. */ |
6d0f6bcf | 570 | #define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */ |
42d1f039 | 571 | /* until the TFTP is successful. */ |
6d0f6bcf | 572 | #define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */ |
42d1f039 | 573 | /* turn off the STATUS LEDs. */ |
6d0f6bcf | 574 | #define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */ |
42d1f039 | 575 | /* incoming data. */ |
6d0f6bcf | 576 | #define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */ |
42d1f039 | 577 | /* to signify that tftp is moving. */ |
6d0f6bcf | 578 | #define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */ |
42d1f039 | 579 | /* flash the status LED. */ |
6d0f6bcf | 580 | #define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */ |
42d1f039 | 581 | /* during the tftp file transfer. */ |
6d0f6bcf | 582 | #define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */ |
42d1f039 | 583 | /* '#'s from the tftp command. */ |
6d0f6bcf | 584 | #define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */ |
42d1f039 | 585 | /* issued during the tftp command. */ |
6d0f6bcf | 586 | #define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */ |
78137c3c WD |
587 | /* before it gives up. */ |
588 | ||
46da1e96 | 589 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 590 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
fe8c2806 | 591 | #else |
6d0f6bcf | 592 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
fe8c2806 WD |
593 | #endif |
594 | ||
595 | /* Print Buffer Size */ | |
6d0f6bcf | 596 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) |
fe8c2806 | 597 | |
6d0f6bcf | 598 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
fe8c2806 | 599 | |
6d0f6bcf | 600 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
fe8c2806 | 601 | |
6d0f6bcf JCPV |
602 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
603 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
fe8c2806 | 604 | |
6d0f6bcf JCPV |
605 | #define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */ |
606 | #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ | |
fe8c2806 WD |
607 | /* the exception vector table */ |
608 | /* to the end of the DRAM */ | |
609 | /* less monitor and malloc area */ | |
6d0f6bcf JCPV |
610 | #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ |
611 | #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ | |
612 | + CONFIG_SYS_MALLOC_LEN \ | |
0e8d1586 | 613 | + CONFIG_ENV_SECT_SIZE \ |
6d0f6bcf | 614 | + CONFIG_SYS_STACK_USAGE ) |
fe8c2806 | 615 | |
6d0f6bcf JCPV |
616 | #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ |
617 | - CONFIG_SYS_MEM_END_USAGE ) | |
fe8c2806 | 618 | |
fe8c2806 WD |
619 | /* |
620 | * Low Level Configuration Settings | |
621 | * (address mappings, register initial values, etc.) | |
622 | * You should know what you are doing if you make changes here. | |
623 | */ | |
624 | ||
6d0f6bcf JCPV |
625 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE |
626 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE | |
627 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE | |
628 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE | |
fe8c2806 WD |
629 | |
630 | /*----------------------------------------------------------------------- | |
631 | * Hard Reset Configuration Words | |
632 | */ | |
6d0f6bcf JCPV |
633 | #if defined(CONFIG_SYS_SBC_BOOT_LOW) |
634 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
fe8c2806 | 635 | #else |
6d0f6bcf JCPV |
636 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) |
637 | #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ | |
fe8c2806 | 638 | |
6d0f6bcf JCPV |
639 | /* get the HRCW ISB field from CONFIG_SYS_IMMR */ |
640 | #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ | |
641 | ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ | |
642 | ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) | |
fe8c2806 | 643 | |
6d0f6bcf | 644 | #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \ |
fe8c2806 | 645 | HRCW_DPPC11 | \ |
6d0f6bcf | 646 | CONFIG_SYS_SBC_HRCW_IMMR | \ |
fe8c2806 WD |
647 | HRCW_MMR00 | \ |
648 | HRCW_LBPC11 | \ | |
649 | HRCW_APPC10 | \ | |
650 | HRCW_CS10PC00 | \ | |
6d0f6bcf JCPV |
651 | (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ |
652 | CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) | |
fe8c2806 WD |
653 | |
654 | /* no slaves */ | |
6d0f6bcf JCPV |
655 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
656 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
657 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
658 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
659 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
660 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
661 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
fe8c2806 WD |
662 | |
663 | /*----------------------------------------------------------------------- | |
664 | * Definitions for initial stack pointer and data area (in DPRAM) | |
665 | */ | |
6d0f6bcf | 666 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 667 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 668 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 669 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
fe8c2806 WD |
670 | |
671 | /*----------------------------------------------------------------------- | |
672 | * Start addresses for the final memory configuration | |
673 | * (Set up by the startup code) | |
6d0f6bcf JCPV |
674 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
675 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. | |
fe8c2806 | 676 | */ |
6d0f6bcf | 677 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE |
fe8c2806 | 678 | |
6d0f6bcf JCPV |
679 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
680 | # define CONFIG_SYS_RAMBOOT | |
fe8c2806 WD |
681 | #endif |
682 | ||
6d0f6bcf JCPV |
683 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
684 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
fe8c2806 WD |
685 | |
686 | /* | |
687 | * For booting Linux, the board info and command line data | |
688 | * have to be in the first 8 MB of memory, since this is | |
689 | * the maximum mapped by the Linux kernel during initialization. | |
690 | */ | |
6d0f6bcf | 691 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
fe8c2806 WD |
692 | |
693 | /*----------------------------------------------------------------------- | |
694 | * FLASH and environment organization | |
695 | */ | |
696 | ||
6d0f6bcf JCPV |
697 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
698 | #undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ | |
699 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
700 | #define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */ | |
fe8c2806 | 701 | |
6d0f6bcf JCPV |
702 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
703 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ | |
fe8c2806 | 704 | |
6d0f6bcf | 705 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 706 | # define CONFIG_ENV_IS_IN_FLASH 1 |
fe8c2806 | 707 | |
0e8d1586 | 708 | # ifdef CONFIG_ENV_IN_OWN_SECT |
6d0f6bcf | 709 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 710 | # define CONFIG_ENV_SECT_SIZE 0x10000 |
fe8c2806 | 711 | # else |
6d0f6bcf | 712 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
713 | # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
714 | # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ | |
715 | # endif /* CONFIG_ENV_IN_OWN_SECT */ | |
fe8c2806 WD |
716 | |
717 | #else | |
9314cee6 | 718 | # define CONFIG_ENV_IS_IN_NVRAM 1 |
6d0f6bcf | 719 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 720 | # define CONFIG_ENV_SIZE 0x200 |
6d0f6bcf | 721 | #endif /* CONFIG_SYS_RAMBOOT */ |
fe8c2806 WD |
722 | |
723 | /*----------------------------------------------------------------------- | |
724 | * Cache Configuration | |
725 | */ | |
6d0f6bcf | 726 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
fe8c2806 | 727 | |
46da1e96 | 728 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 729 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
fe8c2806 WD |
730 | #endif |
731 | ||
732 | /*----------------------------------------------------------------------- | |
733 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
734 | *----------------------------------------------------------------------- | |
735 | * HID0 also contains cache control - initially enable both caches and | |
736 | * invalidate contents, then the final state leaves only the instruction | |
737 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
738 | * but Soft reset does not. | |
739 | * | |
740 | * HID1 has only read-only information - nothing to set. | |
741 | */ | |
6d0f6bcf | 742 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ |
fe8c2806 WD |
743 | HID0_DCE |\ |
744 | HID0_ICFI |\ | |
745 | HID0_DCI |\ | |
746 | HID0_IFEM |\ | |
747 | HID0_ABE) | |
748 | ||
6d0f6bcf | 749 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ |
fe8c2806 WD |
750 | HID0_IFEM |\ |
751 | HID0_ABE |\ | |
752 | HID0_EMCP) | |
6d0f6bcf | 753 | #define CONFIG_SYS_HID2 0 |
fe8c2806 WD |
754 | |
755 | /*----------------------------------------------------------------------- | |
756 | * RMR - Reset Mode Register | |
757 | *----------------------------------------------------------------------- | |
758 | */ | |
6d0f6bcf | 759 | #define CONFIG_SYS_RMR 0 |
fe8c2806 WD |
760 | |
761 | /*----------------------------------------------------------------------- | |
762 | * BCR - Bus Configuration 4-25 | |
763 | *----------------------------------------------------------------------- | |
764 | */ | |
6d0f6bcf | 765 | #define CONFIG_SYS_BCR (BCR_ETM) |
fe8c2806 WD |
766 | |
767 | /*----------------------------------------------------------------------- | |
768 | * SIUMCR - SIU Module Configuration 4-31 | |
769 | *----------------------------------------------------------------------- | |
770 | */ | |
771 | ||
6d0f6bcf | 772 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ |
fe8c2806 WD |
773 | SIUMCR_L2CPC00 |\ |
774 | SIUMCR_APPC10 |\ | |
775 | SIUMCR_MMR00) | |
776 | ||
777 | ||
778 | /*----------------------------------------------------------------------- | |
779 | * SYPCR - System Protection Control 11-9 | |
780 | * SYPCR can only be written once after reset! | |
781 | *----------------------------------------------------------------------- | |
782 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
783 | */ | |
78137c3c | 784 | #if defined(CONFIG_WATCHDOG) |
6d0f6bcf | 785 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
78137c3c WD |
786 | SYPCR_BMT |\ |
787 | SYPCR_PBME |\ | |
788 | SYPCR_LBME |\ | |
789 | SYPCR_SWRI |\ | |
790 | SYPCR_SWP |\ | |
42d1f039 | 791 | SYPCR_SWE) |
78137c3c | 792 | #else |
6d0f6bcf | 793 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
fe8c2806 WD |
794 | SYPCR_BMT |\ |
795 | SYPCR_PBME |\ | |
796 | SYPCR_LBME |\ | |
797 | SYPCR_SWRI |\ | |
798 | SYPCR_SWP) | |
78137c3c | 799 | #endif /* CONFIG_WATCHDOG */ |
fe8c2806 WD |
800 | |
801 | /*----------------------------------------------------------------------- | |
802 | * TMCNTSC - Time Counter Status and Control 4-40 | |
803 | *----------------------------------------------------------------------- | |
804 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
805 | * and enable Time Counter | |
806 | */ | |
6d0f6bcf | 807 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ |
fe8c2806 WD |
808 | TMCNTSC_ALR |\ |
809 | TMCNTSC_TCF |\ | |
810 | TMCNTSC_TCE) | |
811 | ||
812 | /*----------------------------------------------------------------------- | |
813 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
814 | *----------------------------------------------------------------------- | |
815 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
816 | * Periodic timer | |
817 | */ | |
6d0f6bcf | 818 | #define CONFIG_SYS_PISCR (PISCR_PS |\ |
fe8c2806 WD |
819 | PISCR_PTF |\ |
820 | PISCR_PTE) | |
821 | ||
822 | /*----------------------------------------------------------------------- | |
823 | * SCCR - System Clock Control 9-8 | |
824 | *----------------------------------------------------------------------- | |
825 | */ | |
6d0f6bcf | 826 | #define CONFIG_SYS_SCCR 0 |
fe8c2806 WD |
827 | |
828 | /*----------------------------------------------------------------------- | |
829 | * RCCR - RISC Controller Configuration 13-7 | |
830 | *----------------------------------------------------------------------- | |
831 | */ | |
6d0f6bcf | 832 | #define CONFIG_SYS_RCCR 0 |
fe8c2806 WD |
833 | |
834 | /* | |
835 | * Initialize Memory Controller: | |
836 | * | |
837 | * Bank Bus Machine PortSz Device | |
838 | * ---- --- ------- ------ ------ | |
839 | * 0 60x GPCM 16 bit FLASH (primary flash - 2MB) | |
840 | * 1 60x GPCM -- bit (Unused) | |
841 | * 2 60x SDRAM 64 bit SDRAM (DIMM) | |
842 | * 3 60x SDRAM 64 bit SDRAM (DIMM) | |
843 | * 4 60x GPCM -- bit (Unused) | |
844 | * 5 60x GPCM -- bit (Unused) | |
845 | * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB) | |
846 | */ | |
847 | ||
848 | /*----------------------------------------------------------------------- | |
849 | * BR0,BR1 - Base Register | |
850 | * Ref: Section 10.3.1 on page 10-14 | |
851 | * OR0,OR1 - Option Register | |
852 | * Ref: Section 10.3.2 on page 10-18 | |
853 | *----------------------------------------------------------------------- | |
854 | */ | |
855 | ||
856 | /* Bank 0 - Primary FLASH | |
857 | */ | |
858 | ||
859 | /* BR0 is configured as follows: | |
860 | * | |
861 | * - Base address of 0x40000000 | |
862 | * - 16 bit port size | |
863 | * - Data errors checking is disabled | |
864 | * - Read and write access | |
865 | * - GPCM 60x bus | |
866 | * - Access are handled by the memory controller according to MSEL | |
867 | * - Not used for atomic operations | |
868 | * - No data pipelining is done | |
869 | * - Valid | |
870 | */ | |
6d0f6bcf | 871 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
872 | BRx_PS_16 |\ |
873 | BRx_MS_GPCM_P |\ | |
874 | BRx_V) | |
875 | ||
876 | /* OR0 is configured as follows: | |
877 | * | |
878 | * - 4 MB | |
879 | * - *BCTL0 is asserted upon access to the current memory bank | |
880 | * - *CW / *WE are negated a quarter of a clock earlier | |
881 | * - *CS is output at the same time as the address lines | |
882 | * - Uses a clock cycle length of 5 | |
883 | * - *PSDVAL is generated internally by the memory controller | |
884 | * unless *GTA is asserted earlier externally. | |
885 | * - Relaxed timing is generated by the GPCM for accesses | |
886 | * initiated to this memory region. | |
887 | * - One idle clock is inserted between a read access from the | |
888 | * current bank and the next access. | |
889 | */ | |
6d0f6bcf | 890 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ |
fe8c2806 WD |
891 | ORxG_CSNT |\ |
892 | ORxG_ACS_DIV1 |\ | |
893 | ORxG_SCY_5_CLK |\ | |
894 | ORxG_TRLX |\ | |
895 | ORxG_EHTR) | |
896 | ||
897 | /*----------------------------------------------------------------------- | |
898 | * BR2,BR3 - Base Register | |
899 | * Ref: Section 10.3.1 on page 10-14 | |
900 | * OR2,OR3 - Option Register | |
901 | * Ref: Section 10.3.2 on page 10-16 | |
902 | *----------------------------------------------------------------------- | |
903 | */ | |
904 | ||
905 | /* Bank 2,3 - SDRAM DIMM | |
906 | */ | |
907 | ||
908 | /* The BR2 is configured as follows: | |
909 | * | |
910 | * - Base address of 0x00000000 | |
911 | * - 64 bit port size (60x bus only) | |
912 | * - Data errors checking is disabled | |
913 | * - Read and write access | |
914 | * - SDRAM 60x bus | |
915 | * - Access are handled by the memory controller according to MSEL | |
916 | * - Not used for atomic operations | |
917 | * - No data pipelining is done | |
918 | * - Valid | |
919 | */ | |
6d0f6bcf | 920 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
921 | BRx_PS_64 |\ |
922 | BRx_MS_SDRAM_P |\ | |
923 | BRx_V) | |
924 | ||
6d0f6bcf | 925 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
926 | BRx_PS_64 |\ |
927 | BRx_MS_SDRAM_P |\ | |
928 | BRx_V) | |
929 | ||
930 | /* With a 64 MB DIMM, the OR2 is configured as follows: | |
931 | * | |
932 | * - 64 MB | |
933 | * - 4 internal banks per device | |
934 | * - Row start address bit is A8 with PSDMR[PBI] = 0 | |
935 | * - 12 row address lines | |
936 | * - Back-to-back page mode | |
937 | * - Internal bank interleaving within save device enabled | |
938 | */ | |
6d0f6bcf JCPV |
939 | #if (CONFIG_SYS_SDRAM0_SIZE == 64) |
940 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ | |
fe8c2806 WD |
941 | ORxS_BPD_4 |\ |
942 | ORxS_ROWST_PBI0_A8 |\ | |
943 | ORxS_NUMR_12) | |
944 | #else | |
945 | #error "INVALID SDRAM CONFIGURATION" | |
946 | #endif | |
947 | ||
948 | /*----------------------------------------------------------------------- | |
949 | * PSDMR - 60x Bus SDRAM Mode Register | |
950 | * Ref: Section 10.3.3 on page 10-21 | |
951 | *----------------------------------------------------------------------- | |
952 | */ | |
953 | ||
954 | /* Address that the DIMM SPD memory lives at. | |
955 | */ | |
956 | #define SDRAM_SPD_ADDR 0x50 | |
957 | ||
6d0f6bcf | 958 | #if (CONFIG_SYS_SDRAM0_SIZE == 64) |
fe8c2806 WD |
959 | /* With a 64 MB DIMM, the PSDMR is configured as follows: |
960 | * | |
961 | * - Bank Based Interleaving, | |
962 | * - Refresh Enable, | |
963 | * - Address Multiplexing where A5 is output on A14 pin | |
964 | * (A6 on A15, and so on), | |
965 | * - use address pins A14-A16 as bank select, | |
966 | * - A9 is output on SDA10 during an ACTIVATE command, | |
967 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
968 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
969 | * is 3 clocks, | |
970 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
971 | * 2 clocks, | |
972 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
973 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
974 | * - CAS Latency is 2. | |
975 | */ | |
6d0f6bcf | 976 | #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ |
fe8c2806 WD |
977 | PSDMR_SDAM_A14_IS_A5 |\ |
978 | PSDMR_BSMA_A14_A16 |\ | |
979 | PSDMR_SDA10_PBI0_A9 |\ | |
980 | PSDMR_RFRC_7_CLK |\ | |
981 | PSDMR_PRETOACT_3W |\ | |
982 | PSDMR_ACTTORW_2W |\ | |
983 | PSDMR_LDOTOPRE_1C |\ | |
984 | PSDMR_WRC_1C |\ | |
985 | PSDMR_CL_2) | |
986 | #else | |
987 | #error "INVALID SDRAM CONFIGURATION" | |
988 | #endif | |
989 | ||
990 | /* | |
991 | * Shoot for approximately 1MHz on the prescaler. | |
992 | */ | |
993 | #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000)) | |
6d0f6bcf | 994 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64 |
fe8c2806 | 995 | #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000)) |
6d0f6bcf | 996 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 |
fe8c2806 | 997 | #else |
6d0f6bcf JCPV |
998 | #warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK" |
999 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 | |
fe8c2806 | 1000 | #endif |
6d0f6bcf | 1001 | #define CONFIG_SYS_PSRT 14 |
fe8c2806 WD |
1002 | |
1003 | ||
1004 | /*----------------------------------------------------------------------- | |
1005 | * BR6 - Base Register | |
1006 | * Ref: Section 10.3.1 on page 10-14 | |
1007 | * OR6 - Option Register | |
1008 | * Ref: Section 10.3.2 on page 10-18 | |
1009 | *----------------------------------------------------------------------- | |
1010 | */ | |
1011 | ||
1012 | /* Bank 6 - Secondary FLASH | |
1013 | * | |
1014 | * The secondary FLASH is connected to *CS6 | |
1015 | */ | |
6d0f6bcf | 1016 | #if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) |
fe8c2806 WD |
1017 | |
1018 | /* BR6 is configured as follows: | |
1019 | * | |
1020 | * - Base address of 0x60000000 | |
1021 | * - 16 bit port size | |
1022 | * - Data errors checking is disabled | |
1023 | * - Read and write access | |
1024 | * - GPCM 60x bus | |
1025 | * - Access are handled by the memory controller according to MSEL | |
1026 | * - Not used for atomic operations | |
1027 | * - No data pipelining is done | |
1028 | * - Valid | |
1029 | */ | |
6d0f6bcf | 1030 | # define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
1031 | BRx_PS_16 |\ |
1032 | BRx_MS_GPCM_P |\ | |
1033 | BRx_V) | |
1034 | ||
1035 | /* OR6 is configured as follows: | |
1036 | * | |
1037 | * - 2 MB | |
1038 | * - *BCTL0 is asserted upon access to the current memory bank | |
1039 | * - *CW / *WE are negated a quarter of a clock earlier | |
1040 | * - *CS is output at the same time as the address lines | |
1041 | * - Uses a clock cycle length of 5 | |
1042 | * - *PSDVAL is generated internally by the memory controller | |
1043 | * unless *GTA is asserted earlier externally. | |
1044 | * - Relaxed timing is generated by the GPCM for accesses | |
1045 | * initiated to this memory region. | |
1046 | * - One idle clock is inserted between a read access from the | |
1047 | * current bank and the next access. | |
1048 | */ | |
6d0f6bcf | 1049 | # define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\ |
fe8c2806 WD |
1050 | ORxG_CSNT |\ |
1051 | ORxG_ACS_DIV1 |\ | |
1052 | ORxG_SCY_5_CLK |\ | |
1053 | ORxG_TRLX |\ | |
1054 | ORxG_EHTR) | |
6d0f6bcf | 1055 | #endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */ |
fe8c2806 | 1056 | |
fe8c2806 | 1057 | #endif /* __CONFIG_H */ |