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1/*
2 * Configuration settings for the SAMA5D4EK board.
3 *
4 * Copyright (C) 2014 Atmel
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
b2d387bc 13#include "at91-sama5_common.h"
927b901b 14
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15/* SDRAM */
16#define CONFIG_NR_DRAM_BANKS 1
e61ed48f 17#define CONFIG_SYS_SDRAM_BASE 0x20000000
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18#define CONFIG_SYS_SDRAM_SIZE 0x20000000
19
5a4c9c22 20#ifdef CONFIG_SPL_BUILD
ef33aa3d 21#define CONFIG_SYS_INIT_SP_ADDR 0x218000
5a4c9c22 22#else
927b901b 23#define CONFIG_SYS_INIT_SP_ADDR \
ef33aa3d 24 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
5a4c9c22 25#endif
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26
27#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
28
927b901b 29#ifdef CONFIG_CMD_SF
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30#define CONFIG_SF_DEFAULT_SPEED 30000000
31#endif
32
33/* NAND flash */
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34#ifdef CONFIG_CMD_NAND
35#define CONFIG_NAND_ATMEL
36#define CONFIG_SYS_MAX_NAND_DEVICE 1
e61ed48f 37#define CONFIG_SYS_NAND_BASE 0x80000000
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38/* our ALE is AD21 */
39#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
40/* our CLE is AD22 */
41#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
42#define CONFIG_SYS_NAND_ONFI_DETECTION
43/* PMECC & PMERRLOC */
44#define CONFIG_ATMEL_NAND_HWECC
45#define CONFIG_ATMEL_NAND_HW_PMECC
46#endif
47
927b901b 48/* LCD */
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49#define LCD_BPP LCD_COLOR16
50#define LCD_OUTPUT_BPP 18
51#define CONFIG_LCD_LOGO
52#define CONFIG_LCD_INFO
53#define CONFIG_LCD_INFO_BELOW_LOGO
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54#define CONFIG_ATMEL_HLCD
55#define CONFIG_ATMEL_LCD_RGB565
927b901b 56
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57/* SPL */
58#define CONFIG_SPL_FRAMEWORK
59#define CONFIG_SPL_TEXT_BASE 0x200000
ef33aa3d 60#define CONFIG_SPL_MAX_SIZE 0x18000
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61#define CONFIG_SPL_BSS_START_ADDR 0x20000000
62#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
63#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
64#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
65
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66#define CONFIG_SYS_MONITOR_LEN (512 << 10)
67
5541543f 68#ifdef CONFIG_SD_BOOT
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69#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
70#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
5a4c9c22 71
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72#elif CONFIG_SPI_BOOT
73#define CONFIG_SPL_SPI_LOAD
74#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
75
76#elif CONFIG_NAND_BOOT
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77#define CONFIG_SPL_NAND_DRIVERS
78#define CONFIG_SPL_NAND_BASE
5541543f 79#endif
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80#define CONFIG_PMECC_CAP 8
81#define CONFIG_PMECC_SECTOR_SIZE 512
82#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
83#define CONFIG_SYS_NAND_5_ADDR_CYCLE
84#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
85#define CONFIG_SYS_NAND_PAGE_COUNT 64
86#define CONFIG_SYS_NAND_OOBSIZE 224
87#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
88#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
89#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
90
927b901b 91#endif