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Commit | Line | Data |
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c861fbf7 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
1a459660 | 3 | * SPDX-License-Identifier: GPL-2.0+ |
c861fbf7 SG |
4 | */ |
5 | ||
6 | #ifndef __CONFIG_H | |
7 | #define __CONFIG_H | |
8 | ||
e2ee100f SG |
9 | #ifdef FTRACE |
10 | #define CONFIG_TRACE | |
11 | #define CONFIG_CMD_TRACE | |
12 | #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) | |
13 | #define CONFIG_TRACE_EARLY_SIZE (8 << 20) | |
14 | #define CONFIG_TRACE_EARLY | |
15 | #define CONFIG_TRACE_EARLY_ADDR 0x00100000 | |
16 | ||
17 | #endif | |
18 | ||
1c12bcee | 19 | #ifndef CONFIG_SPL_BUILD |
42d3b29d SG |
20 | #define CONFIG_IO_TRACE |
21 | #define CONFIG_CMD_IOTRACE | |
1c12bcee | 22 | #endif |
42d3b29d | 23 | |
9961a0b6 | 24 | #ifndef CONFIG_TIMER |
28c860b2 | 25 | #define CONFIG_SYS_TIMER_RATE 1000000 |
9961a0b6 | 26 | #endif |
28c860b2 | 27 | |
5923c843 SG |
28 | /* |
29 | * Number of bits in a C 'long' on this architecture. Set this to 32 when | |
30 | * building on a 32-bit machine. | |
31 | */ | |
c861fbf7 SG |
32 | #define CONFIG_SANDBOX_BITS_PER_LONG 64 |
33 | ||
7b06b66c | 34 | #define CONFIG_LMB |
07c0cd71 | 35 | #define CONFIG_ANDROID_BOOT_IMAGE |
7b06b66c | 36 | |
a33aca10 | 37 | #define CONFIG_CMD_PCI |
a33aca10 SG |
38 | #define CONFIG_CMD_IO |
39 | ||
10fc1218 | 40 | #define CONFIG_FS_FAT |
79444955 | 41 | #define CONFIG_FAT_WRITE |
10fc1218 SG |
42 | #define CONFIG_FS_EXT4 |
43 | #define CONFIG_EXT4_WRITE | |
782b9780 SG |
44 | #define CONFIG_CMD_CBFS |
45 | #define CONFIG_CMD_CRAMFS | |
f4d8de48 | 46 | #define CONFIG_CMD_PART |
f4d8de48 | 47 | #define CONFIG_HOST_MAX_DEVICES 4 |
79444955 | 48 | #define CONFIG_CMD_MD5SUM |
10fc1218 | 49 | |
5d62314c EE |
50 | #define CONFIG_CMD_GPT |
51 | #define CONFIG_PARTITION_UUIDS | |
14142811 | 52 | #define CONFIG_EFI_PARTITION |
5d62314c | 53 | |
c861fbf7 | 54 | /* |
b53e94b1 | 55 | * Size of malloc() pool, before and after relocation |
c861fbf7 | 56 | */ |
b53e94b1 | 57 | #define CONFIG_MALLOC_F_ADDR 0x0010000 |
9f604425 | 58 | #define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ |
c861fbf7 | 59 | |
c861fbf7 SG |
60 | #define CONFIG_SYS_LONGHELP /* #undef to save memory */ |
61 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
62 | ||
63 | /* Print Buffer Size */ | |
64 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
65 | #define CONFIG_SYS_MAXARGS 16 | |
66 | ||
67 | /* turn on command-line edit/c/auto */ | |
68 | #define CONFIG_CMDLINE_EDITING | |
69 | #define CONFIG_COMMAND_HISTORY | |
ed0fc4b1 | 70 | #define CONFIG_AUTO_COMPLETE |
c861fbf7 SG |
71 | |
72 | #define CONFIG_ENV_SIZE 8192 | |
73 | #define CONFIG_ENV_IS_NOWHERE | |
74 | ||
5e74934d | 75 | /* SPI - enable all SPI flash types for testing purposes */ |
ca9a5019 | 76 | #define CONFIG_CMD_SF_TEST |
ca9a5019 | 77 | |
ac395f08 | 78 | #define CONFIG_I2C_EDID |
ac395f08 | 79 | |
c861fbf7 | 80 | /* Memory things - we don't really want a memory test */ |
ecdbf419 SG |
81 | #define CONFIG_SYS_LOAD_ADDR 0x00000000 |
82 | #define CONFIG_SYS_MEMTEST_START 0x00100000 | |
c861fbf7 | 83 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) |
2c072c95 SG |
84 | #define CONFIG_SYS_FDT_LOAD_ADDR 0x100 |
85 | ||
86 | #define CONFIG_PHYSMEM | |
c861fbf7 SG |
87 | |
88 | /* Size of our emulated memory */ | |
a733b06b | 89 | #define CONFIG_SYS_SDRAM_BASE 0 |
c861fbf7 | 90 | #define CONFIG_SYS_SDRAM_SIZE (128 << 20) |
a733b06b SG |
91 | #define CONFIG_SYS_TEXT_BASE 0 |
92 | #define CONFIG_SYS_MONITOR_BASE 0 | |
93 | #define CONFIG_NR_DRAM_BANKS 1 | |
c861fbf7 SG |
94 | |
95 | #define CONFIG_BAUDRATE 115200 | |
96 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
97 | 115200} | |
c861fbf7 SG |
98 | |
99 | #define CONFIG_SYS_NO_FLASH | |
100 | ||
101 | /* include default commands */ | |
791a9f67 SS |
102 | #include <config_distro_defaults.h> |
103 | ||
104 | #define BOOT_TARGET_DEVICES(func) \ | |
105 | func(HOST, host, 1) \ | |
106 | func(HOST, host, 0) | |
107 | ||
ebaa832e SS |
108 | #define CONFIG_BOOTCOMMAND "" |
109 | ||
791a9f67 | 110 | #include <config_distro_bootcmd.h> |
c861fbf7 | 111 | |
1f5bc524 JH |
112 | #define CONFIG_KEEP_SERVERADDR |
113 | #define CONFIG_UDP_CHECKSUM | |
1f5bc524 | 114 | #define CONFIG_TIMESTAMP |
f3e0c374 JH |
115 | #define CONFIG_BOOTP_DNS |
116 | #define CONFIG_BOOTP_DNS2 | |
f3e0c374 JH |
117 | #define CONFIG_BOOTP_SEND_HOSTNAME |
118 | #define CONFIG_BOOTP_SERVERIP | |
f3e0c374 | 119 | #define CONFIG_IP_DEFRAG |
c861fbf7 | 120 | |
791a9f67 | 121 | /* Can't boot elf images */ |
791a9f67 | 122 | |
ecdbf419 SG |
123 | #define CONFIG_CMD_HASH |
124 | #define CONFIG_HASH_VERIFY | |
125 | #define CONFIG_SHA1 | |
126 | #define CONFIG_SHA256 | |
127 | ||
e40753b2 SG |
128 | #define CONFIG_CMD_SANDBOX |
129 | ||
7acdf781 JH |
130 | #define CONFIG_CMD_ENV_FLAGS |
131 | #define CONFIG_CMD_ENV_CALLBACK | |
7acdf781 | 132 | |
c861fbf7 SG |
133 | #define CONFIG_BOOTARGS "" |
134 | ||
ad0e4639 | 135 | #ifndef SANDBOX_NO_SDL |
2c072c95 | 136 | #define CONFIG_SANDBOX_SDL |
ad0e4639 SG |
137 | #endif |
138 | ||
139 | /* LCD and keyboard require SDL support */ | |
140 | #ifdef CONFIG_SANDBOX_SDL | |
2c072c95 | 141 | #define CONFIG_CMD_BMP |
2c072c95 | 142 | #define LCD_BPP LCD_COLOR16 |
0156444c | 143 | #define CONFIG_LCD_BMP_RLE8 |
747440d0 SG |
144 | #define CONFIG_VIDEO_BMP_RLE8 |
145 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
2c072c95 | 146 | |
ad0e4639 SG |
147 | #define CONFIG_KEYBOARD |
148 | ||
460a7172 | 149 | #define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \ |
f1a1247d SG |
150 | "stdout=serial,vidconsole\0" \ |
151 | "stderr=serial,vidconsole\0" | |
ad0e4639 | 152 | #else |
3ea143ab | 153 | #define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \ |
f1a1247d SG |
154 | "stdout=serial,vidconsole\0" \ |
155 | "stderr=serial,vidconsole\0" | |
ad0e4639 | 156 | #endif |
c861fbf7 | 157 | |
3ea143ab JH |
158 | #define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ |
159 | "eth1addr=00:00:11:22:33:45\0" \ | |
71d7971f BM |
160 | "eth3addr=00:00:11:22:33:46\0" \ |
161 | "eth5addr=00:00:11:22:33:47\0" \ | |
3ea143ab JH |
162 | "ipaddr=1.2.3.4\0" |
163 | ||
791a9f67 SS |
164 | #define MEM_LAYOUT_ENV_SETTINGS \ |
165 | "bootm_size=0x10000000\0" \ | |
166 | "kernel_addr_r=0x1000000\0" \ | |
167 | "fdt_addr_r=0xc00000\0" \ | |
168 | "ramdisk_addr_r=0x2000000\0" \ | |
169 | "scriptaddr=0x1000\0" \ | |
170 | "pxefile_addr_r=0x2000\0" | |
171 | ||
172 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
173 | SANDBOX_SERIAL_SETTINGS \ | |
174 | SANDBOX_ETH_SETTINGS \ | |
175 | BOOTENV \ | |
176 | MEM_LAYOUT_ENV_SETTINGS | |
3ea143ab | 177 | |
3153e915 KC |
178 | #define CONFIG_GZIP_COMPRESSED |
179 | #define CONFIG_BZIP2 | |
180 | #define CONFIG_LZO | |
181 | #define CONFIG_LZMA | |
182 | ||
def23217 | 183 | #define CONFIG_CMD_LZMADEC |
8e7083fc | 184 | #define CONFIG_CMD_DATE |
def23217 | 185 | |
1c12bcee | 186 | #ifndef CONFIG_SPL_BUILD |
74c6dc14 SG |
187 | #define CONFIG_CMD_IDE |
188 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
189 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
190 | #define CONFIG_SYS_IDE_MAXDEVICE 2 | |
191 | #define CONFIG_SYS_ATA_BASE_ADDR 0x100 | |
192 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 | |
193 | #define CONFIG_SYS_ATA_REG_OFFSET 1 | |
194 | #define CONFIG_SYS_ATA_ALT_OFFSET 2 | |
195 | #define CONFIG_SYS_ATA_STRIDE 4 | |
1c12bcee | 196 | #endif |
74c6dc14 | 197 | |
e8c0a250 SG |
198 | #define CONFIG_SCSI |
199 | #define CONFIG_SCSI_AHCI_PLAT | |
200 | #define CONFIG_SYS_SCSI_MAX_DEVICE 2 | |
201 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 8 | |
202 | #define CONFIG_SYS_SCSI_MAX_LUN 4 | |
203 | ||
199a1201 SG |
204 | #define CONFIG_CMD_SATA |
205 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
206 | ||
cd995a8a SG |
207 | #define CONFIG_SYSTEMACE |
208 | #define CONFIG_SYS_SYSTEMACE_WIDTH 16 | |
209 | #define CONFIG_SYS_SYSTEMACE_BASE 0 | |
210 | ||
afa2c312 SG |
211 | #define CONFIG_GENERIC_MMC |
212 | ||
c861fbf7 | 213 | #endif |