[people/ms/u-boot.git] / include / configs / sbc2410x.h

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 * Gary Jennejohn <garyj@denx.de>
 * David Mueller <d.mueller@elsoft.ch>
 *
 * Modified for the friendly-arm SBC-2410X by
 * (C) Copyright 2005
 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
 *
 * Configuation settings for the friendly-arm SBC-2410X board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * If we are developing, we might want to start armboot from ram
 * so we MUST NOT initialize critical regs like mem-timing ...
 */
#undef CONFIG_SKIP_LOWLEVEL_INIT	/* undef for developing */

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM920T	1	/* This is an ARM920T Core	*/
#define CONFIG_S3C24X0	1	/* in a SAMSUNG S3C24x0-type SoC	*/
#define CONFIG_S3C2410	1	/* specifically a SAMSUNG S3C2410 SoC	*/
#define CONFIG_SBC2410X	1	/* on a friendly-arm SBC-2410X Board  */

/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	12000000/* the SBC2410X has 12MHz input clock */


#define USE_920T_MMU		1
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)

/*
 * Hardware drivers
 */
#define CONFIG_NET_MULTI
#define CONFIG_CS8900		/* we have a CS8900 on-board */
#define CONFIG_CS8900_BASE	0x19000300
#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */

/*
 * select serial console configuration
 */
#define CONFIG_S3C24X0_SERIAL
#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SBC2410X */

/************************************************************
 * RTC
 ************************************************************/
#define	CONFIG_RTC_S3C24X0	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS		"console=ttySAC0 root=/dev/nfs " \
		"nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
		"ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
#define CONFIG_ETHADDR	        08:00:3e:26:0a:5b
#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR		192.168.0.69
#define CONFIG_SERVERIP		192.168.0.1
/*#define CONFIG_BOOTFILE	"elinos-lart" */
#define CONFIG_BOOTCOMMAND	"dhcp; bootm"

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"[ ~ljh@GDLC ]# "	/* Monitor Command Prompt	*/
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x33000000	/* default load address	*/

#define	CONFIG_SYS_HZ			1000

/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
/* #define CONFIG_AMD_LV400	1	/\* uncomment this if you have a LV400 flash *\/ */

#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */

#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif

#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
#endif

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */

/*-----------------------------------------------------------------------
 * NAND flash settings
 */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_S3C2410
#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
#endif	/* CONFIG_CMD_NAND */

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG

#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2   "> "

#define CONFIG_CMDLINE_EDITING

#ifdef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
#else
#define CONFIG_AUTO_COMPLETE
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
32cb2c70 WD	1	/*
	2	* (C) Copyright 2002
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
792a09eb	5	* Gary Jennejohn <garyj@denx.de>
32cb2c70 WD	6	* David Mueller <d.mueller@elsoft.ch>
	7	*
	8	* Modified for the friendly-arm SBC-2410X by
	9	* (C) Copyright 2005
	10	* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
	11	*
	12	* Configuation settings for the friendly-arm SBC-2410X board.
	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	/*
	37	* If we are developing, we might want to start armboot from ram
	38	* so we MUST NOT initialize critical regs like mem-timing ...
	39	*/
	40	#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
	41
	42	/*
	43	* High Level Configuration Options
	44	* (easy to change)
	45	*/
ac67804f	46	#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
	47	#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
	48	#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
	49	#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
32cb2c70 WD	50
	51	/* input clock of PLL */
	52	#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
	53
	54
	55	#define USE_920T_MMU 1
	56	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	57
	58	/*
	59	* Size of malloc() pool
	60	*/
6d0f6bcf	61	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
32cb2c70 WD	62
	63	/*
	64	* Hardware drivers
	65	*/
b1c0eaac BW	66	#define CONFIG_NET_MULTI
	67	#define CONFIG_CS8900 /* we have a CS8900 on-board */
	68	#define CONFIG_CS8900_BASE 0x19000300
	69	#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
32cb2c70 WD	70
	71	/*
	72	* select serial console configuration
	73	*/
300f99f4	74	#define CONFIG_S3C24X0_SERIAL
32cb2c70 WD	75	#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
	76
	77	/************************************************************
	78	* RTC
	79	************************************************************/
	80	#define CONFIG_RTC_S3C24X0 1
	81
	82	/* allow to overwrite serial and ethaddr */
	83	#define CONFIG_ENV_OVERWRITE
	84
	85	#define CONFIG_BAUDRATE 115200
	86
866e3089	87
079a136c JL	88	/*
	89	* BOOTP options
	90	*/
	91	#define CONFIG_BOOTP_BOOTFILESIZE
	92	#define CONFIG_BOOTP_BOOTPATH
	93	#define CONFIG_BOOTP_GATEWAY
	94	#define CONFIG_BOOTP_HOSTNAME
	95
	96
866e3089 JL	97	/*
	98	* Command line configuration.
	99	*/
	100	#include <config_cmd_default.h>
	101
	102	#define CONFIG_CMD_ASKENV
	103	#define CONFIG_CMD_CACHE
	104	#define CONFIG_CMD_DATE
	105	#define CONFIG_CMD_DHCP
	106	#define CONFIG_CMD_ELF
	107	#define CONFIG_CMD_PING
866e3089	108
32cb2c70 WD	109
32cb2c70 WD	110	#define CONFIG_BOOTDELAY 3
53677ef1 WD	111	#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \
	112	"nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
	113	"ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
32cb2c70 WD	114	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	115	#define CONFIG_NETMASK 255.255.255.0
	116	#define CONFIG_IPADDR 192.168.0.69
	117	#define CONFIG_SERVERIP 192.168.0.1
	118	/#define CONFIG_BOOTFILE "elinos-lart" /
	119	#define CONFIG_BOOTCOMMAND "dhcp; bootm"
	120
866e3089	121	#if defined(CONFIG_CMD_KGDB)
32cb2c70 WD	122	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	123	/* what's this ? it's not used anywhere */
	124	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	125	#endif
	126
	127	/*
	128	* Miscellaneous configurable options
	129	*/
6d0f6bcf JCPV	130	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	131	#define CONFIG_SYS_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
	132	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	133	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	134	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	135	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
32cb2c70	136
6d0f6bcf JCPV	137	#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
6d0f6bcf JCPV	138	#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
32cb2c70	139
6d0f6bcf	140	#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
32cb2c70	141
cd85662b	142	#define CONFIG_SYS_HZ 1000
32cb2c70 WD	143
32cb2c70 WD	144	/* valid baudrates */
6d0f6bcf	145	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
32cb2c70 WD	146
	147	/*-----------------------------------------------------------------------
	148	* Stack sizes
	149	*
	150	* The stack sizes are set up in start.S using the settings below
	151	*/
	152	#define CONFIG_STACKSIZE (1281024) / regular stack */
	153	#ifdef CONFIG_USE_IRQ
	154	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	155	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	156	#endif
	157
	158	/*-----------------------------------------------------------------------
	159	* Physical Memory Map
	160	*/
	161	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	162	#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
	163	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	164
	165	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	166
6d0f6bcf	167	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
32cb2c70 WD	168
	169	/*-----------------------------------------------------------------------
	170	* FLASH and environment organization
	171	*/
	172	/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash \/ /
	173
	174	#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
	175
6d0f6bcf	176	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
32cb2c70 WD	177
	178	#ifdef CONFIG_AMD_LV800
	179	#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
6d0f6bcf JCPV	180	#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
6d0f6bcf JCPV	181	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
32cb2c70 WD	182	#endif
	183
	184	#ifdef CONFIG_AMD_LV400
	185	#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
6d0f6bcf JCPV	187	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
32cb2c70 WD	188	#endif
	189
	190	/* timeout values are in ticks */
6d0f6bcf JCPV	191	#define CONFIG_SYS_FLASH_ERASE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	192	#define CONFIG_SYS_FLASH_WRITE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Write */
32cb2c70	193
5a1aceb0	194	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	195	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
32cb2c70 WD	196
	197	/*-----------------------------------------------------------------------
	198	* NAND flash settings
	199	*/
866e3089	200	#if defined(CONFIG_CMD_NAND)
b3f66b0b	201	#define CONFIG_NAND_S3C2410
6d0f6bcf	202	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
866e3089	203	#endif /* CONFIG_CMD_NAND */
32cb2c70 WD	204
	205	#define CONFIG_SETUP_MEMORY_TAGS
	206	#define CONFIG_INITRD_TAG
	207	#define CONFIG_CMDLINE_TAG
	208
6d0f6bcf JCPV	209	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	210	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
32cb2c70 WD	211
	212	#define CONFIG_CMDLINE_EDITING
	213
	214	#ifdef CONFIG_CMDLINE_EDITING
	215	#undef CONFIG_AUTO_COMPLETE
	216	#else
	217	#define CONFIG_AUTO_COMPLETE
	218	#endif
	219
	220	#endif /* __CONFIG_H */