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652a10c0 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * board/config.h - configuration options, board specific | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
35 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
36 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
37 | #define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ | |
38 | ||
2ae18241 WD |
39 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
40 | ||
652a10c0 WD |
41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
42 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
43 | ||
44 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
45 | ||
46 | #define CONFIG_BAUDRATE 9600 | |
47 | ||
48 | #define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo" | |
49 | ||
50 | #define CONFIG_RAMBOOT \ | |
fe126d8b WD |
51 | "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ |
52 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
652a10c0 WD |
53 | "bootm ffc00000 ffca0000" |
54 | #define CONFIG_NFSBOOT \ | |
fe126d8b WD |
55 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
56 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
652a10c0 WD |
57 | "bootm ffc00000" |
58 | ||
59 | #undef CONFIG_BOOTARGS | |
fe126d8b | 60 | #define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */ |
652a10c0 WD |
61 | |
62 | ||
96e21f86 | 63 | #define CONFIG_PPC4xx_EMAC |
652a10c0 WD |
64 | #define CONFIG_MII 1 /* MII PHY management */ |
65 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
66 | #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ | |
18cc7afd | 67 | #define CONFIG_NET_MULTI |
652a10c0 WD |
68 | |
69 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
70 | "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \ | |
71 | "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \ | |
72 | "f=0x08 tn=sbc405 o=emac \0" \ | |
73 | "env_startaddr=FF000000\0" \ | |
74 | "env_endaddr=FF03FFFF\0" \ | |
75 | "loadfile=vxWorks.st\0" \ | |
76 | "loadaddr=0x01000000\0" \ | |
fe126d8b | 77 | "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ |
652a10c0 WD |
78 | "uboot_startaddr=FFFC0000\0" \ |
79 | "uboot_endaddr=FFFFFFFF\0" \ | |
fe126d8b WD |
80 | "update=tftp ${loadaddr} u-boot.bin;" \ |
81 | "protect off ${uboot_startaddr} ${uboot_endaddr};" \ | |
82 | "era ${uboot_startaddr} ${uboot_endaddr};" \ | |
83 | "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \ | |
84 | "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \ | |
85 | "zapenv=protect off ${env_startaddr} ${env_endaddr};" \ | |
86 | "era ${env_startaddr} ${env_endaddr};" \ | |
87 | "protect on ${env_startaddr} ${env_endaddr}\0" | |
652a10c0 WD |
88 | |
89 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
90 | ||
d3b8c1a7 JL |
91 | /* |
92 | * BOOTP options | |
93 | */ | |
94 | #define CONFIG_BOOTP_SUBNETMASK | |
95 | #define CONFIG_BOOTP_GATEWAY | |
96 | #define CONFIG_BOOTP_HOSTNAME | |
97 | #define CONFIG_BOOTP_BOOTPATH | |
98 | #define CONFIG_BOOTP_BOOTFILESIZE | |
99 | ||
652a10c0 WD |
100 | |
101 | #define CONFIG_ENV_OVERWRITE | |
102 | ||
866e3089 JL |
103 | |
104 | /* | |
105 | * Command line configuration. | |
106 | */ | |
107 | #include <config_cmd_default.h> | |
108 | ||
109 | #define CONFIG_CMD_BSP | |
110 | #define CONFIG_CMD_ELF | |
111 | #define CONFIG_CMD_I2C | |
112 | #define CONFIG_CMD_IRQ | |
113 | #define CONFIG_CMD_MII | |
114 | #define CONFIG_CMD_PCI | |
115 | #define CONFIG_CMD_PING | |
116 | #define CONFIG_CMD_SDRAM | |
117 | ||
652a10c0 WD |
118 | |
119 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
120 | ||
121 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
122 | ||
123 | #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ | |
124 | #define CONFIG_IPADDR 192.168.193.102 | |
125 | #define CONFIG_NETMASK 255.255.255.224 | |
126 | #define CONFIG_SERVERIP 192.168.193.119 | |
127 | #define CONFIG_GATEWAYIP 192.168.193.97 | |
128 | ||
129 | /* | |
130 | * Miscellaneous configurable options | |
131 | */ | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
133 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
652a10c0 | 134 | |
6d0f6bcf JCPV |
135 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
136 | #ifdef CONFIG_SYS_HUSH_PARSER | |
137 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
652a10c0 WD |
138 | #endif |
139 | ||
866e3089 | 140 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 141 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
652a10c0 | 142 | #else |
6d0f6bcf | 143 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
652a10c0 | 144 | #endif |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
146 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
147 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
652a10c0 | 148 | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
150 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
652a10c0 | 151 | |
550650dd SR |
152 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
153 | #define CONFIG_SYS_NS16550 | |
154 | #define CONFIG_SYS_NS16550_SERIAL | |
155 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
156 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
157 | ||
6d0f6bcf | 158 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 159 | #define CONFIG_SYS_BASE_BAUD 691200 |
652a10c0 WD |
160 | |
161 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 162 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
652a10c0 WD |
163 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
164 | 57600, 115200, 230400, 460800, 921600 } | |
165 | ||
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
167 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ | |
652a10c0 | 168 | |
6d0f6bcf | 169 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
652a10c0 WD |
170 | |
171 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
172 | ||
6d0f6bcf | 173 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
652a10c0 WD |
174 | |
175 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
176 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
d0b0dcaa | 177 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
179 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
652a10c0 WD |
180 | |
181 | /*----------------------------------------------------------------------- | |
182 | * PCI stuff | |
183 | *----------------------------------------------------------------------- | |
184 | */ | |
185 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
186 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
187 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
188 | ||
189 | #define CONFIG_PCI /* include pci support */ | |
190 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
191 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
192 | /* resource configuration */ | |
193 | ||
194 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
195 | ||
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
197 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ | |
198 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
199 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
200 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
201 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
202 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
203 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
204 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
652a10c0 WD |
205 | |
206 | /*----------------------------------------------------------------------- | |
207 | * Start addresses for the final memory configuration | |
208 | * (Set up by the startup code) | |
6d0f6bcf | 209 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
652a10c0 | 210 | */ |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
212 | #define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 | |
213 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
214 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
652a10c0 WD |
215 | |
216 | /* | |
217 | * For booting Linux, the board info and command line data | |
218 | * have to be in the first 8 MB of memory, since this is | |
219 | * the maximum mapped by the Linux kernel during initialization. | |
220 | */ | |
6d0f6bcf | 221 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
652a10c0 WD |
222 | |
223 | /*----------------------------------------------------------------------- | |
224 | * FLASH organization | |
225 | */ | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
227 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
228 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
229 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ | |
230 | #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 | |
231 | #undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ | |
232 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
233 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
234 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
235 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
652a10c0 WD |
236 | |
237 | /*----------------------------------------------------------------------- | |
238 | * Environment Variable setup | |
239 | */ | |
6d0f6bcf | 240 | #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */ |
5a1aceb0 | 241 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
242 | #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ |
243 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ | |
244 | #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ | |
652a10c0 | 245 | |
652a10c0 WD |
246 | /*----------------------------------------------------------------------- |
247 | * External Bus Controller (EBC) Setup | |
248 | */ | |
6d0f6bcf | 249 | #define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */ |
652a10c0 WD |
250 | |
251 | /* Memory Bank 0 (Flash Bank 0) initialization */ | |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
253 | #define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/ | |
652a10c0 WD |
254 | |
255 | /*----------------------------------------------------------------------- | |
256 | * Definitions for initial stack pointer and data area (in data cache) | |
257 | */ | |
258 | ||
259 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 260 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
652a10c0 WD |
261 | |
262 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
264 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
265 | ||
266 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 267 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
25ddd1fb | 268 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 269 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
652a10c0 WD |
270 | |
271 | /*----------------------------------------------------------------------- | |
272 | * Definitions for Serial Presence Detect EEPROM address | |
273 | * (to get SDRAM settings) | |
274 | */ | |
275 | #define SPD_EEPROM_ADDRESS 0x50 | |
276 | #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ | |
277 | ||
652a10c0 | 278 | #endif /* __CONFIG_H */ |