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9e3ed392 | 1 | /* |
2738bc8d | 2 | * Copyright 2007,2009 Wind River Systems <www.windriver.com> |
9e3ed392 JH |
3 | * Copyright 2007 Embedded Specialties, Inc. |
4 | * Copyright 2004, 2007 Freescale Semiconductor. | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
9e3ed392 JH |
7 | */ |
8 | ||
9 | /* | |
10 | * sbc8548 board configuration file | |
2738bc8d | 11 | * Please refer to doc/README.sbc8548 for more info. |
9e3ed392 JH |
12 | */ |
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
2738bc8d PG |
16 | /* |
17 | * Top level Makefile configuration choices | |
18 | */ | |
d24f2d32 | 19 | #ifdef CONFIG_PCI |
842033e6 | 20 | #define CONFIG_PCI_INDIRECT_BRIDGE |
2738bc8d PG |
21 | #define CONFIG_PCI1 |
22 | #endif | |
23 | ||
d24f2d32 | 24 | #ifdef CONFIG_66 |
2738bc8d PG |
25 | #define CONFIG_SYS_CLK_DIV 1 |
26 | #endif | |
27 | ||
d24f2d32 | 28 | #ifdef CONFIG_33 |
2738bc8d PG |
29 | #define CONFIG_SYS_CLK_DIV 2 |
30 | #endif | |
31 | ||
d24f2d32 | 32 | #ifdef CONFIG_PCIE |
2738bc8d PG |
33 | #define CONFIG_PCIE1 |
34 | #endif | |
35 | ||
36 | /* | |
37 | * High Level Configuration Options | |
38 | */ | |
9e3ed392 JH |
39 | #define CONFIG_SBC8548 1 /* SBC8548 board specific */ |
40 | ||
f0aec4ea PG |
41 | /* |
42 | * If you want to boot from the SODIMM flash, instead of the soldered | |
43 | * on flash, set this, and change JP12, SW2:8 accordingly. | |
44 | */ | |
45 | #undef CONFIG_SYS_ALT_BOOT | |
46 | ||
2ae18241 | 47 | #ifndef CONFIG_SYS_TEXT_BASE |
f0aec4ea PG |
48 | #ifdef CONFIG_SYS_ALT_BOOT |
49 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 | |
50 | #else | |
2ae18241 WD |
51 | #define CONFIG_SYS_TEXT_BASE 0xfffa0000 |
52 | #endif | |
f0aec4ea | 53 | #endif |
2ae18241 | 54 | |
9e3ed392 | 55 | #undef CONFIG_RIO |
fdc7eb90 PG |
56 | |
57 | #ifdef CONFIG_PCI | |
58 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
59 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
60 | #endif | |
61 | #ifdef CONFIG_PCIE1 | |
62 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
63 | #endif | |
9e3ed392 JH |
64 | |
65 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
66 | #define CONFIG_ENV_OVERWRITE | |
9e3ed392 | 67 | |
9e3ed392 JH |
68 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
69 | ||
2738bc8d PG |
70 | /* |
71 | * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] | |
72 | */ | |
73 | #ifndef CONFIG_SYS_CLK_DIV | |
74 | #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ | |
75 | #endif | |
76 | #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) | |
9e3ed392 JH |
77 | |
78 | /* | |
79 | * These can be toggled for performance analysis, otherwise use default. | |
80 | */ | |
81 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
82 | #define CONFIG_BTB /* toggle branch predition */ | |
9e3ed392 JH |
83 | |
84 | /* | |
85 | * Only possible on E500 Version 2 or newer cores. | |
86 | */ | |
87 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
88 | ||
6d0f6bcf JCPV |
89 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
90 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
91 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
9e3ed392 | 92 | |
e46fedfe TT |
93 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
94 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
9e3ed392 | 95 | |
33b9079b | 96 | /* DDR Setup */ |
33b9079b | 97 | #undef CONFIG_FSL_DDR_INTERACTIVE |
7e44f2b7 PG |
98 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
99 | /* | |
100 | * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD | |
101 | * to collide, meaning you couldn't reliably read either. So | |
102 | * physically remove the LBC PC100 SDRAM module from the board | |
3e3262bd PG |
103 | * before enabling the two SPD options below, or check that you |
104 | * have the hardware fix on your board via "i2c probe" and looking | |
105 | * for a device at 0x53. | |
7e44f2b7 | 106 | */ |
33b9079b KG |
107 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
108 | #undef CONFIG_DDR_SPD | |
33b9079b KG |
109 | |
110 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
111 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
112 | ||
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
114 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
33b9079b KG |
115 | #define CONFIG_VERY_BIG_RAM |
116 | ||
33b9079b KG |
117 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
118 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
9e3ed392 | 119 | |
3e3262bd PG |
120 | /* |
121 | * The hardware fix for the I2C address collision puts the DDR | |
122 | * SPD at 0x53, but if we are running on an older board w/o the | |
123 | * fix, it will still be at 0x51. We check 0x53 1st. | |
124 | */ | |
33b9079b | 125 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
3e3262bd | 126 | #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ |
9e3ed392 JH |
127 | |
128 | /* | |
129 | * Make sure required options are set | |
130 | */ | |
131 | #ifndef CONFIG_SPD_EEPROM | |
6d0f6bcf | 132 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
2a6b3b74 | 133 | #define CONFIG_SYS_DDR_CONTROL 0xc300c000 |
9e3ed392 JH |
134 | #endif |
135 | ||
136 | #undef CONFIG_CLOCKS_IN_MHZ | |
137 | ||
138 | /* | |
139 | * FLASH on the Local Bus | |
140 | * Two banks, one 8MB the other 64MB, using the CFI driver. | |
f0aec4ea PG |
141 | * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have |
142 | * CS0 the 8MB boot flash, and CS6 the 64MB flash. | |
143 | * | |
144 | * Default: | |
145 | * ec00_0000 efff_ffff 64MB SODIMM | |
146 | * ff80_0000 ffff_ffff 8MB soldered flash | |
9e3ed392 | 147 | * |
f0aec4ea PG |
148 | * Alternate: |
149 | * ef80_0000 efff_ffff 8MB soldered flash | |
150 | * fc00_0000 ffff_ffff 64MB SODIMM | |
151 | * | |
152 | * BR0_8M: | |
9e3ed392 JH |
153 | * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 |
154 | * Port Size = 8 bits = BRx[19:20] = 01 | |
155 | * Use GPCM = BRx[24:26] = 000 | |
156 | * Valid = BRx[31] = 1 | |
157 | * | |
f0aec4ea PG |
158 | * BR0_64M: |
159 | * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 | |
9e3ed392 | 160 | * Port Size = 32 bits = BRx[19:20] = 11 |
f0aec4ea PG |
161 | * |
162 | * 0 4 8 12 16 20 24 28 | |
163 | * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M | |
164 | * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M | |
165 | */ | |
166 | #define CONFIG_SYS_BR0_8M 0xff800801 | |
167 | #define CONFIG_SYS_BR0_64M 0xfc001801 | |
168 | ||
169 | /* | |
170 | * BR6_8M: | |
171 | * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 | |
172 | * Port Size = 8 bits = BRx[19:20] = 01 | |
9e3ed392 JH |
173 | * Use GPCM = BRx[24:26] = 000 |
174 | * Valid = BRx[31] = 1 | |
f0aec4ea PG |
175 | |
176 | * BR6_64M: | |
177 | * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 | |
178 | * Port Size = 32 bits = BRx[19:20] = 11 | |
9e3ed392 JH |
179 | * |
180 | * 0 4 8 12 16 20 24 28 | |
f0aec4ea PG |
181 | * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M |
182 | * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M | |
183 | */ | |
184 | #define CONFIG_SYS_BR6_8M 0xef800801 | |
185 | #define CONFIG_SYS_BR6_64M 0xec001801 | |
186 | ||
187 | /* | |
188 | * OR0_8M: | |
9e3ed392 JH |
189 | * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 |
190 | * XAM = OR0[17:18] = 11 | |
191 | * CSNT = OR0[20] = 1 | |
192 | * ACS = half cycle delay = OR0[21:22] = 11 | |
193 | * SCY = 6 = OR0[24:27] = 0110 | |
194 | * TRLX = use relaxed timing = OR0[29] = 1 | |
195 | * EAD = use external address latch delay = OR0[31] = 1 | |
196 | * | |
f0aec4ea PG |
197 | * OR0_64M: |
198 | * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 | |
9e3ed392 | 199 | * |
f0aec4ea PG |
200 | * |
201 | * 0 4 8 12 16 20 24 28 | |
202 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M | |
203 | * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M | |
204 | */ | |
205 | #define CONFIG_SYS_OR0_8M 0xff806e65 | |
206 | #define CONFIG_SYS_OR0_64M 0xfc006e65 | |
207 | ||
208 | /* | |
209 | * OR6_8M: | |
210 | * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 | |
9e3ed392 JH |
211 | * XAM = OR6[17:18] = 11 |
212 | * CSNT = OR6[20] = 1 | |
213 | * ACS = half cycle delay = OR6[21:22] = 11 | |
214 | * SCY = 6 = OR6[24:27] = 0110 | |
215 | * TRLX = use relaxed timing = OR6[29] = 1 | |
216 | * EAD = use external address latch delay = OR6[31] = 1 | |
217 | * | |
f0aec4ea PG |
218 | * OR6_64M: |
219 | * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 | |
220 | * | |
9e3ed392 | 221 | * 0 4 8 12 16 20 24 28 |
f0aec4ea PG |
222 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M |
223 | * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M | |
9e3ed392 | 224 | */ |
f0aec4ea PG |
225 | #define CONFIG_SYS_OR6_8M 0xff806e65 |
226 | #define CONFIG_SYS_OR6_64M 0xfc006e65 | |
9e3ed392 | 227 | |
f0aec4ea | 228 | #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ |
6d0f6bcf | 229 | #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ |
3fd673cf | 230 | #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ |
9e3ed392 | 231 | |
f0aec4ea PG |
232 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M |
233 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M | |
234 | ||
235 | #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M | |
236 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M | |
237 | #else /* JP12 in alternate position */ | |
238 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ | |
239 | #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ | |
9e3ed392 | 240 | |
f0aec4ea PG |
241 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M |
242 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M | |
243 | ||
244 | #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M | |
245 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M | |
246 | #endif | |
9e3ed392 | 247 | |
f0aec4ea | 248 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK |
9b3ba24f PG |
249 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ |
250 | CONFIG_SYS_ALT_FLASH} | |
251 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
252 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
6d0f6bcf JCPV |
253 | #undef CONFIG_SYS_FLASH_CHECKSUM |
254 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
255 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
9e3ed392 | 256 | |
14d0a02a | 257 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
9e3ed392 | 258 | |
00b1883a | 259 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_FLASH_CFI |
261 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
9e3ed392 JH |
262 | |
263 | /* CS5 = Local bus peripherals controlled by the EPLD */ | |
264 | ||
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_BR5_PRELIM 0xf8000801 |
266 | #define CONFIG_SYS_OR5_PRELIM 0xff006e65 | |
267 | #define CONFIG_SYS_EPLD_BASE 0xf8000000 | |
268 | #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 | |
269 | #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 | |
270 | #define CONFIG_SYS_BD_REV 0xf8300000 | |
271 | #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 | |
9e3ed392 JH |
272 | |
273 | /* | |
11d5a629 | 274 | * SDRAM on the Local Bus (CS3 and CS4) |
7e44f2b7 PG |
275 | * Note that most boards have a hardware errata where both the |
276 | * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible | |
277 | * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. | |
3e3262bd | 278 | * A hardware workaround is also available, see README.sbc8548 file. |
9e3ed392 | 279 | */ |
6d0f6bcf | 280 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
11d5a629 | 281 | #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ |
9e3ed392 JH |
282 | |
283 | /* | |
11d5a629 | 284 | * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. |
6d0f6bcf | 285 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
9e3ed392 JH |
286 | * |
287 | * For BR3, need: | |
288 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
289 | * port-size = 32-bits = BR2[19:20] = 11 | |
290 | * no parity checking = BR2[21:22] = 00 | |
291 | * SDRAM for MSEL = BR2[24:26] = 011 | |
292 | * Valid = BR[31] = 1 | |
293 | * | |
294 | * 0 4 8 12 16 20 24 28 | |
295 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
296 | * | |
297 | */ | |
298 | ||
6d0f6bcf | 299 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 |
9e3ed392 JH |
300 | |
301 | /* | |
11d5a629 | 302 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
9e3ed392 JH |
303 | * |
304 | * For OR3, need: | |
305 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
306 | * XAM, OR3[17:18] = 11 | |
307 | * 10 columns OR3[19-21] = 011 | |
308 | * 12 rows OR3[23-25] = 011 | |
309 | * EAD set for extra time OR[31] = 0 | |
310 | * | |
311 | * 0 4 8 12 16 20 24 28 | |
312 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
313 | */ | |
314 | ||
6d0f6bcf | 315 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 |
9e3ed392 | 316 | |
11d5a629 PG |
317 | /* |
318 | * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. | |
319 | * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. | |
320 | * | |
321 | * For BR4, need: | |
322 | * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 | |
323 | * port-size = 32-bits = BR2[19:20] = 11 | |
324 | * no parity checking = BR2[21:22] = 00 | |
325 | * SDRAM for MSEL = BR2[24:26] = 011 | |
326 | * Valid = BR[31] = 1 | |
327 | * | |
328 | * 0 4 8 12 16 20 24 28 | |
329 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 | |
330 | * | |
331 | */ | |
332 | ||
333 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 | |
334 | ||
335 | /* | |
336 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. | |
337 | * | |
338 | * For OR4, need: | |
339 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
340 | * XAM, OR3[17:18] = 11 | |
341 | * 10 columns OR3[19-21] = 011 | |
342 | * 12 rows OR3[23-25] = 011 | |
343 | * EAD set for extra time OR[31] = 0 | |
344 | * | |
345 | * 0 4 8 12 16 20 24 28 | |
346 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
347 | */ | |
348 | ||
349 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 | |
350 | ||
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ |
352 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
353 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
354 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
9e3ed392 | 355 | |
9e3ed392 JH |
356 | /* |
357 | * Common settings for all Local Bus SDRAM commands. | |
9e3ed392 | 358 | */ |
b0fe93ed | 359 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
5f4c6f0d PG |
360 | | LSDMR_BSMA1516 \ |
361 | | LSDMR_PRETOACT3 \ | |
362 | | LSDMR_ACTTORW3 \ | |
363 | | LSDMR_BUFCMD \ | |
b0fe93ed | 364 | | LSDMR_BL8 \ |
5f4c6f0d | 365 | | LSDMR_WRC2 \ |
b0fe93ed | 366 | | LSDMR_CL3 \ |
9e3ed392 JH |
367 | ) |
368 | ||
5f4c6f0d PG |
369 | #define CONFIG_SYS_LBC_LSDMR_PCHALL \ |
370 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) | |
371 | #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ | |
372 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
373 | #define CONFIG_SYS_LBC_LSDMR_MRW \ | |
374 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
375 | #define CONFIG_SYS_LBC_LSDMR_RFEN \ | |
376 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) | |
377 | ||
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
379 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 380 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
9e3ed392 | 381 | |
6d0f6bcf | 382 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
9e3ed392 | 383 | |
25ddd1fb | 384 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 385 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9e3ed392 | 386 | |
dd9ca98f PG |
387 | /* |
388 | * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and | |
14d0a02a | 389 | * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM |
dd9ca98f | 390 | * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg |
14d0a02a | 391 | * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right |
dd9ca98f PG |
392 | * thing for MONITOR_LEN in both cases. |
393 | */ | |
14d0a02a | 394 | #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) |
f0aec4ea | 395 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
9e3ed392 JH |
396 | |
397 | /* Serial Port */ | |
398 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_NS16550_SERIAL |
400 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
2738bc8d | 401 | #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) |
9e3ed392 | 402 | |
6d0f6bcf | 403 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9e3ed392 JH |
404 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
405 | ||
6d0f6bcf JCPV |
406 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
407 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
9e3ed392 | 408 | |
9e3ed392 JH |
409 | /* |
410 | * I2C | |
411 | */ | |
00f792e0 HS |
412 | #define CONFIG_SYS_I2C |
413 | #define CONFIG_SYS_I2C_FSL | |
414 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
415 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
416 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
6d0f6bcf | 417 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
9e3ed392 JH |
418 | |
419 | /* | |
420 | * General PCI | |
421 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
422 | */ | |
fdc7eb90 | 423 | #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ |
6d0f6bcf | 424 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
9e3ed392 | 425 | |
fdc7eb90 PG |
426 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
427 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 | |
428 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
6d0f6bcf | 429 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
fdc7eb90 PG |
430 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
431 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
432 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 | |
433 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
9e3ed392 JH |
434 | |
435 | #ifdef CONFIG_PCIE1 | |
fdc7eb90 PG |
436 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
437 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
438 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
6d0f6bcf | 439 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
fdc7eb90 PG |
440 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
441 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
442 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
443 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
9e3ed392 JH |
444 | #endif |
445 | ||
446 | #ifdef CONFIG_RIO | |
447 | /* | |
448 | * RapidIO MMU | |
449 | */ | |
6d0f6bcf JCPV |
450 | #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 |
451 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ | |
9e3ed392 JH |
452 | #endif |
453 | ||
9e3ed392 | 454 | #if defined(CONFIG_PCI) |
9e3ed392 JH |
455 | #undef CONFIG_EEPRO100 |
456 | #undef CONFIG_TULIP | |
457 | ||
fdc7eb90 | 458 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
9e3ed392 | 459 | |
9e3ed392 JH |
460 | #endif /* CONFIG_PCI */ |
461 | ||
9e3ed392 JH |
462 | #if defined(CONFIG_TSEC_ENET) |
463 | ||
9e3ed392 JH |
464 | #define CONFIG_MII 1 /* MII PHY management */ |
465 | #define CONFIG_TSEC1 1 | |
466 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
467 | #define CONFIG_TSEC2 1 | |
468 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
9e3ed392 JH |
469 | #undef CONFIG_MPC85XX_FEC |
470 | ||
58da8890 PG |
471 | #define TSEC1_PHY_ADDR 0x19 |
472 | #define TSEC2_PHY_ADDR 0x1a | |
9e3ed392 JH |
473 | |
474 | #define TSEC1_PHYIDX 0 | |
475 | #define TSEC2_PHYIDX 0 | |
bd93105f | 476 | |
9e3ed392 JH |
477 | #define TSEC1_FLAGS TSEC_GIGABIT |
478 | #define TSEC2_FLAGS TSEC_GIGABIT | |
9e3ed392 JH |
479 | |
480 | /* Options are: eTSEC[0-3] */ | |
481 | #define CONFIG_ETHPRIME "eTSEC0" | |
482 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
483 | #endif /* CONFIG_TSEC_ENET */ | |
484 | ||
485 | /* | |
486 | * Environment | |
487 | */ | |
5a1aceb0 | 488 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 489 | #define CONFIG_ENV_SIZE 0x2000 |
14d0a02a | 490 | #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ |
dd9ca98f PG |
491 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) |
492 | #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ | |
14d0a02a | 493 | #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ |
dd9ca98f PG |
494 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
495 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
496 | #else | |
497 | #warning undefined environment size/location. | |
498 | #endif | |
9e3ed392 JH |
499 | |
500 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 501 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9e3ed392 JH |
502 | |
503 | /* | |
504 | * BOOTP options | |
505 | */ | |
506 | #define CONFIG_BOOTP_BOOTFILESIZE | |
507 | #define CONFIG_BOOTP_BOOTPATH | |
508 | #define CONFIG_BOOTP_GATEWAY | |
509 | #define CONFIG_BOOTP_HOSTNAME | |
510 | ||
9e3ed392 JH |
511 | /* |
512 | * Command line configuration. | |
513 | */ | |
199e262e | 514 | #define CONFIG_CMD_REGINFO |
9e3ed392 JH |
515 | |
516 | #if defined(CONFIG_PCI) | |
517 | #define CONFIG_CMD_PCI | |
518 | #endif | |
519 | ||
9e3ed392 JH |
520 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
521 | ||
522 | /* | |
523 | * Miscellaneous configurable options | |
524 | */ | |
ad22f927 | 525 | #define CONFIG_CMDLINE_EDITING /* undef to save memory */ |
5be58f5f | 526 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
6d0f6bcf JCPV |
527 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
528 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
9e3ed392 | 529 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 530 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9e3ed392 | 531 | #else |
6d0f6bcf | 532 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9e3ed392 | 533 | #endif |
6d0f6bcf JCPV |
534 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
535 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
536 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
9e3ed392 JH |
537 | |
538 | /* | |
539 | * For booting Linux, the board info and command line data | |
540 | * have to be in the first 8 MB of memory, since this is | |
541 | * the maximum mapped by the Linux kernel during initialization. | |
542 | */ | |
6d0f6bcf | 543 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
9e3ed392 | 544 | |
9e3ed392 JH |
545 | #if defined(CONFIG_CMD_KGDB) |
546 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
9e3ed392 JH |
547 | #endif |
548 | ||
549 | /* | |
550 | * Environment Configuration | |
551 | */ | |
9e3ed392 JH |
552 | #if defined(CONFIG_TSEC_ENET) |
553 | #define CONFIG_HAS_ETH0 | |
9e3ed392 | 554 | #define CONFIG_HAS_ETH1 |
9e3ed392 JH |
555 | #endif |
556 | ||
557 | #define CONFIG_IPADDR 192.168.0.55 | |
558 | ||
559 | #define CONFIG_HOSTNAME sbc8548 | |
8b3637c6 | 560 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" |
b3f44c21 | 561 | #define CONFIG_BOOTFILE "/uImage" |
9e3ed392 JH |
562 | #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ |
563 | ||
564 | #define CONFIG_SERVERIP 192.168.0.2 | |
565 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
566 | #define CONFIG_NETMASK 255.255.255.0 | |
567 | ||
568 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
569 | ||
9e3ed392 JH |
570 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
571 | ||
9e3ed392 | 572 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
573 | "netdev=eth0\0" \ |
574 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
575 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
576 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
577 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
578 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
579 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
580 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
581 | "consoledev=ttyS0\0" \ | |
582 | "ramdiskaddr=2000000\0" \ | |
583 | "ramdiskfile=uRamdisk\0" \ | |
b24a4f62 | 584 | "fdtaddr=1e00000\0" \ |
5368c55d | 585 | "fdtfile=sbc8548.dtb\0" |
9e3ed392 JH |
586 | |
587 | #define CONFIG_NFSBOOTCOMMAND \ | |
588 | "setenv bootargs root=/dev/nfs rw " \ | |
589 | "nfsroot=$serverip:$rootpath " \ | |
590 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
591 | "console=$consoledev,$baudrate $othbootargs;" \ | |
592 | "tftp $loadaddr $bootfile;" \ | |
593 | "tftp $fdtaddr $fdtfile;" \ | |
594 | "bootm $loadaddr - $fdtaddr" | |
595 | ||
9e3ed392 JH |
596 | #define CONFIG_RAMBOOTCOMMAND \ |
597 | "setenv bootargs root=/dev/ram rw " \ | |
598 | "console=$consoledev,$baudrate $othbootargs;" \ | |
599 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
600 | "tftp $loadaddr $bootfile;" \ | |
601 | "tftp $fdtaddr $fdtfile;" \ | |
602 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
603 | ||
604 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
605 | ||
606 | #endif /* __CONFIG_H */ |