projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9e3ed392 | 1 | /* |
| 2738bc8d | 2 | * Copyright 2007,2009 Wind River Systems <www.windriver.com> |
| 9e3ed392 JH |
3 | * Copyright 2007 Embedded Specialties, Inc. |
| 4 | * Copyright 2004, 2007 Freescale Semiconductor. | |
| 5 | * | |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 25 | /* | |
| 26 | * sbc8548 board configuration file | |
| 2738bc8d | 27 | * Please refer to doc/README.sbc8548 for more info. |
| 9e3ed392 JH |
28 | */ |
| 29 | #ifndef __CONFIG_H | |
| 30 | #define __CONFIG_H | |
| 31 | ||
| 2738bc8d PG |
32 | /* |
| 33 | * Top level Makefile configuration choices | |
| 34 | */ | |
| d24f2d32 | 35 | #ifdef CONFIG_PCI |
| 2738bc8d PG |
36 | #define CONFIG_PCI1 |
| 37 | #endif | |
| 38 | ||
| d24f2d32 | 39 | #ifdef CONFIG_66 |
| 2738bc8d PG |
40 | #define CONFIG_SYS_CLK_DIV 1 |
| 41 | #endif | |
| 42 | ||
| d24f2d32 | 43 | #ifdef CONFIG_33 |
| 2738bc8d PG |
44 | #define CONFIG_SYS_CLK_DIV 2 |
| 45 | #endif | |
| 46 | ||
| d24f2d32 | 47 | #ifdef CONFIG_PCIE |
| 2738bc8d PG |
48 | #define CONFIG_PCIE1 |
| 49 | #endif | |
| 50 | ||
| 51 | /* | |
| 52 | * High Level Configuration Options | |
| 53 | */ | |
| 9e3ed392 JH |
54 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 55 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 56 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 57 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ | |
| 58 | #define CONFIG_SBC8548 1 /* SBC8548 board specific */ | |
| 59 | ||
| 2ae18241 WD |
60 | #ifndef CONFIG_SYS_TEXT_BASE |
| 61 | #define CONFIG_SYS_TEXT_BASE 0xfffa0000 | |
| 62 | #endif | |
| 63 | ||
| 9e3ed392 | 64 | #undef CONFIG_RIO |
| fdc7eb90 PG |
65 | |
| 66 | #ifdef CONFIG_PCI | |
| 67 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 68 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
| 69 | #endif | |
| 70 | #ifdef CONFIG_PCIE1 | |
| 71 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 72 | #endif | |
| 9e3ed392 JH |
73 | |
| 74 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 75 | #define CONFIG_ENV_OVERWRITE | |
| 9e3ed392 | 76 | |
| 9e3ed392 JH |
77 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
| 78 | ||
| e2b159d0 | 79 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 9e3ed392 | 80 | |
| 2738bc8d PG |
81 | /* |
| 82 | * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] | |
| 83 | */ | |
| 84 | #ifndef CONFIG_SYS_CLK_DIV | |
| 85 | #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ | |
| 86 | #endif | |
| 87 | #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) | |
| 9e3ed392 JH |
88 | |
| 89 | /* | |
| 90 | * These can be toggled for performance analysis, otherwise use default. | |
| 91 | */ | |
| 92 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 93 | #define CONFIG_BTB /* toggle branch predition */ | |
| 9e3ed392 JH |
94 | |
| 95 | /* | |
| 96 | * Only possible on E500 Version 2 or newer cores. | |
| 97 | */ | |
| 98 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 99 | ||
| 100 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 101 | ||
| 6d0f6bcf JCPV |
102 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 103 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 104 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 9e3ed392 JH |
105 | |
| 106 | /* | |
| 107 | * Base addresses -- Note these are effective addresses where the | |
| 108 | * actual resources get mapped (not physical addresses) | |
| 109 | */ | |
| 6d0f6bcf JCPV |
110 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 111 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
| 112 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
| 113 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
| 9e3ed392 | 114 | |
| 33b9079b KG |
115 | /* DDR Setup */ |
| 116 | #define CONFIG_FSL_DDR2 | |
| 117 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 118 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 119 | #undef CONFIG_DDR_SPD | |
| 120 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
| 121 | ||
| 122 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 123 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 124 | ||
| 6d0f6bcf JCPV |
125 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 126 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 33b9079b KG |
127 | #define CONFIG_VERY_BIG_RAM |
| 128 | ||
| 129 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 130 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 131 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 9e3ed392 | 132 | |
| 33b9079b KG |
133 | /* I2C addresses of SPD EEPROMs */ |
| 134 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
| 9e3ed392 JH |
135 | |
| 136 | /* | |
| 137 | * Make sure required options are set | |
| 138 | */ | |
| 139 | #ifndef CONFIG_SPD_EEPROM | |
| 6d0f6bcf | 140 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 9e3ed392 JH |
141 | #endif |
| 142 | ||
| 143 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 144 | ||
| 145 | /* | |
| 146 | * FLASH on the Local Bus | |
| 147 | * Two banks, one 8MB the other 64MB, using the CFI driver. | |
| 148 | * Boot from BR0/OR0 bank at 0xff80_0000 | |
| 149 | * Alternate BR6/OR6 bank at 0xfb80_0000 | |
| 150 | * | |
| 151 | * BR0: | |
| 152 | * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 | |
| 153 | * Port Size = 8 bits = BRx[19:20] = 01 | |
| 154 | * Use GPCM = BRx[24:26] = 000 | |
| 155 | * Valid = BRx[31] = 1 | |
| 156 | * | |
| 157 | * 0 4 8 12 16 20 24 28 | |
| 158 | * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 | |
| 159 | * | |
| 160 | * BR6: | |
| 161 | * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 | |
| 162 | * Port Size = 32 bits = BRx[19:20] = 11 | |
| 163 | * Use GPCM = BRx[24:26] = 000 | |
| 164 | * Valid = BRx[31] = 1 | |
| 165 | * | |
| 166 | * 0 4 8 12 16 20 24 28 | |
| 167 | * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 | |
| 168 | * | |
| 169 | * OR0: | |
| 170 | * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 | |
| 171 | * XAM = OR0[17:18] = 11 | |
| 172 | * CSNT = OR0[20] = 1 | |
| 173 | * ACS = half cycle delay = OR0[21:22] = 11 | |
| 174 | * SCY = 6 = OR0[24:27] = 0110 | |
| 175 | * TRLX = use relaxed timing = OR0[29] = 1 | |
| 176 | * EAD = use external address latch delay = OR0[31] = 1 | |
| 177 | * | |
| 178 | * 0 4 8 12 16 20 24 28 | |
| 179 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 | |
| 180 | * | |
| 181 | * OR6: | |
| ccf1ad53 | 182 | * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 |
| 9e3ed392 JH |
183 | * XAM = OR6[17:18] = 11 |
| 184 | * CSNT = OR6[20] = 1 | |
| 185 | * ACS = half cycle delay = OR6[21:22] = 11 | |
| 186 | * SCY = 6 = OR6[24:27] = 0110 | |
| 187 | * TRLX = use relaxed timing = OR6[29] = 1 | |
| 188 | * EAD = use external address latch delay = OR6[31] = 1 | |
| 189 | * | |
| 190 | * 0 4 8 12 16 20 24 28 | |
| ccf1ad53 | 191 | * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 |
| 9e3ed392 JH |
192 | */ |
| 193 | ||
| 6d0f6bcf | 194 | #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ |
| 9b3ba24f | 195 | #define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ |
| 6d0f6bcf | 196 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ |
| 9e3ed392 | 197 | |
| 6d0f6bcf JCPV |
198 | #define CONFIG_SYS_BR0_PRELIM 0xff800801 |
| 199 | #define CONFIG_SYS_BR6_PRELIM 0xfb801801 | |
| 9e3ed392 | 200 | |
| 6d0f6bcf JCPV |
201 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
| 202 | #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 | |
| 9e3ed392 | 203 | |
| 9b3ba24f PG |
204 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ |
| 205 | CONFIG_SYS_ALT_FLASH} | |
| 206 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 207 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
| 6d0f6bcf JCPV |
208 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 209 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 210 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 9e3ed392 | 211 | |
| 14d0a02a | 212 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 9e3ed392 | 213 | |
| 00b1883a | 214 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
215 | #define CONFIG_SYS_FLASH_CFI |
| 216 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 9e3ed392 JH |
217 | |
| 218 | /* CS5 = Local bus peripherals controlled by the EPLD */ | |
| 219 | ||
| 6d0f6bcf JCPV |
220 | #define CONFIG_SYS_BR5_PRELIM 0xf8000801 |
| 221 | #define CONFIG_SYS_OR5_PRELIM 0xff006e65 | |
| 222 | #define CONFIG_SYS_EPLD_BASE 0xf8000000 | |
| 223 | #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 | |
| 224 | #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 | |
| 225 | #define CONFIG_SYS_BD_REV 0xf8300000 | |
| 226 | #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 | |
| 9e3ed392 JH |
227 | |
| 228 | /* | |
| 11d5a629 | 229 | * SDRAM on the Local Bus (CS3 and CS4) |
| 9e3ed392 | 230 | */ |
| 6d0f6bcf | 231 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| 11d5a629 | 232 | #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ |
| 9e3ed392 JH |
233 | |
| 234 | /* | |
| 11d5a629 | 235 | * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. |
| 6d0f6bcf | 236 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| 9e3ed392 JH |
237 | * |
| 238 | * For BR3, need: | |
| 239 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 240 | * port-size = 32-bits = BR2[19:20] = 11 | |
| 241 | * no parity checking = BR2[21:22] = 00 | |
| 242 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 243 | * Valid = BR[31] = 1 | |
| 244 | * | |
| 245 | * 0 4 8 12 16 20 24 28 | |
| 246 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
| 247 | * | |
| 248 | */ | |
| 249 | ||
| 6d0f6bcf | 250 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 |
| 9e3ed392 JH |
251 | |
| 252 | /* | |
| 11d5a629 | 253 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 9e3ed392 JH |
254 | * |
| 255 | * For OR3, need: | |
| 256 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
| 257 | * XAM, OR3[17:18] = 11 | |
| 258 | * 10 columns OR3[19-21] = 011 | |
| 259 | * 12 rows OR3[23-25] = 011 | |
| 260 | * EAD set for extra time OR[31] = 0 | |
| 261 | * | |
| 262 | * 0 4 8 12 16 20 24 28 | |
| 263 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
| 264 | */ | |
| 265 | ||
| 6d0f6bcf | 266 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 |
| 9e3ed392 | 267 | |
| 11d5a629 PG |
268 | /* |
| 269 | * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. | |
| 270 | * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. | |
| 271 | * | |
| 272 | * For BR4, need: | |
| 273 | * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 | |
| 274 | * port-size = 32-bits = BR2[19:20] = 11 | |
| 275 | * no parity checking = BR2[21:22] = 00 | |
| 276 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 277 | * Valid = BR[31] = 1 | |
| 278 | * | |
| 279 | * 0 4 8 12 16 20 24 28 | |
| 280 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 | |
| 281 | * | |
| 282 | */ | |
| 283 | ||
| 284 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 | |
| 285 | ||
| 286 | /* | |
| 287 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. | |
| 288 | * | |
| 289 | * For OR4, need: | |
| 290 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
| 291 | * XAM, OR3[17:18] = 11 | |
| 292 | * 10 columns OR3[19-21] = 011 | |
| 293 | * 12 rows OR3[23-25] = 011 | |
| 294 | * EAD set for extra time OR[31] = 0 | |
| 295 | * | |
| 296 | * 0 4 8 12 16 20 24 28 | |
| 297 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
| 298 | */ | |
| 299 | ||
| 300 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 | |
| 301 | ||
| 6d0f6bcf JCPV |
302 | #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ |
| 303 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
| 304 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
| 305 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
| 9e3ed392 | 306 | |
| 9e3ed392 JH |
307 | /* |
| 308 | * Common settings for all Local Bus SDRAM commands. | |
| 309 | * At run time, either BSMA1516 (for CPU 1.1) | |
| 310 | * or BSMA1617 (for CPU 1.0) (old) | |
| 311 | * is OR'ed in too. | |
| 312 | */ | |
| b0fe93ed KG |
313 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
| 314 | | LSDMR_PRETOACT7 \ | |
| 315 | | LSDMR_ACTTORW7 \ | |
| 316 | | LSDMR_BL8 \ | |
| 317 | | LSDMR_WRC4 \ | |
| 318 | | LSDMR_CL3 \ | |
| 319 | | LSDMR_RFEN \ | |
| 9e3ed392 JH |
320 | ) |
| 321 | ||
| 6d0f6bcf JCPV |
322 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 323 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
| 553f0982 | 324 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
| 9e3ed392 | 325 | |
| 6d0f6bcf | 326 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
| 9e3ed392 | 327 | |
| 6d0f6bcf | 328 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 553f0982 | 329 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) |
| 6d0f6bcf | 330 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 9e3ed392 | 331 | |
| dd9ca98f PG |
332 | /* |
| 333 | * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and | |
| 14d0a02a | 334 | * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM |
| dd9ca98f | 335 | * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg |
| 14d0a02a | 336 | * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right |
| dd9ca98f PG |
337 | * thing for MONITOR_LEN in both cases. |
| 338 | */ | |
| 14d0a02a | 339 | #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) |
| 6d0f6bcf | 340 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
| 9e3ed392 JH |
341 | |
| 342 | /* Serial Port */ | |
| 343 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
344 | #define CONFIG_SYS_NS16550 |
| 345 | #define CONFIG_SYS_NS16550_SERIAL | |
| 346 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 2738bc8d | 347 | #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) |
| 9e3ed392 | 348 | |
| 6d0f6bcf | 349 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 9e3ed392 JH |
350 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 351 | ||
| 6d0f6bcf JCPV |
352 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 353 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 9e3ed392 JH |
354 | |
| 355 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
356 | #define CONFIG_SYS_HUSH_PARSER |
| 357 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 358 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 9e3ed392 JH |
359 | #endif |
| 360 | ||
| 361 | /* pass open firmware flat tree */ | |
| 362 | #define CONFIG_OF_LIBFDT 1 | |
| 363 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 364 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 365 | ||
| 366 | /* | |
| 367 | * I2C | |
| 368 | */ | |
| 369 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 370 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 371 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 6d0f6bcf JCPV |
372 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 373 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
| 374 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 375 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 9e3ed392 JH |
376 | |
| 377 | /* | |
| 378 | * General PCI | |
| 379 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 380 | */ | |
| fdc7eb90 | 381 | #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ |
| 6d0f6bcf | 382 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
| 9e3ed392 | 383 | |
| fdc7eb90 PG |
384 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
| 385 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 | |
| 386 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
| 6d0f6bcf | 387 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| fdc7eb90 PG |
388 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
| 389 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
| 390 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 | |
| 391 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
| 9e3ed392 JH |
392 | |
| 393 | #ifdef CONFIG_PCIE1 | |
| fdc7eb90 PG |
394 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
| 395 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
| 396 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
| 6d0f6bcf | 397 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| fdc7eb90 PG |
398 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
| 399 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 400 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
| 401 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
| 9e3ed392 JH |
402 | #endif |
| 403 | ||
| 404 | #ifdef CONFIG_RIO | |
| 405 | /* | |
| 406 | * RapidIO MMU | |
| 407 | */ | |
| 6d0f6bcf JCPV |
408 | #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 |
| 409 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ | |
| 9e3ed392 JH |
410 | #endif |
| 411 | ||
| 9e3ed392 JH |
412 | #if defined(CONFIG_PCI) |
| 413 | ||
| 414 | #define CONFIG_NET_MULTI | |
| 415 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 416 | ||
| 417 | #undef CONFIG_EEPRO100 | |
| 418 | #undef CONFIG_TULIP | |
| 419 | ||
| fdc7eb90 | 420 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 9e3ed392 | 421 | |
| 9e3ed392 JH |
422 | #endif /* CONFIG_PCI */ |
| 423 | ||
| 424 | ||
| 425 | #if defined(CONFIG_TSEC_ENET) | |
| 426 | ||
| 427 | #ifndef CONFIG_NET_MULTI | |
| 428 | #define CONFIG_NET_MULTI 1 | |
| 429 | #endif | |
| 430 | ||
| 431 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 432 | #define CONFIG_TSEC1 1 | |
| 433 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
| 434 | #define CONFIG_TSEC2 1 | |
| 435 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
| 9e3ed392 JH |
436 | #undef CONFIG_MPC85XX_FEC |
| 437 | ||
| 58da8890 PG |
438 | #define TSEC1_PHY_ADDR 0x19 |
| 439 | #define TSEC2_PHY_ADDR 0x1a | |
| 9e3ed392 JH |
440 | |
| 441 | #define TSEC1_PHYIDX 0 | |
| 442 | #define TSEC2_PHYIDX 0 | |
| bd93105f | 443 | |
| 9e3ed392 JH |
444 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 445 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 9e3ed392 JH |
446 | |
| 447 | /* Options are: eTSEC[0-3] */ | |
| 448 | #define CONFIG_ETHPRIME "eTSEC0" | |
| 449 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 450 | #endif /* CONFIG_TSEC_ENET */ | |
| 451 | ||
| 452 | /* | |
| 453 | * Environment | |
| 454 | */ | |
| 5a1aceb0 | 455 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 | 456 | #define CONFIG_ENV_SIZE 0x2000 |
| 14d0a02a | 457 | #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ |
| dd9ca98f PG |
458 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) |
| 459 | #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ | |
| 14d0a02a | 460 | #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ |
| dd9ca98f PG |
461 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
| 462 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
| 463 | #else | |
| 464 | #warning undefined environment size/location. | |
| 465 | #endif | |
| 9e3ed392 JH |
466 | |
| 467 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 468 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 9e3ed392 JH |
469 | |
| 470 | /* | |
| 471 | * BOOTP options | |
| 472 | */ | |
| 473 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 474 | #define CONFIG_BOOTP_BOOTPATH | |
| 475 | #define CONFIG_BOOTP_GATEWAY | |
| 476 | #define CONFIG_BOOTP_HOSTNAME | |
| 477 | ||
| 478 | ||
| 479 | /* | |
| 480 | * Command line configuration. | |
| 481 | */ | |
| 482 | #include <config_cmd_default.h> | |
| 483 | ||
| 484 | #define CONFIG_CMD_PING | |
| 485 | #define CONFIG_CMD_I2C | |
| 486 | #define CONFIG_CMD_MII | |
| 487 | #define CONFIG_CMD_ELF | |
| 199e262e | 488 | #define CONFIG_CMD_REGINFO |
| 9e3ed392 JH |
489 | |
| 490 | #if defined(CONFIG_PCI) | |
| 491 | #define CONFIG_CMD_PCI | |
| 492 | #endif | |
| 493 | ||
| 494 | ||
| 495 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 496 | ||
| 497 | /* | |
| 498 | * Miscellaneous configurable options | |
| 499 | */ | |
| ad22f927 | 500 | #define CONFIG_CMDLINE_EDITING /* undef to save memory */ |
| 5be58f5f | 501 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 6d0f6bcf JCPV |
502 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 503 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 504 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 9e3ed392 | 505 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 506 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 9e3ed392 | 507 | #else |
| 6d0f6bcf | 508 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 9e3ed392 | 509 | #endif |
| 6d0f6bcf JCPV |
510 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 511 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 512 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 513 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 9e3ed392 JH |
514 | |
| 515 | /* | |
| 516 | * For booting Linux, the board info and command line data | |
| 517 | * have to be in the first 8 MB of memory, since this is | |
| 518 | * the maximum mapped by the Linux kernel during initialization. | |
| 519 | */ | |
| 6d0f6bcf | 520 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 9e3ed392 | 521 | |
| 9e3ed392 JH |
522 | #if defined(CONFIG_CMD_KGDB) |
| 523 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 524 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 525 | #endif | |
| 526 | ||
| 527 | /* | |
| 528 | * Environment Configuration | |
| 529 | */ | |
| 530 | ||
| 531 | /* The mac addresses for all ethernet interface */ | |
| 532 | #if defined(CONFIG_TSEC_ENET) | |
| 533 | #define CONFIG_HAS_ETH0 | |
| 534 | #define CONFIG_ETHADDR 02:E0:0C:00:00:FD | |
| 535 | #define CONFIG_HAS_ETH1 | |
| 536 | #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD | |
| 9e3ed392 JH |
537 | #endif |
| 538 | ||
| 539 | #define CONFIG_IPADDR 192.168.0.55 | |
| 540 | ||
| 541 | #define CONFIG_HOSTNAME sbc8548 | |
| 542 | #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx | |
| 543 | #define CONFIG_BOOTFILE /uImage | |
| 544 | #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ | |
| 545 | ||
| 546 | #define CONFIG_SERVERIP 192.168.0.2 | |
| 547 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
| 548 | #define CONFIG_NETMASK 255.255.255.0 | |
| 549 | ||
| 550 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
| 551 | ||
| 552 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 553 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
| 554 | ||
| 555 | #define CONFIG_BAUDRATE 115200 | |
| 556 | ||
| 557 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 558 | "netdev=eth0\0" \ | |
| 559 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 560 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 14d0a02a WD |
561 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 562 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 563 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
| 564 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 565 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
| 9e3ed392 JH |
566 | "consoledev=ttyS0\0" \ |
| 567 | "ramdiskaddr=2000000\0" \ | |
| 568 | "ramdiskfile=uRamdisk\0" \ | |
| 569 | "fdtaddr=c00000\0" \ | |
| 570 | "fdtfile=sbc8548.dtb\0" | |
| 571 | ||
| 572 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 573 | "setenv bootargs root=/dev/nfs rw " \ | |
| 574 | "nfsroot=$serverip:$rootpath " \ | |
| 575 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 576 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 577 | "tftp $loadaddr $bootfile;" \ | |
| 578 | "tftp $fdtaddr $fdtfile;" \ | |
| 579 | "bootm $loadaddr - $fdtaddr" | |
| 580 | ||
| 581 | ||
| 582 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 583 | "setenv bootargs root=/dev/ram rw " \ | |
| 584 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 585 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 586 | "tftp $loadaddr $bootfile;" \ | |
| 587 | "tftp $fdtaddr $fdtfile;" \ | |
| 588 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 589 | ||
| 590 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 591 | ||
| 592 | #endif /* __CONFIG_H */ |