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9e3ed392 | 1 | /* |
2738bc8d | 2 | * Copyright 2007,2009 Wind River Systems <www.windriver.com> |
9e3ed392 JH |
3 | * Copyright 2007 Embedded Specialties, Inc. |
4 | * Copyright 2004, 2007 Freescale Semiconductor. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * sbc8548 board configuration file | |
2738bc8d | 27 | * Please refer to doc/README.sbc8548 for more info. |
9e3ed392 JH |
28 | */ |
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
2738bc8d PG |
32 | /* |
33 | * Top level Makefile configuration choices | |
34 | */ | |
35 | #ifdef CONFIG_MK_PCI | |
36 | #define CONFIG_PCI | |
37 | #define CONFIG_PCI1 | |
38 | #endif | |
39 | ||
40 | #ifdef CONFIG_MK_66 | |
41 | #define CONFIG_SYS_CLK_DIV 1 | |
42 | #endif | |
43 | ||
44 | #ifdef CONFIG_MK_33 | |
45 | #define CONFIG_SYS_CLK_DIV 2 | |
46 | #endif | |
47 | ||
48 | #ifdef CONFIG_MK_PCIE | |
49 | #define CONFIG_PCIE1 | |
50 | #endif | |
51 | ||
52 | /* | |
53 | * High Level Configuration Options | |
54 | */ | |
9e3ed392 JH |
55 | #define CONFIG_BOOKE 1 /* BOOKE */ |
56 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
57 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
58 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ | |
59 | #define CONFIG_SBC8548 1 /* SBC8548 board specific */ | |
60 | ||
9e3ed392 | 61 | #undef CONFIG_RIO |
fdc7eb90 PG |
62 | |
63 | #ifdef CONFIG_PCI | |
64 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
65 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
66 | #endif | |
67 | #ifdef CONFIG_PCIE1 | |
68 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
69 | #endif | |
9e3ed392 JH |
70 | |
71 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
72 | #define CONFIG_ENV_OVERWRITE | |
9e3ed392 | 73 | |
9e3ed392 JH |
74 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
75 | ||
e2b159d0 | 76 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
9e3ed392 | 77 | |
2738bc8d PG |
78 | /* |
79 | * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] | |
80 | */ | |
81 | #ifndef CONFIG_SYS_CLK_DIV | |
82 | #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ | |
83 | #endif | |
84 | #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) | |
9e3ed392 JH |
85 | |
86 | /* | |
87 | * These can be toggled for performance analysis, otherwise use default. | |
88 | */ | |
89 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
90 | #define CONFIG_BTB /* toggle branch predition */ | |
9e3ed392 JH |
91 | |
92 | /* | |
93 | * Only possible on E500 Version 2 or newer cores. | |
94 | */ | |
95 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
96 | ||
97 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
98 | ||
6d0f6bcf JCPV |
99 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
100 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
101 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
9e3ed392 JH |
102 | |
103 | /* | |
104 | * Base addresses -- Note these are effective addresses where the | |
105 | * actual resources get mapped (not physical addresses) | |
106 | */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
108 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
109 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
110 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
9e3ed392 | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
113 | #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) | |
114 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) | |
9e3ed392 | 115 | |
33b9079b KG |
116 | /* DDR Setup */ |
117 | #define CONFIG_FSL_DDR2 | |
118 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
119 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
120 | #undef CONFIG_DDR_SPD | |
121 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
122 | ||
123 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
124 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
125 | ||
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
127 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
33b9079b KG |
128 | #define CONFIG_VERY_BIG_RAM |
129 | ||
130 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
131 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
132 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
9e3ed392 | 133 | |
33b9079b KG |
134 | /* I2C addresses of SPD EEPROMs */ |
135 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
9e3ed392 JH |
136 | |
137 | /* | |
138 | * Make sure required options are set | |
139 | */ | |
140 | #ifndef CONFIG_SPD_EEPROM | |
6d0f6bcf | 141 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
9e3ed392 JH |
142 | #endif |
143 | ||
144 | #undef CONFIG_CLOCKS_IN_MHZ | |
145 | ||
146 | /* | |
147 | * FLASH on the Local Bus | |
148 | * Two banks, one 8MB the other 64MB, using the CFI driver. | |
149 | * Boot from BR0/OR0 bank at 0xff80_0000 | |
150 | * Alternate BR6/OR6 bank at 0xfb80_0000 | |
151 | * | |
152 | * BR0: | |
153 | * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 | |
154 | * Port Size = 8 bits = BRx[19:20] = 01 | |
155 | * Use GPCM = BRx[24:26] = 000 | |
156 | * Valid = BRx[31] = 1 | |
157 | * | |
158 | * 0 4 8 12 16 20 24 28 | |
159 | * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 | |
160 | * | |
161 | * BR6: | |
162 | * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 | |
163 | * Port Size = 32 bits = BRx[19:20] = 11 | |
164 | * Use GPCM = BRx[24:26] = 000 | |
165 | * Valid = BRx[31] = 1 | |
166 | * | |
167 | * 0 4 8 12 16 20 24 28 | |
168 | * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 | |
169 | * | |
170 | * OR0: | |
171 | * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 | |
172 | * XAM = OR0[17:18] = 11 | |
173 | * CSNT = OR0[20] = 1 | |
174 | * ACS = half cycle delay = OR0[21:22] = 11 | |
175 | * SCY = 6 = OR0[24:27] = 0110 | |
176 | * TRLX = use relaxed timing = OR0[29] = 1 | |
177 | * EAD = use external address latch delay = OR0[31] = 1 | |
178 | * | |
179 | * 0 4 8 12 16 20 24 28 | |
180 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 | |
181 | * | |
182 | * OR6: | |
ccf1ad53 | 183 | * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 |
9e3ed392 JH |
184 | * XAM = OR6[17:18] = 11 |
185 | * CSNT = OR6[20] = 1 | |
186 | * ACS = half cycle delay = OR6[21:22] = 11 | |
187 | * SCY = 6 = OR6[24:27] = 0110 | |
188 | * TRLX = use relaxed timing = OR6[29] = 1 | |
189 | * EAD = use external address latch delay = OR6[31] = 1 | |
190 | * | |
191 | * 0 4 8 12 16 20 24 28 | |
ccf1ad53 | 192 | * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 |
9e3ed392 JH |
193 | */ |
194 | ||
6d0f6bcf | 195 | #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ |
9b3ba24f | 196 | #define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ |
6d0f6bcf | 197 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ |
9e3ed392 | 198 | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_BR0_PRELIM 0xff800801 |
200 | #define CONFIG_SYS_BR6_PRELIM 0xfb801801 | |
9e3ed392 | 201 | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
203 | #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 | |
9e3ed392 | 204 | |
9b3ba24f PG |
205 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ |
206 | CONFIG_SYS_ALT_FLASH} | |
207 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
208 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
6d0f6bcf JCPV |
209 | #undef CONFIG_SYS_FLASH_CHECKSUM |
210 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
211 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
9e3ed392 | 212 | |
6d0f6bcf | 213 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
9e3ed392 | 214 | |
00b1883a | 215 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH_CFI |
217 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
9e3ed392 JH |
218 | |
219 | /* CS5 = Local bus peripherals controlled by the EPLD */ | |
220 | ||
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_BR5_PRELIM 0xf8000801 |
222 | #define CONFIG_SYS_OR5_PRELIM 0xff006e65 | |
223 | #define CONFIG_SYS_EPLD_BASE 0xf8000000 | |
224 | #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 | |
225 | #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 | |
226 | #define CONFIG_SYS_BD_REV 0xf8300000 | |
227 | #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 | |
9e3ed392 JH |
228 | |
229 | /* | |
11d5a629 | 230 | * SDRAM on the Local Bus (CS3 and CS4) |
9e3ed392 | 231 | */ |
6d0f6bcf | 232 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
11d5a629 | 233 | #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ |
9e3ed392 JH |
234 | |
235 | /* | |
11d5a629 | 236 | * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. |
6d0f6bcf | 237 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
9e3ed392 JH |
238 | * |
239 | * For BR3, need: | |
240 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
241 | * port-size = 32-bits = BR2[19:20] = 11 | |
242 | * no parity checking = BR2[21:22] = 00 | |
243 | * SDRAM for MSEL = BR2[24:26] = 011 | |
244 | * Valid = BR[31] = 1 | |
245 | * | |
246 | * 0 4 8 12 16 20 24 28 | |
247 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
248 | * | |
249 | */ | |
250 | ||
6d0f6bcf | 251 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 |
9e3ed392 JH |
252 | |
253 | /* | |
11d5a629 | 254 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
9e3ed392 JH |
255 | * |
256 | * For OR3, need: | |
257 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
258 | * XAM, OR3[17:18] = 11 | |
259 | * 10 columns OR3[19-21] = 011 | |
260 | * 12 rows OR3[23-25] = 011 | |
261 | * EAD set for extra time OR[31] = 0 | |
262 | * | |
263 | * 0 4 8 12 16 20 24 28 | |
264 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
265 | */ | |
266 | ||
6d0f6bcf | 267 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 |
9e3ed392 | 268 | |
11d5a629 PG |
269 | /* |
270 | * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. | |
271 | * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. | |
272 | * | |
273 | * For BR4, need: | |
274 | * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 | |
275 | * port-size = 32-bits = BR2[19:20] = 11 | |
276 | * no parity checking = BR2[21:22] = 00 | |
277 | * SDRAM for MSEL = BR2[24:26] = 011 | |
278 | * Valid = BR[31] = 1 | |
279 | * | |
280 | * 0 4 8 12 16 20 24 28 | |
281 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 | |
282 | * | |
283 | */ | |
284 | ||
285 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 | |
286 | ||
287 | /* | |
288 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. | |
289 | * | |
290 | * For OR4, need: | |
291 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
292 | * XAM, OR3[17:18] = 11 | |
293 | * 10 columns OR3[19-21] = 011 | |
294 | * 12 rows OR3[23-25] = 011 | |
295 | * EAD set for extra time OR[31] = 0 | |
296 | * | |
297 | * 0 4 8 12 16 20 24 28 | |
298 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
299 | */ | |
300 | ||
301 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 | |
302 | ||
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ |
304 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
305 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
306 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
9e3ed392 | 307 | |
9e3ed392 JH |
308 | /* |
309 | * Common settings for all Local Bus SDRAM commands. | |
310 | * At run time, either BSMA1516 (for CPU 1.1) | |
311 | * or BSMA1617 (for CPU 1.0) (old) | |
312 | * is OR'ed in too. | |
313 | */ | |
b0fe93ed KG |
314 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
315 | | LSDMR_PRETOACT7 \ | |
316 | | LSDMR_ACTTORW7 \ | |
317 | | LSDMR_BL8 \ | |
318 | | LSDMR_WRC4 \ | |
319 | | LSDMR_CL3 \ | |
320 | | LSDMR_RFEN \ | |
9e3ed392 JH |
321 | ) |
322 | ||
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
324 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
325 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
9e3ed392 | 326 | |
6d0f6bcf | 327 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
9e3ed392 | 328 | |
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
330 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
331 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
9e3ed392 | 332 | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
334 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
9e3ed392 JH |
335 | |
336 | /* Serial Port */ | |
337 | #define CONFIG_CONS_INDEX 1 | |
338 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_NS16550 |
340 | #define CONFIG_SYS_NS16550_SERIAL | |
341 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
2738bc8d | 342 | #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) |
9e3ed392 | 343 | |
6d0f6bcf | 344 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9e3ed392 JH |
345 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
346 | ||
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
348 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
9e3ed392 JH |
349 | |
350 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_HUSH_PARSER |
352 | #ifdef CONFIG_SYS_HUSH_PARSER | |
353 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
9e3ed392 JH |
354 | #endif |
355 | ||
356 | /* pass open firmware flat tree */ | |
357 | #define CONFIG_OF_LIBFDT 1 | |
358 | #define CONFIG_OF_BOARD_SETUP 1 | |
359 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
360 | ||
361 | /* | |
362 | * I2C | |
363 | */ | |
364 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
365 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
366 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
368 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
369 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
370 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
9e3ed392 JH |
371 | |
372 | /* | |
373 | * General PCI | |
374 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
375 | */ | |
fdc7eb90 | 376 | #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ |
6d0f6bcf | 377 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
9e3ed392 | 378 | |
fdc7eb90 PG |
379 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
380 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 | |
381 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
6d0f6bcf | 382 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
fdc7eb90 PG |
383 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
384 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
385 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 | |
386 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
9e3ed392 JH |
387 | |
388 | #ifdef CONFIG_PCIE1 | |
fdc7eb90 PG |
389 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
390 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
391 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
6d0f6bcf | 392 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
fdc7eb90 PG |
393 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
394 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
395 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
396 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
9e3ed392 JH |
397 | #endif |
398 | ||
399 | #ifdef CONFIG_RIO | |
400 | /* | |
401 | * RapidIO MMU | |
402 | */ | |
6d0f6bcf JCPV |
403 | #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 |
404 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ | |
9e3ed392 JH |
405 | #endif |
406 | ||
9e3ed392 JH |
407 | #if defined(CONFIG_PCI) |
408 | ||
409 | #define CONFIG_NET_MULTI | |
410 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
411 | ||
412 | #undef CONFIG_EEPRO100 | |
413 | #undef CONFIG_TULIP | |
414 | ||
fdc7eb90 | 415 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
9e3ed392 | 416 | |
9e3ed392 JH |
417 | #endif /* CONFIG_PCI */ |
418 | ||
419 | ||
420 | #if defined(CONFIG_TSEC_ENET) | |
421 | ||
422 | #ifndef CONFIG_NET_MULTI | |
423 | #define CONFIG_NET_MULTI 1 | |
424 | #endif | |
425 | ||
426 | #define CONFIG_MII 1 /* MII PHY management */ | |
427 | #define CONFIG_TSEC1 1 | |
428 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
429 | #define CONFIG_TSEC2 1 | |
430 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
9e3ed392 JH |
431 | #undef CONFIG_MPC85XX_FEC |
432 | ||
58da8890 PG |
433 | #define TSEC1_PHY_ADDR 0x19 |
434 | #define TSEC2_PHY_ADDR 0x1a | |
9e3ed392 JH |
435 | |
436 | #define TSEC1_PHYIDX 0 | |
437 | #define TSEC2_PHYIDX 0 | |
bd93105f | 438 | |
9e3ed392 JH |
439 | #define TSEC1_FLAGS TSEC_GIGABIT |
440 | #define TSEC2_FLAGS TSEC_GIGABIT | |
9e3ed392 JH |
441 | |
442 | /* Options are: eTSEC[0-3] */ | |
443 | #define CONFIG_ETHPRIME "eTSEC0" | |
444 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
445 | #endif /* CONFIG_TSEC_ENET */ | |
446 | ||
447 | /* | |
448 | * Environment | |
449 | */ | |
5a1aceb0 | 450 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 451 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
452 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
453 | #define CONFIG_ENV_SIZE 0x2000 | |
9e3ed392 JH |
454 | |
455 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 456 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9e3ed392 JH |
457 | |
458 | /* | |
459 | * BOOTP options | |
460 | */ | |
461 | #define CONFIG_BOOTP_BOOTFILESIZE | |
462 | #define CONFIG_BOOTP_BOOTPATH | |
463 | #define CONFIG_BOOTP_GATEWAY | |
464 | #define CONFIG_BOOTP_HOSTNAME | |
465 | ||
466 | ||
467 | /* | |
468 | * Command line configuration. | |
469 | */ | |
470 | #include <config_cmd_default.h> | |
471 | ||
472 | #define CONFIG_CMD_PING | |
473 | #define CONFIG_CMD_I2C | |
474 | #define CONFIG_CMD_MII | |
475 | #define CONFIG_CMD_ELF | |
476 | ||
477 | #if defined(CONFIG_PCI) | |
478 | #define CONFIG_CMD_PCI | |
479 | #endif | |
480 | ||
481 | ||
482 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
483 | ||
484 | /* | |
485 | * Miscellaneous configurable options | |
486 | */ | |
ad22f927 | 487 | #define CONFIG_CMDLINE_EDITING /* undef to save memory */ |
6d0f6bcf JCPV |
488 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
489 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
490 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
9e3ed392 | 491 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 492 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9e3ed392 | 493 | #else |
6d0f6bcf | 494 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9e3ed392 | 495 | #endif |
6d0f6bcf JCPV |
496 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
497 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
498 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
499 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
9e3ed392 JH |
500 | |
501 | /* | |
502 | * For booting Linux, the board info and command line data | |
503 | * have to be in the first 8 MB of memory, since this is | |
504 | * the maximum mapped by the Linux kernel during initialization. | |
505 | */ | |
6d0f6bcf | 506 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
9e3ed392 | 507 | |
9e3ed392 JH |
508 | /* |
509 | * Internal Definitions | |
510 | * | |
511 | * Boot Flags | |
512 | */ | |
513 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
514 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
515 | ||
516 | #if defined(CONFIG_CMD_KGDB) | |
517 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
518 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
519 | #endif | |
520 | ||
521 | /* | |
522 | * Environment Configuration | |
523 | */ | |
524 | ||
525 | /* The mac addresses for all ethernet interface */ | |
526 | #if defined(CONFIG_TSEC_ENET) | |
527 | #define CONFIG_HAS_ETH0 | |
528 | #define CONFIG_ETHADDR 02:E0:0C:00:00:FD | |
529 | #define CONFIG_HAS_ETH1 | |
530 | #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD | |
9e3ed392 JH |
531 | #endif |
532 | ||
533 | #define CONFIG_IPADDR 192.168.0.55 | |
534 | ||
535 | #define CONFIG_HOSTNAME sbc8548 | |
536 | #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx | |
537 | #define CONFIG_BOOTFILE /uImage | |
538 | #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ | |
539 | ||
540 | #define CONFIG_SERVERIP 192.168.0.2 | |
541 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
542 | #define CONFIG_NETMASK 255.255.255.0 | |
543 | ||
544 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
545 | ||
546 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
547 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
548 | ||
549 | #define CONFIG_BAUDRATE 115200 | |
550 | ||
551 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
552 | "netdev=eth0\0" \ | |
553 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
554 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
555 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
556 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
557 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
558 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
559 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
560 | "consoledev=ttyS0\0" \ | |
561 | "ramdiskaddr=2000000\0" \ | |
562 | "ramdiskfile=uRamdisk\0" \ | |
563 | "fdtaddr=c00000\0" \ | |
564 | "fdtfile=sbc8548.dtb\0" | |
565 | ||
566 | #define CONFIG_NFSBOOTCOMMAND \ | |
567 | "setenv bootargs root=/dev/nfs rw " \ | |
568 | "nfsroot=$serverip:$rootpath " \ | |
569 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
570 | "console=$consoledev,$baudrate $othbootargs;" \ | |
571 | "tftp $loadaddr $bootfile;" \ | |
572 | "tftp $fdtaddr $fdtfile;" \ | |
573 | "bootm $loadaddr - $fdtaddr" | |
574 | ||
575 | ||
576 | #define CONFIG_RAMBOOTCOMMAND \ | |
577 | "setenv bootargs root=/dev/ram rw " \ | |
578 | "console=$consoledev,$baudrate $othbootargs;" \ | |
579 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
580 | "tftp $loadaddr $bootfile;" \ | |
581 | "tftp $fdtaddr $fdtfile;" \ | |
582 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
583 | ||
584 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
585 | ||
586 | #endif /* __CONFIG_H */ |