[thirdparty/u-boot.git] / include / configs / sbc8548.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
 * Copyright 2007 Embedded Specialties, Inc.
 * Copyright 2004, 2007 Freescale Semiconductor.
 */

/*
 * sbc8548 board configuration file
 * Please refer to board/sbc8548/README for more info.
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Top level Makefile configuration choices
 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI1
#endif

#ifdef CONFIG_66
#define CONFIG_SYS_CLK_DIV 1
#endif

#ifdef CONFIG_33
#define CONFIG_SYS_CLK_DIV 2
#endif

#ifdef CONFIG_PCIE
#define CONFIG_PCIE1
#endif

/*
 * High Level Configuration Options
 */

/*
 * If you want to boot from the SODIMM flash, instead of the soldered
 * on flash, set this, and change JP12, SW2:8 accordingly.
 */
#undef CONFIG_SYS_ALT_BOOT

#undef CONFIG_RIO

#ifdef CONFIG_PCI
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT    1	/* enable 64-bit PCI resources */
#endif

#define CONFIG_ENV_OVERWRITE

#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

/*
 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
 */
#ifndef CONFIG_SYS_CLK_DIV
#define CONFIG_SYS_CLK_DIV	1	/* 2, if 33MHz PCI card installed */
#endif
#define CONFIG_SYS_CLK_FREQ	(66000000 / CONFIG_SYS_CLK_DIV)

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
/*
 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
 * to collide, meaning you couldn't reliably read either. So
 * physically remove the LBC PC100 SDRAM module from the board
 * before enabling the two SPD options below, or check that you
 * have the hardware fix on your board via "i2c probe" and looking
 * for a device at 0x53.
 */
#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD

#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/*
 * The hardware fix for the I2C address collision puts the DDR
 * SPD at 0x53, but if we are running on an older board w/o the
 * fix, it will still be at 0x51.  We check 0x53 1st.
 */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
#define ALT_SPD_EEPROM_ADDRESS	0x53	/* CTLR 0 DIMM 0 */

/*
 * Make sure required options are set
 */
#ifndef CONFIG_SPD_EEPROM
	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
	#define CONFIG_SYS_DDR_CONTROL	0xc300c000
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * FLASH on the Local Bus
 * Two banks, one 8MB the other 64MB, using the CFI driver.
 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
 * CS0 the 8MB boot flash, and CS6 the 64MB flash.
 *
 *	Default:
 *	ec00_0000	efff_ffff	64MB SODIMM
 *	ff80_0000	ffff_ffff	8MB soldered flash
 *
 *	Alternate:
 *	ef80_0000	efff_ffff	8MB soldered flash
 *	fc00_0000	ffff_ffff	64MB SODIMM
 *
 * BR0_8M:
 *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 8 bits = BRx[19:20] = 01
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * BR0_64M:
 *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
 *    Port Size = 32 bits = BRx[19:20] = 11
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
 */
#define CONFIG_SYS_BR0_8M	0xff800801
#define CONFIG_SYS_BR0_64M	0xfc001801

/*
 * BR6_8M:
 *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
 *    Port Size = 8 bits = BRx[19:20] = 01
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1

 * BR6_64M:
 *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
 *    Port Size = 32 bits = BRx[19:20] = 11
 *
 * 0    4    8    12   16   20   24   28
 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
 */
#define CONFIG_SYS_BR6_8M	0xef800801
#define CONFIG_SYS_BR6_64M	0xec001801

/*
 * OR0_8M:
 *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 *    XAM = OR0[17:18] = 11
 *    CSNT = OR0[20] = 1
 *    ACS = half cycle delay = OR0[21:22] = 11
 *    SCY = 6 = OR0[24:27] = 0110
 *    TRLX = use relaxed timing = OR0[29] = 1
 *    EAD = use external address latch delay = OR0[31] = 1
 *
 * OR0_64M:
 *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
 *
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
 */
#define CONFIG_SYS_OR0_8M	0xff806e65
#define CONFIG_SYS_OR0_64M	0xfc006e65

/*
 * OR6_8M:
 *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
 *    XAM = OR6[17:18] = 11
 *    CSNT = OR6[20] = 1
 *    ACS = half cycle delay = OR6[21:22] = 11
 *    SCY = 6 = OR6[24:27] = 0110
 *    TRLX = use relaxed timing = OR6[29] = 1
 *    EAD = use external address latch delay = OR6[31] = 1
 *
 * OR6_64M:
 *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
 */
#define CONFIG_SYS_OR6_8M	0xff806e65
#define CONFIG_SYS_OR6_64M	0xfc006e65

#ifndef CONFIG_SYS_ALT_BOOT		/* JP12 in default position */
#define CONFIG_SYS_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
#define CONFIG_SYS_ALT_FLASH		0xec000000	/* 64MB "user" flash */

#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_8M
#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_8M

#define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_64M
#define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_64M
#else					/* JP12 in alternate position */
#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* start 64MB Flash */
#define CONFIG_SYS_ALT_FLASH		0xef800000	/* 8MB soldered flash */

#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_64M
#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_64M

#define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_8M
#define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_8M
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
					 CONFIG_SYS_ALT_FLASH}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_SYS_FLASH_EMPTY_INFO

/* CS5 = Local bus peripherals controlled by the EPLD */

#define CONFIG_SYS_BR5_PRELIM		0xf8000801
#define CONFIG_SYS_OR5_PRELIM		0xff006e65
#define CONFIG_SYS_EPLD_BASE		0xf8000000
#define CONFIG_SYS_LED_DISP_BASE	0xf8000000
#define CONFIG_SYS_USER_SWITCHES_BASE	0xf8100000
#define CONFIG_SYS_BD_REV		0xf8300000
#define CONFIG_SYS_EEPROM_BASE		0xf8b00000

/*
 * SDRAM on the Local Bus (CS3 and CS4)
 * Note that most boards have a hardware errata where both the
 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
 * A hardware workaround is also available, see README.sbc8548 file.
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */

/*
 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR3, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 */

#define CONFIG_SYS_BR3_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR3, need:
 *    64MB mask for AM, OR3[0:7] = 1111 1100
 *		   XAM, OR3[17:18] = 11
 *    10 columns OR3[19-21] = 011
 *    12 rows   OR3[23-25] = 011
 *    EAD set for extra time OR[31] = 0
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 */

#define CONFIG_SYS_OR3_PRELIM		0xfc006cc0

/*
 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
 *
 * For BR4, need:
 *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
 *
 */

#define CONFIG_SYS_BR4_PRELIM		0xf4001861

/*
 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR4, need:
 *    64MB mask for AM, OR3[0:7] = 1111 1100
 *		   XAM, OR3[17:18] = 11
 *    10 columns OR3[19-21] = 011
 *    12 rows   OR3[23-25] = 011
 *    EAD set for extra time OR[31] = 0
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 */

#define CONFIG_SYS_OR4_PRELIM		0xfc006cc0

#define CONFIG_SYS_LBC_LCRR		0x00000002    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_BSMA1516	\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BUFCMD		\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				)

#define CONFIG_SYS_LBC_LSDMR_PCHALL	\
	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_ARFRSH	\
	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_MRW	\
	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_RFEN	\
	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
 * thing for MONITOR_LEN in both cases.
 */
#define CONFIG_SYS_MONITOR_LEN		(~CONFIG_SYS_TEXT_BASE + 1)
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024) /* Reserved for malloc */

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(400000000 / CONFIG_SYS_CLK_DIV)

#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI_VIRT		0x80000000	/* 1G PCI TLB */
#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */

#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT		0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 8M */

#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
#endif

#ifdef CONFIG_RIO
/*
 * RapidIO MMU
 */
#define CONFIG_SYS_RIO_MEM_BASE	0xC0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
#endif

#if defined(CONFIG_PCI)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#undef CONFIG_MPC85XX_FEC

#define TSEC1_PHY_ADDR		0x19
#define TSEC2_PHY_ADDR		0x1a

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME		"eTSEC0"
#endif	/* CONFIG_TSEC_ENET */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_IPADDR	 192.168.0.55

#define CONFIG_HOSTNAME	 "sbc8548"
#define CONFIG_ROOTPATH	 "/opt/eldk/ppc_85xx"
#define CONFIG_BOOTFILE	 "/uImage"
#define CONFIG_UBOOTPATH /u-boot.bin	/* TFTP server */

#define CONFIG_SERVERIP	 192.168.0.2
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_NETMASK	 255.255.255.0

#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/

#define	CONFIG_EXTRA_ENV_SETTINGS				\
"netdev=eth0\0"						\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
"tftpflash=tftpboot $loadaddr $uboot; "			\
	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0"				\
"ramdiskaddr=2000000\0"			\
"ramdiskfile=uRamdisk\0"			\
"fdtaddr=1e00000\0"				\
"fdtfile=sbc8548.dtb\0"

#define CONFIG_NFSBOOTCOMMAND						\
   "setenv bootargs root=/dev/nfs rw "					\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "					\
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $ramdiskaddr $ramdiskfile;"					\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
9e3ed392	2	/*
2738bc8d	3	* Copyright 2007,2009 Wind River Systems <www.windriver.com>
9e3ed392 JH	4	* Copyright 2007 Embedded Specialties, Inc.
9e3ed392 JH	5	* Copyright 2004, 2007 Freescale Semiconductor.
9e3ed392 JH	6	*/
	7
	8	/*
	9	* sbc8548 board configuration file
add83917	10	* Please refer to board/sbc8548/README for more info.
9e3ed392 JH	11	*/
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
2738bc8d PG	15	/*
	16	* Top level Makefile configuration choices
	17	*/
d24f2d32	18	#ifdef CONFIG_PCI
842033e6	19	#define CONFIG_PCI_INDIRECT_BRIDGE
2738bc8d PG	20	#define CONFIG_PCI1
	21	#endif
	22
d24f2d32	23	#ifdef CONFIG_66
2738bc8d PG	24	#define CONFIG_SYS_CLK_DIV 1
	25	#endif
	26
d24f2d32	27	#ifdef CONFIG_33
2738bc8d PG	28	#define CONFIG_SYS_CLK_DIV 2
	29	#endif
	30
d24f2d32	31	#ifdef CONFIG_PCIE
2738bc8d PG	32	#define CONFIG_PCIE1
	33	#endif
	34
	35	/*
	36	* High Level Configuration Options
	37	*/
9e3ed392	38
f0aec4ea PG	39	/*
	40	* If you want to boot from the SODIMM flash, instead of the soldered
	41	* on flash, set this, and change JP12, SW2:8 accordingly.
	42	*/
	43	#undef CONFIG_SYS_ALT_BOOT
	44
9e3ed392	45	#undef CONFIG_RIO
fdc7eb90 PG	46
	47	#ifdef CONFIG_PCI
	48	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	49	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
	50	#endif
9e3ed392	51
9e3ed392	52	#define CONFIG_ENV_OVERWRITE
9e3ed392	53
9e3ed392 JH	54	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
9e3ed392 JH	55
2738bc8d PG	56	/*
	57	* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
	58	*/
	59	#ifndef CONFIG_SYS_CLK_DIV
	60	#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
	61	#endif
	62	#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
9e3ed392 JH	63
	64	/*
	65	* These can be toggled for performance analysis, otherwise use default.
	66	*/
	67	#define CONFIG_L2_CACHE /* toggle L2 cache */
	68	#define CONFIG_BTB /* toggle branch predition */
9e3ed392 JH	69
	70	/*
	71	* Only possible on E500 Version 2 or newer cores.
	72	*/
	73	#define CONFIG_ENABLE_36BIT_PHYS 1
	74
6d0f6bcf	75	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
9e3ed392	76
e46fedfe TT	77	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	78	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
9e3ed392	79
33b9079b	80	/* DDR Setup */
7e44f2b7 PG	81	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	82	/*
	83	* A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
	84	* to collide, meaning you couldn't reliably read either. So
	85	* physically remove the LBC PC100 SDRAM module from the board
3e3262bd PG	86	* before enabling the two SPD options below, or check that you
	87	* have the hardware fix on your board via "i2c probe" and looking
	88	* for a device at 0x53.
7e44f2b7	89	*/
33b9079b KG	90	#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
33b9079b KG	91	#undef CONFIG_DDR_SPD
33b9079b KG	92
	93	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	94	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	95
6d0f6bcf JCPV	96	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	97	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
33b9079b KG	98	#define CONFIG_VERY_BIG_RAM
33b9079b KG	99
33b9079b KG	100	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
33b9079b KG	101	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
9e3ed392	102
3e3262bd PG	103	/*
	104	* The hardware fix for the I2C address collision puts the DDR
	105	* SPD at 0x53, but if we are running on an older board w/o the
	106	* fix, it will still be at 0x51. We check 0x53 1st.
	107	*/
33b9079b	108	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
3e3262bd	109	#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
9e3ed392 JH	110
	111	/*
	112	* Make sure required options are set
	113	*/
	114	#ifndef CONFIG_SPD_EEPROM
6d0f6bcf	115	#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
2a6b3b74	116	#define CONFIG_SYS_DDR_CONTROL 0xc300c000
9e3ed392 JH	117	#endif
	118
	119	#undef CONFIG_CLOCKS_IN_MHZ
	120
	121	/*
	122	* FLASH on the Local Bus
	123	* Two banks, one 8MB the other 64MB, using the CFI driver.
f0aec4ea PG	124	* JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
	125	* CS0 the 8MB boot flash, and CS6 the 64MB flash.
	126	*
	127	* Default:
	128	* ec00_0000 efff_ffff 64MB SODIMM
	129	* ff80_0000 ffff_ffff 8MB soldered flash
9e3ed392	130	*
f0aec4ea PG	131	* Alternate:
	132	* ef80_0000 efff_ffff 8MB soldered flash
	133	* fc00_0000 ffff_ffff 64MB SODIMM
	134	*
	135	* BR0_8M:
9e3ed392 JH	136	* Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
	137	* Port Size = 8 bits = BRx[19:20] = 01
	138	* Use GPCM = BRx[24:26] = 000
	139	* Valid = BRx[31] = 1
	140	*
f0aec4ea PG	141	* BR0_64M:
f0aec4ea PG	142	* Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
9e3ed392	143	* Port Size = 32 bits = BRx[19:20] = 11
f0aec4ea PG	144	*
	145	* 0 4 8 12 16 20 24 28
	146	* 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
	147	* 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
	148	*/
	149	#define CONFIG_SYS_BR0_8M 0xff800801
	150	#define CONFIG_SYS_BR0_64M 0xfc001801
	151
	152	/*
	153	* BR6_8M:
	154	* Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
	155	* Port Size = 8 bits = BRx[19:20] = 01
9e3ed392 JH	156	* Use GPCM = BRx[24:26] = 000
9e3ed392 JH	157	* Valid = BRx[31] = 1
f0aec4ea PG	158
	159	* BR6_64M:
	160	* Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
	161	* Port Size = 32 bits = BRx[19:20] = 11
9e3ed392 JH	162	*
9e3ed392 JH	163	* 0 4 8 12 16 20 24 28
f0aec4ea PG	164	* 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
	165	* 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
	166	*/
	167	#define CONFIG_SYS_BR6_8M 0xef800801
	168	#define CONFIG_SYS_BR6_64M 0xec001801
	169
	170	/*
	171	* OR0_8M:
9e3ed392 JH	172	* Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
	173	* XAM = OR0[17:18] = 11
	174	* CSNT = OR0[20] = 1
	175	* ACS = half cycle delay = OR0[21:22] = 11
	176	* SCY = 6 = OR0[24:27] = 0110
	177	* TRLX = use relaxed timing = OR0[29] = 1
	178	* EAD = use external address latch delay = OR0[31] = 1
	179	*
f0aec4ea PG	180	* OR0_64M:
f0aec4ea PG	181	* Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
9e3ed392	182	*
f0aec4ea PG	183	*
	184	* 0 4 8 12 16 20 24 28
	185	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
	186	* 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
	187	*/
	188	#define CONFIG_SYS_OR0_8M 0xff806e65
	189	#define CONFIG_SYS_OR0_64M 0xfc006e65
	190
	191	/*
	192	* OR6_8M:
	193	* Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
9e3ed392 JH	194	* XAM = OR6[17:18] = 11
	195	* CSNT = OR6[20] = 1
	196	* ACS = half cycle delay = OR6[21:22] = 11
	197	* SCY = 6 = OR6[24:27] = 0110
	198	* TRLX = use relaxed timing = OR6[29] = 1
	199	* EAD = use external address latch delay = OR6[31] = 1
	200	*
f0aec4ea PG	201	* OR6_64M:
	202	* Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
	203	*
9e3ed392	204	* 0 4 8 12 16 20 24 28
f0aec4ea PG	205	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
f0aec4ea PG	206	* 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
9e3ed392	207	*/
f0aec4ea PG	208	#define CONFIG_SYS_OR6_8M 0xff806e65
f0aec4ea PG	209	#define CONFIG_SYS_OR6_64M 0xfc006e65
9e3ed392	210
f0aec4ea	211	#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
6d0f6bcf	212	#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
3fd673cf	213	#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
9e3ed392	214
f0aec4ea PG	215	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
	216	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
	217
	218	#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
	219	#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
	220	#else /* JP12 in alternate position */
	221	#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
	222	#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
9e3ed392	223
f0aec4ea PG	224	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
	225	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
	226
	227	#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
	228	#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
	229	#endif
9e3ed392	230
f0aec4ea	231	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
9b3ba24f PG	232	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
	233	CONFIG_SYS_ALT_FLASH}
	234	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	235	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
6d0f6bcf JCPV	236	#undef CONFIG_SYS_FLASH_CHECKSUM
	237	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	238	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
9e3ed392	239
14d0a02a	240	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
9e3ed392	241
6d0f6bcf	242	#define CONFIG_SYS_FLASH_EMPTY_INFO
9e3ed392 JH	243
	244	/* CS5 = Local bus peripherals controlled by the EPLD */
	245
6d0f6bcf JCPV	246	#define CONFIG_SYS_BR5_PRELIM 0xf8000801
	247	#define CONFIG_SYS_OR5_PRELIM 0xff006e65
	248	#define CONFIG_SYS_EPLD_BASE 0xf8000000
	249	#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
	250	#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
	251	#define CONFIG_SYS_BD_REV 0xf8300000
	252	#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
9e3ed392 JH	253
9e3ed392 JH	254	/*
11d5a629	255	* SDRAM on the Local Bus (CS3 and CS4)
7e44f2b7 PG	256	* Note that most boards have a hardware errata where both the
	257	* LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
	258	* to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
3e3262bd	259	* A hardware workaround is also available, see README.sbc8548 file.
9e3ed392	260	*/
6d0f6bcf	261	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
11d5a629	262	#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
9e3ed392 JH	263
9e3ed392 JH	264	/*
11d5a629	265	* Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
6d0f6bcf	266	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
9e3ed392 JH	267	*
	268	* For BR3, need:
	269	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	270	* port-size = 32-bits = BR2[19:20] = 11
	271	* no parity checking = BR2[21:22] = 00
	272	* SDRAM for MSEL = BR2[24:26] = 011
	273	* Valid = BR[31] = 1
	274	*
	275	* 0 4 8 12 16 20 24 28
	276	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	277	*
	278	*/
	279
6d0f6bcf	280	#define CONFIG_SYS_BR3_PRELIM 0xf0001861
9e3ed392 JH	281
9e3ed392 JH	282	/*
11d5a629	283	* The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
9e3ed392 JH	284	*
	285	* For OR3, need:
	286	* 64MB mask for AM, OR3[0:7] = 1111 1100
	287	* XAM, OR3[17:18] = 11
	288	* 10 columns OR3[19-21] = 011
	289	* 12 rows OR3[23-25] = 011
	290	* EAD set for extra time OR[31] = 0
	291	*
	292	* 0 4 8 12 16 20 24 28
	293	* 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
	294	*/
	295
6d0f6bcf	296	#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
9e3ed392	297
11d5a629 PG	298	/*
	299	* Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
	300	* The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
	301	*
	302	* For BR4, need:
	303	* Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
	304	* port-size = 32-bits = BR2[19:20] = 11
	305	* no parity checking = BR2[21:22] = 00
	306	* SDRAM for MSEL = BR2[24:26] = 011
	307	* Valid = BR[31] = 1
	308	*
	309	* 0 4 8 12 16 20 24 28
	310	* 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
	311	*
	312	*/
	313
	314	#define CONFIG_SYS_BR4_PRELIM 0xf4001861
	315
	316	/*
	317	* The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
	318	*
	319	* For OR4, need:
	320	* 64MB mask for AM, OR3[0:7] = 1111 1100
	321	* XAM, OR3[17:18] = 11
	322	* 10 columns OR3[19-21] = 011
	323	* 12 rows OR3[23-25] = 011
	324	* EAD set for extra time OR[31] = 0
	325	*
	326	* 0 4 8 12 16 20 24 28
	327	* 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
	328	*/
	329
	330	#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
	331
6d0f6bcf JCPV	332	#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
	333	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	334	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	335	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
9e3ed392	336
9e3ed392 JH	337	/*
9e3ed392 JH	338	* Common settings for all Local Bus SDRAM commands.
9e3ed392	339	*/
b0fe93ed	340	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
5f4c6f0d PG	341	\| LSDMR_BSMA1516 \
	342	\| LSDMR_PRETOACT3 \
	343	\| LSDMR_ACTTORW3 \
	344	\| LSDMR_BUFCMD \
b0fe93ed	345	\| LSDMR_BL8 \
5f4c6f0d	346	\| LSDMR_WRC2 \
b0fe93ed	347	\| LSDMR_CL3 \
9e3ed392 JH	348	)
9e3ed392 JH	349
5f4c6f0d PG	350	#define CONFIG_SYS_LBC_LSDMR_PCHALL \
	351	(CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	352	#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
	353	(CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	354	#define CONFIG_SYS_LBC_LSDMR_MRW \
	355	(CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	356	#define CONFIG_SYS_LBC_LSDMR_RFEN \
	357	(CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_RFEN)
	358
6d0f6bcf JCPV	359	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	360	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	361	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
9e3ed392	362
6d0f6bcf	363	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
9e3ed392	364
25ddd1fb	365	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	366	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
9e3ed392	367
dd9ca98f PG	368	/*
dd9ca98f PG	369	* For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
14d0a02a	370	* one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
dd9ca98f	371	* flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
14d0a02a	372	* (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
dd9ca98f PG	373	* thing for MONITOR_LEN in both cases.
dd9ca98f PG	374	*/
14d0a02a	375	#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
f0aec4ea	376	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
9e3ed392 JH	377
9e3ed392 JH	378	/* Serial Port */
6d0f6bcf JCPV	379	#define CONFIG_SYS_NS16550_SERIAL
6d0f6bcf JCPV	380	#define CONFIG_SYS_NS16550_REG_SIZE 1
2738bc8d	381	#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
9e3ed392	382
6d0f6bcf	383	#define CONFIG_SYS_BAUDRATE_TABLE \
9e3ed392 JH	384	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
9e3ed392 JH	385
6d0f6bcf JCPV	386	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	387	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
9e3ed392	388
9e3ed392 JH	389	/*
	390	* I2C
	391	*/
00f792e0 HS	392	#define CONFIG_SYS_I2C
	393	#define CONFIG_SYS_I2C_FSL
	394	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	395	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	396	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
6d0f6bcf	397	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
9e3ed392 JH	398
	399	/*
	400	* General PCI
	401	* Memory space is mapped 1-1, but I/O space must start from 0.
	402	*/
fdc7eb90	403	#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
6d0f6bcf	404	#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
9e3ed392	405
fdc7eb90 PG	406	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
	407	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
	408	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	409	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
fdc7eb90 PG	410	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
	411	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
	412	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
	413	#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
9e3ed392 JH	414
9e3ed392 JH	415	#ifdef CONFIG_PCIE1
fdc7eb90 PG	416	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
	417	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
	418	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
6d0f6bcf	419	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
fdc7eb90 PG	420	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
	421	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	422	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
	423	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
9e3ed392 JH	424	#endif
	425
	426	#ifdef CONFIG_RIO
	427	/*
	428	* RapidIO MMU
	429	*/
6d0f6bcf JCPV	430	#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
6d0f6bcf JCPV	431	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
9e3ed392 JH	432	#endif
9e3ed392 JH	433
9e3ed392	434	#if defined(CONFIG_PCI)
9e3ed392 JH	435	#undef CONFIG_EEPRO100
	436	#undef CONFIG_TULIP
	437
fdc7eb90	438	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
9e3ed392	439
9e3ed392 JH	440	#endif /* CONFIG_PCI */
9e3ed392 JH	441
9e3ed392 JH	442	#if defined(CONFIG_TSEC_ENET)
9e3ed392 JH	443
9e3ed392 JH	444	#define CONFIG_TSEC1 1
	445	#define CONFIG_TSEC1_NAME "eTSEC0"
	446	#define CONFIG_TSEC2 1
	447	#define CONFIG_TSEC2_NAME "eTSEC1"
9e3ed392 JH	448	#undef CONFIG_MPC85XX_FEC
9e3ed392 JH	449
58da8890 PG	450	#define TSEC1_PHY_ADDR 0x19
58da8890 PG	451	#define TSEC2_PHY_ADDR 0x1a
9e3ed392 JH	452
	453	#define TSEC1_PHYIDX 0
	454	#define TSEC2_PHYIDX 0
bd93105f	455
9e3ed392 JH	456	#define TSEC1_FLAGS TSEC_GIGABIT
9e3ed392 JH	457	#define TSEC2_FLAGS TSEC_GIGABIT
9e3ed392 JH	458
	459	/* Options are: eTSEC[0-3] */
	460	#define CONFIG_ETHPRIME "eTSEC0"
9e3ed392 JH	461	#endif /* CONFIG_TSEC_ENET */
9e3ed392 JH	462
9e3ed392	463	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	464	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
9e3ed392 JH	465
	466	/*
	467	* BOOTP options
	468	*/
	469	#define CONFIG_BOOTP_BOOTFILESIZE
9e3ed392	470
9e3ed392 JH	471	#undef CONFIG_WATCHDOG /* watchdog disabled */
	472
	473	/*
	474	* Miscellaneous configurable options
	475	*/
6d0f6bcf	476	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
9e3ed392 JH	477
	478	/*
	479	* For booting Linux, the board info and command line data
	480	* have to be in the first 8 MB of memory, since this is
	481	* the maximum mapped by the Linux kernel during initialization.
	482	*/
6d0f6bcf	483	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
9e3ed392	484
9e3ed392 JH	485	#if defined(CONFIG_CMD_KGDB)
9e3ed392 JH	486	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
9e3ed392 JH	487	#endif
	488
	489	/*
	490	* Environment Configuration
	491	*/
9e3ed392 JH	492	#if defined(CONFIG_TSEC_ENET)
9e3ed392 JH	493	#define CONFIG_HAS_ETH0
9e3ed392	494	#define CONFIG_HAS_ETH1
9e3ed392 JH	495	#endif
	496
	497	#define CONFIG_IPADDR 192.168.0.55
	498
5bc0543d	499	#define CONFIG_HOSTNAME "sbc8548"
8b3637c6	500	#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
b3f44c21	501	#define CONFIG_BOOTFILE "/uImage"
9e3ed392 JH	502	#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
	503
	504	#define CONFIG_SERVERIP 192.168.0.2
	505	#define CONFIG_GATEWAYIP 192.168.0.1
	506	#define CONFIG_NETMASK 255.255.255.0
	507
	508	#define CONFIG_LOADADDR 1000000 /default location for tftp and bootm/
	509
9e3ed392	510	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d MV	511	"netdev=eth0\0" \
	512	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	513	"tftpflash=tftpboot $loadaddr $uboot; " \
	514	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	515	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	516	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	517	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	518	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
	519	"consoledev=ttyS0\0" \
	520	"ramdiskaddr=2000000\0" \
	521	"ramdiskfile=uRamdisk\0" \
b24a4f62	522	"fdtaddr=1e00000\0" \
5368c55d	523	"fdtfile=sbc8548.dtb\0"
9e3ed392 JH	524
	525	#define CONFIG_NFSBOOTCOMMAND \
	526	"setenv bootargs root=/dev/nfs rw " \
	527	"nfsroot=$serverip:$rootpath " \
	528	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	529	"console=$consoledev,$baudrate $othbootargs;" \
	530	"tftp $loadaddr $bootfile;" \
	531	"tftp $fdtaddr $fdtfile;" \
	532	"bootm $loadaddr - $fdtaddr"
	533
9e3ed392 JH	534	#define CONFIG_RAMBOOTCOMMAND \
	535	"setenv bootargs root=/dev/ram rw " \
	536	"console=$consoledev,$baudrate $othbootargs;" \
	537	"tftp $ramdiskaddr $ramdiskfile;" \
	538	"tftp $loadaddr $bootfile;" \
	539	"tftp $fdtaddr $fdtfile;" \
	540	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	541
	542	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	543
	544	#endif /* __CONFIG_H */