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10a36a98 WD |
1 | /* |
2 | * (C) Copyright 2002,2003 Motorola,Inc. | |
3 | * Xianghua Xiao <X.Xiao@motorola.com> | |
4 | * | |
5 | * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. | |
6 | * Added support for Wind River SBC8560 board | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
37fef499 PG |
27 | /* sbc8560 board configuration file */ |
28 | /* please refer to doc/README.sbc8560 for more info */ | |
10a36a98 WD |
29 | /* make sure you change the MAC address and other network params first, |
30 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
36 | /* High Level Configuration Options */ | |
37 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
38 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
39 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
40 | #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ | |
41 | ||
42 | ||
9c4c5ae3 | 43 | #define CONFIG_CPM2 1 /* has CPM2 */ |
10a36a98 | 44 | #define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ |
f060054d | 45 | #define CONFIG_MPC8560 1 |
10a36a98 WD |
46 | |
47 | /* XXX flagging this as something I might want to delete */ | |
48 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ | |
49 | ||
50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
51 | #undef CONFIG_PCI /* pci ethernet support */ | |
52 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ | |
53 | ||
e2b159d0 | 54 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
10a36a98 WD |
55 | |
56 | #define CONFIG_ENV_OVERWRITE | |
57 | ||
58 | /* Using Localbus SDRAM to emulate flash before we can program the flash, | |
59 | * normally you need a flash-boot image(u-boot.bin), if so undef this. | |
60 | */ | |
61 | #undef CONFIG_RAM_AS_FLASH | |
62 | ||
63 | #if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ | |
64 | #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ | |
65 | #else | |
66 | #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ | |
67 | #endif | |
68 | ||
69 | /* below can be toggled for performance analysis. otherwise use default */ | |
70 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
71 | #undef CONFIG_BTB /* toggle branch predition */ | |
72 | #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
73 | ||
74 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
75 | ||
76 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
77 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
78 | #define CFG_MEMTEST_END 0x00400000 | |
79 | ||
80 | #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ | |
81 | defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ | |
82 | defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) | |
83 | #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." | |
84 | #endif | |
85 | ||
86 | /* | |
87 | * Base addresses -- Note these are effective addresses where the | |
88 | * actual resources get mapped (not physical addresses) | |
89 | */ | |
90 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
91 | ||
92 | #if XXX | |
93 | #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ | |
94 | #else | |
95 | #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ | |
96 | #endif | |
f69766e4 | 97 | #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ |
10a36a98 WD |
98 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
99 | ||
10a36a98 | 100 | #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ |
10a36a98 | 101 | |
8e55313b KG |
102 | /* DDR Setup */ |
103 | #define CONFIG_FSL_DDR1 | |
104 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
105 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
106 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
107 | #undef CONFIG_DDR_SPD | |
10a36a98 WD |
108 | |
109 | #if defined(CONFIG_MPC85xx_REV1) | |
8e55313b | 110 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
10a36a98 WD |
111 | #endif |
112 | ||
8e55313b KG |
113 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
114 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
115 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
116 | ||
117 | #define CFG_DDR_SDRAM_BASE 0x00000000 | |
118 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
119 | #define CONFIG_VERY_BIG_RAM | |
120 | ||
121 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
122 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
123 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
124 | ||
125 | /* I2C addresses of SPD EEPROMs */ | |
126 | #define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ | |
127 | ||
10a36a98 WD |
128 | #undef CONFIG_CLOCKS_IN_MHZ |
129 | ||
130 | #if defined(CONFIG_RAM_AS_FLASH) | |
131 | #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ | |
132 | #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ | |
133 | #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ | |
134 | #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ | |
135 | #else /* Boot from real Flash */ | |
136 | #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ | |
137 | #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ | |
138 | #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ | |
139 | #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ | |
140 | #endif | |
141 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
142 | ||
143 | /* local bus definitions */ | |
144 | #define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ | |
145 | #define CFG_OR1_PRELIM 0xfc000ff7 | |
146 | ||
147 | #define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ | |
148 | #define CFG_OR2_PRELIM 0x00000000 | |
149 | ||
150 | #define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ | |
151 | #define CFG_OR3_PRELIM 0xfc000cc1 | |
152 | ||
153 | #if defined(CONFIG_RAM_AS_FLASH) | |
154 | #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ | |
155 | #else | |
156 | #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ | |
157 | #endif | |
158 | #define CFG_OR4_PRELIM 0xfc000cc1 | |
159 | ||
160 | #define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ | |
161 | #if 1 | |
162 | #define CFG_OR5_PRELIM 0xff000ff7 | |
163 | #else | |
164 | #define CFG_OR5_PRELIM 0xff0000f0 | |
165 | #endif | |
166 | ||
167 | #define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ | |
168 | #define CFG_OR6_PRELIM 0xfc000ff7 | |
169 | #define CFG_LBC_LCRR 0x00030002 /* local bus freq */ | |
170 | #define CFG_LBC_LBCR 0x00000000 | |
171 | #define CFG_LBC_LSRT 0x20000000 | |
172 | #define CFG_LBC_MRTPR 0x20000000 | |
173 | #define CFG_LBC_LSDMR_1 0x2861b723 | |
174 | #define CFG_LBC_LSDMR_2 0x0861b723 | |
175 | #define CFG_LBC_LSDMR_3 0x0861b723 | |
176 | #define CFG_LBC_LSDMR_4 0x1861b723 | |
177 | #define CFG_LBC_LSDMR_5 0x4061b723 | |
178 | ||
179 | /* just hijack the MOT BCSR def for SBC8560 misc devices */ | |
180 | #define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) | |
181 | /* the size of CS5 needs to be >= 16M for TLB and LAW setups */ | |
182 | ||
183 | #define CONFIG_L1_INIT_RAM | |
184 | #define CFG_INIT_RAM_LOCK 1 | |
185 | #define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ | |
186 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
187 | ||
188 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
189 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
190 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
191 | ||
192 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
193 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
194 | ||
195 | /* Serial Port */ | |
c158bcac PG |
196 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
197 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
10a36a98 WD |
198 | |
199 | #define CONFIG_CONS_INDEX 1 | |
200 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
201 | #define CFG_NS16550 | |
202 | #define CFG_NS16550_SERIAL | |
203 | #define CFG_NS16550_REG_SIZE 1 | |
204 | #define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ | |
205 | #define CONFIG_BAUDRATE 9600 | |
206 | ||
207 | #define CFG_BAUDRATE_TABLE \ | |
208 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
209 | ||
210 | #define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) | |
211 | #define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) | |
212 | ||
213 | /* Use the HUSH parser */ | |
214 | #define CFG_HUSH_PARSER | |
215 | #ifdef CFG_HUSH_PARSER | |
216 | #define CFG_PROMPT_HUSH_PS2 "> " | |
217 | #endif | |
218 | ||
c3ca7e5e PG |
219 | /* pass open firmware flat tree */ |
220 | #define CONFIG_OF_LIBFDT 1 | |
221 | #define CONFIG_OF_BOARD_SETUP 1 | |
222 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
223 | ||
20476726 JL |
224 | /* |
225 | * I2C | |
226 | */ | |
227 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
228 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
10a36a98 WD |
229 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
230 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
231 | #define CFG_I2C_SLAVE 0x7F | |
232 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
20476726 | 233 | #define CFG_I2C_OFFSET 0x3000 |
10a36a98 WD |
234 | |
235 | #define CFG_PCI_MEM_BASE 0xC0000000 | |
236 | #define CFG_PCI_MEM_PHYS 0xC0000000 | |
237 | #define CFG_PCI_MEM_SIZE 0x10000000 | |
238 | ||
6de5bf24 PG |
239 | #ifdef CONFIG_TSEC_ENET |
240 | ||
241 | #ifndef CONFIG_NET_MULTI | |
242 | #define CONFIG_NET_MULTI 1 | |
243 | #endif | |
244 | ||
245 | #ifndef CONFIG_MII | |
246 | #define CONFIG_MII 1 /* MII PHY management */ | |
247 | #endif | |
248 | #define CONFIG_TSEC1 1 | |
249 | #define CONFIG_TSEC1_NAME "TSEC0" | |
250 | #define CONFIG_TSEC2 1 | |
251 | #define CONFIG_TSEC2_NAME "TSEC1" | |
252 | #define TSEC1_PHY_ADDR 0x19 | |
253 | #define TSEC2_PHY_ADDR 0x1a | |
254 | #define TSEC1_PHYIDX 0 | |
255 | #define TSEC2_PHYIDX 0 | |
256 | #define TSEC1_FLAGS TSEC_GIGABIT | |
257 | #define TSEC2_FLAGS TSEC_GIGABIT | |
258 | ||
259 | /* Options are: TSEC[0-1] */ | |
260 | #define CONFIG_ETHPRIME "TSEC0" | |
10a36a98 WD |
261 | |
262 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ | |
263 | ||
264 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
265 | #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ | |
266 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
267 | ||
268 | #if (CONFIG_ETHER_INDEX == 2) | |
269 | /* | |
270 | * - Rx-CLK is CLK13 | |
271 | * - Tx-CLK is CLK14 | |
272 | * - Select bus for bd/buffers | |
273 | * - Full duplex | |
274 | */ | |
275 | #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) | |
276 | #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
277 | #define CFG_CPMFCR_RAMTYPE 0 | |
278 | #define CFG_FCC_PSMR (FCC_PSMR_FDE) | |
279 | ||
280 | #elif (CONFIG_ETHER_INDEX == 3) | |
281 | /* need more definitions here for FE3 */ | |
282 | #endif /* CONFIG_ETHER_INDEX */ | |
283 | ||
284 | #define CONFIG_MII /* MII PHY management */ | |
285 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
286 | /* | |
287 | * GPIO pins used for bit-banged MII communications | |
288 | */ | |
289 | #define MDIO_PORT 2 /* Port C */ | |
290 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) | |
291 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
292 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
293 | ||
294 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
295 | else iop->pdat &= ~0x00400000 | |
296 | ||
297 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
298 | else iop->pdat &= ~0x00200000 | |
299 | ||
300 | #define MIIDELAY udelay(1) | |
301 | ||
302 | #endif | |
303 | ||
304 | /*----------------------------------------------------------------------- | |
305 | * FLASH and environment organization | |
306 | */ | |
307 | ||
c158bcac | 308 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 309 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
10a36a98 | 310 | #if 0 |
c158bcac PG |
311 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
312 | #define CFG_FLASH_PROTECTION /* use hardware protection */ | |
10a36a98 | 313 | #endif |
c158bcac PG |
314 | #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
315 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
10a36a98 WD |
316 | |
317 | #undef CFG_FLASH_CHECKSUM | |
c158bcac PG |
318 | #define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ |
319 | #define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ | |
10a36a98 | 320 | |
c158bcac | 321 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
10a36a98 WD |
322 | |
323 | #if 0 | |
324 | /* XXX This doesn't work and I don't want to fix it */ | |
325 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
326 | #define CFG_RAMBOOT | |
327 | #else | |
328 | #undef CFG_RAMBOOT | |
329 | #endif | |
330 | #endif | |
331 | ||
332 | /* Environment */ | |
333 | #if !defined(CFG_RAMBOOT) | |
334 | #if defined(CONFIG_RAM_AS_FLASH) | |
335 | #define CFG_ENV_IS_NOWHERE | |
336 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) | |
337 | #define CFG_ENV_SIZE 0x2000 | |
338 | #else | |
339 | #define CFG_ENV_IS_IN_FLASH 1 | |
340 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
341 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) | |
342 | #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ | |
343 | #endif | |
344 | #else | |
345 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
346 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
347 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
348 | #define CFG_ENV_SIZE 0x2000 | |
349 | #endif | |
350 | ||
c158bcac | 351 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600" |
10a36a98 | 352 | /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ |
10a36a98 WD |
353 | #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ |
354 | ||
355 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
356 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
357 | ||
2835e518 | 358 | |
079a136c JL |
359 | /* |
360 | * BOOTP options | |
361 | */ | |
362 | #define CONFIG_BOOTP_BOOTFILESIZE | |
363 | #define CONFIG_BOOTP_BOOTPATH | |
364 | #define CONFIG_BOOTP_GATEWAY | |
365 | #define CONFIG_BOOTP_HOSTNAME | |
366 | ||
367 | ||
2835e518 JL |
368 | /* |
369 | * Command line configuration. | |
370 | */ | |
371 | #include <config_cmd_default.h> | |
372 | ||
373 | #define CONFIG_CMD_PING | |
374 | #define CONFIG_CMD_I2C | |
375 | ||
376 | #if defined(CONFIG_PCI) | |
377 | #define CONFIG_CMD_PCI | |
378 | #endif | |
379 | ||
380 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
381 | #define CONFIG_CMD_MII | |
382 | #endif | |
383 | ||
10a36a98 | 384 | #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) |
2835e518 JL |
385 | #undef CONFIG_CMD_ENV |
386 | #undef CONFIG_CMD_LOADS | |
10a36a98 WD |
387 | #endif |
388 | ||
10a36a98 WD |
389 | |
390 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
391 | ||
392 | /* | |
393 | * Miscellaneous configurable options | |
394 | */ | |
395 | #define CFG_LONGHELP /* undef to save memory */ | |
396 | #define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ | |
2835e518 | 397 | #if defined(CONFIG_CMD_KGDB) |
10a36a98 WD |
398 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
399 | #else | |
400 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
401 | #endif | |
402 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
403 | #define CFG_MAXARGS 16 /* max number of command args */ | |
404 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
405 | #define CFG_LOAD_ADDR 0x1000000 /* default load address */ | |
406 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
407 | ||
408 | /* | |
409 | * For booting Linux, the board info and command line data | |
410 | * have to be in the first 8 MB of memory, since this is | |
411 | * the maximum mapped by the Linux kernel during initialization. | |
412 | */ | |
413 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
414 | ||
10a36a98 WD |
415 | /* |
416 | * Internal Definitions | |
417 | * | |
418 | * Boot Flags | |
419 | */ | |
420 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
421 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
422 | ||
2835e518 | 423 | #if defined(CONFIG_CMD_KGDB) |
37fef499 PG |
424 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
425 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
10a36a98 WD |
426 | #endif |
427 | ||
10a36a98 | 428 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
c158bcac PG |
429 | #define CONFIG_HAS_ETH0 |
430 | #define CONFIG_HAS_ETH1 | |
10a36a98 WD |
431 | #endif |
432 | ||
c158bcac PG |
433 | /* You can compile in a MAC address and your custom net settings by using |
434 | * the following syntax. Your board should be marked with the assigned | |
435 | * MAC addresses directly on it. | |
436 | * | |
437 | * #define CONFIG_ETHADDR de:ad:be:ef:00:00 | |
438 | * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s! | |
439 | * #define CONFIG_SERVERIP <server ip> | |
440 | * #define CONFIG_IPADDR <board ip> | |
441 | * #define CONFIG_GATEWAYIP <gateway ip> | |
442 | * #define CONFIG_NETMASK <your netmask> | |
443 | */ | |
444 | ||
10a36a98 WD |
445 | #define CONFIG_HOSTNAME SBC8560 |
446 | #define CONFIG_ROOTPATH /home/ppc | |
37fef499 PG |
447 | #define CONFIG_BOOTFILE uImage |
448 | ||
449 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
450 | "netdev=eth0\0" \ | |
451 | "consoledev=ttyS0\0" \ | |
452 | "ramdiskaddr=2000000\0" \ | |
453 | "ramdiskfile=ramdisk.uboot\0" \ | |
454 | "fdtaddr=c00000\0" \ | |
455 | "fdtfile=sbc8560.dtb\0" | |
456 | ||
457 | #define CONFIG_NFSBOOTCOMMAND \ | |
458 | "setenv bootargs root=/dev/nfs rw " \ | |
459 | "nfsroot=$serverip:$rootpath " \ | |
460 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
461 | "console=$consoledev,$baudrate $othbootargs;" \ | |
462 | "tftp $loadaddr $bootfile;" \ | |
463 | "tftp $fdtaddr $fdtfile;" \ | |
464 | "bootm $loadaddr - $fdtaddr" | |
465 | ||
466 | ||
467 | #define CONFIG_RAMBOOTCOMMAND \ | |
468 | "setenv bootargs root=/dev/ram rw " \ | |
469 | "console=$consoledev,$baudrate $othbootargs;" \ | |
470 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
471 | "tftp $loadaddr $bootfile;" \ | |
472 | "tftp $fdtaddr $fdtfile;" \ | |
473 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
474 | ||
475 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
10a36a98 WD |
476 | |
477 | #endif /* __CONFIG_H */ |