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10a36a98 WD |
1 | /* |
2 | * (C) Copyright 2002,2003 Motorola,Inc. | |
3 | * Xianghua Xiao <X.Xiao@motorola.com> | |
4 | * | |
5 | * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. | |
6 | * Added support for Wind River SBC8560 board | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
37fef499 PG |
27 | /* sbc8560 board configuration file */ |
28 | /* please refer to doc/README.sbc8560 for more info */ | |
10a36a98 WD |
29 | /* make sure you change the MAC address and other network params first, |
30 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
36 | /* High Level Configuration Options */ | |
37 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
38 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
39 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
40 | #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ | |
41 | ||
42 | ||
9c4c5ae3 | 43 | #define CONFIG_CPM2 1 /* has CPM2 */ |
10a36a98 | 44 | #define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ |
f060054d | 45 | #define CONFIG_MPC8560 1 |
10a36a98 WD |
46 | |
47 | /* XXX flagging this as something I might want to delete */ | |
48 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ | |
49 | ||
50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
51 | #undef CONFIG_PCI /* pci ethernet support */ | |
52 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ | |
53 | ||
e2b159d0 | 54 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
10a36a98 WD |
55 | |
56 | #define CONFIG_ENV_OVERWRITE | |
57 | ||
58 | /* Using Localbus SDRAM to emulate flash before we can program the flash, | |
59 | * normally you need a flash-boot image(u-boot.bin), if so undef this. | |
60 | */ | |
61 | #undef CONFIG_RAM_AS_FLASH | |
62 | ||
63 | #if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ | |
64 | #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ | |
65 | #else | |
66 | #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ | |
67 | #endif | |
68 | ||
69 | /* below can be toggled for performance analysis. otherwise use default */ | |
70 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
71 | #undef CONFIG_BTB /* toggle branch predition */ | |
72 | #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
73 | ||
74 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
75 | ||
6d0f6bcf JCPV |
76 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
77 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
78 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
10a36a98 WD |
79 | |
80 | #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ | |
81 | defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ | |
82 | defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) | |
83 | #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." | |
84 | #endif | |
85 | ||
86 | /* | |
87 | * Base addresses -- Note these are effective addresses where the | |
88 | * actual resources get mapped (not physical addresses) | |
89 | */ | |
6d0f6bcf | 90 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
10a36a98 WD |
91 | |
92 | #if XXX | |
6d0f6bcf | 93 | #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ |
10a36a98 | 94 | #else |
6d0f6bcf | 95 | #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ |
10a36a98 | 96 | #endif |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
98 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
10a36a98 | 99 | |
6d0f6bcf | 100 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
10a36a98 | 101 | |
8e55313b KG |
102 | /* DDR Setup */ |
103 | #define CONFIG_FSL_DDR1 | |
104 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
105 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
106 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
107 | #undef CONFIG_DDR_SPD | |
10a36a98 WD |
108 | |
109 | #if defined(CONFIG_MPC85xx_REV1) | |
8e55313b | 110 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
10a36a98 WD |
111 | #endif |
112 | ||
8e55313b KG |
113 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
114 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
115 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
116 | ||
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
118 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
8e55313b KG |
119 | #define CONFIG_VERY_BIG_RAM |
120 | ||
121 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
122 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
123 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
124 | ||
125 | /* I2C addresses of SPD EEPROMs */ | |
126 | #define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ | |
127 | ||
10a36a98 WD |
128 | #undef CONFIG_CLOCKS_IN_MHZ |
129 | ||
130 | #if defined(CONFIG_RAM_AS_FLASH) | |
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
132 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ | |
133 | #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */ | |
134 | #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ | |
10a36a98 | 135 | #else /* Boot from real Flash */ |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ |
137 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ | |
138 | #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */ | |
139 | #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ | |
10a36a98 | 140 | #endif |
6d0f6bcf | 141 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
10a36a98 WD |
142 | |
143 | /* local bus definitions */ | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ |
145 | #define CONFIG_SYS_OR1_PRELIM 0xfc000ff7 | |
10a36a98 | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */ |
148 | #define CONFIG_SYS_OR2_PRELIM 0x00000000 | |
10a36a98 | 149 | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ |
151 | #define CONFIG_SYS_OR3_PRELIM 0xfc000cc1 | |
10a36a98 WD |
152 | |
153 | #if defined(CONFIG_RAM_AS_FLASH) | |
6d0f6bcf | 154 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ |
10a36a98 | 155 | #else |
6d0f6bcf | 156 | #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ |
10a36a98 | 157 | #endif |
6d0f6bcf | 158 | #define CONFIG_SYS_OR4_PRELIM 0xfc000cc1 |
10a36a98 | 159 | |
6d0f6bcf | 160 | #define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ |
10a36a98 | 161 | #if 1 |
6d0f6bcf | 162 | #define CONFIG_SYS_OR5_PRELIM 0xff000ff7 |
10a36a98 | 163 | #else |
6d0f6bcf | 164 | #define CONFIG_SYS_OR5_PRELIM 0xff0000f0 |
10a36a98 WD |
165 | #endif |
166 | ||
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ |
168 | #define CONFIG_SYS_OR6_PRELIM 0xfc000ff7 | |
169 | #define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */ | |
170 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
171 | #define CONFIG_SYS_LBC_LSRT 0x20000000 | |
172 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
173 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 | |
174 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 | |
175 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 | |
176 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 | |
177 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 | |
10a36a98 WD |
178 | |
179 | /* just hijack the MOT BCSR def for SBC8560 misc devices */ | |
6d0f6bcf | 180 | #define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) |
10a36a98 WD |
181 | /* the size of CS5 needs to be >= 16M for TLB and LAW setups */ |
182 | ||
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
184 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ | |
185 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
10a36a98 | 186 | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
188 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
189 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
10a36a98 | 190 | |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
192 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
10a36a98 WD |
193 | |
194 | /* Serial Port */ | |
c158bcac PG |
195 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
196 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
10a36a98 WD |
197 | |
198 | #define CONFIG_CONS_INDEX 1 | |
199 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_NS16550 |
201 | #define CONFIG_SYS_NS16550_SERIAL | |
202 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
203 | #define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */ | |
10a36a98 WD |
204 | #define CONFIG_BAUDRATE 9600 |
205 | ||
6d0f6bcf | 206 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
10a36a98 WD |
207 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
208 | ||
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000) |
210 | #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000) | |
10a36a98 WD |
211 | |
212 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_HUSH_PARSER |
214 | #ifdef CONFIG_SYS_HUSH_PARSER | |
215 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
10a36a98 WD |
216 | #endif |
217 | ||
c3ca7e5e PG |
218 | /* pass open firmware flat tree */ |
219 | #define CONFIG_OF_LIBFDT 1 | |
220 | #define CONFIG_OF_BOARD_SETUP 1 | |
221 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
222 | ||
20476726 JL |
223 | /* |
224 | * I2C | |
225 | */ | |
226 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
227 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
10a36a98 | 228 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
230 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
231 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
232 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
10a36a98 | 233 | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 |
235 | #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 | |
236 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
10a36a98 | 237 | |
6de5bf24 PG |
238 | #ifdef CONFIG_TSEC_ENET |
239 | ||
240 | #ifndef CONFIG_NET_MULTI | |
241 | #define CONFIG_NET_MULTI 1 | |
242 | #endif | |
243 | ||
244 | #ifndef CONFIG_MII | |
245 | #define CONFIG_MII 1 /* MII PHY management */ | |
246 | #endif | |
247 | #define CONFIG_TSEC1 1 | |
248 | #define CONFIG_TSEC1_NAME "TSEC0" | |
249 | #define CONFIG_TSEC2 1 | |
250 | #define CONFIG_TSEC2_NAME "TSEC1" | |
251 | #define TSEC1_PHY_ADDR 0x19 | |
252 | #define TSEC2_PHY_ADDR 0x1a | |
253 | #define TSEC1_PHYIDX 0 | |
254 | #define TSEC2_PHYIDX 0 | |
255 | #define TSEC1_FLAGS TSEC_GIGABIT | |
256 | #define TSEC2_FLAGS TSEC_GIGABIT | |
257 | ||
258 | /* Options are: TSEC[0-1] */ | |
259 | #define CONFIG_ETHPRIME "TSEC0" | |
10a36a98 WD |
260 | |
261 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ | |
262 | ||
263 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
264 | #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ | |
265 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
266 | ||
267 | #if (CONFIG_ETHER_INDEX == 2) | |
268 | /* | |
269 | * - Rx-CLK is CLK13 | |
270 | * - Tx-CLK is CLK14 | |
271 | * - Select bus for bd/buffers | |
272 | * - Full duplex | |
273 | */ | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
275 | #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
276 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
277 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) | |
10a36a98 WD |
278 | |
279 | #elif (CONFIG_ETHER_INDEX == 3) | |
280 | /* need more definitions here for FE3 */ | |
281 | #endif /* CONFIG_ETHER_INDEX */ | |
282 | ||
283 | #define CONFIG_MII /* MII PHY management */ | |
284 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
285 | /* | |
286 | * GPIO pins used for bit-banged MII communications | |
287 | */ | |
288 | #define MDIO_PORT 2 /* Port C */ | |
289 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) | |
290 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
291 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
292 | ||
293 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
294 | else iop->pdat &= ~0x00400000 | |
295 | ||
296 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
297 | else iop->pdat &= ~0x00200000 | |
298 | ||
299 | #define MIIDELAY udelay(1) | |
300 | ||
301 | #endif | |
302 | ||
303 | /*----------------------------------------------------------------------- | |
304 | * FLASH and environment organization | |
305 | */ | |
306 | ||
6d0f6bcf | 307 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 308 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
10a36a98 | 309 | #if 0 |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
311 | #define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ | |
10a36a98 | 312 | #endif |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
314 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
10a36a98 | 315 | |
6d0f6bcf JCPV |
316 | #undef CONFIG_SYS_FLASH_CHECKSUM |
317 | #define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ | |
318 | #define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ | |
10a36a98 | 319 | |
6d0f6bcf | 320 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
10a36a98 WD |
321 | |
322 | #if 0 | |
323 | /* XXX This doesn't work and I don't want to fix it */ | |
6d0f6bcf JCPV |
324 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
325 | #define CONFIG_SYS_RAMBOOT | |
10a36a98 | 326 | #else |
6d0f6bcf | 327 | #undef CONFIG_SYS_RAMBOOT |
10a36a98 WD |
328 | #endif |
329 | #endif | |
330 | ||
331 | /* Environment */ | |
6d0f6bcf | 332 | #if !defined(CONFIG_SYS_RAMBOOT) |
10a36a98 | 333 | #if defined(CONFIG_RAM_AS_FLASH) |
93f6d725 | 334 | #define CONFIG_ENV_IS_NOWHERE |
6d0f6bcf | 335 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) |
0e8d1586 | 336 | #define CONFIG_ENV_SIZE 0x2000 |
10a36a98 | 337 | #else |
5a1aceb0 | 338 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 339 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
6d0f6bcf | 340 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 341 | #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */ |
10a36a98 WD |
342 | #endif |
343 | #else | |
6d0f6bcf | 344 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 345 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 346 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 347 | #define CONFIG_ENV_SIZE 0x2000 |
10a36a98 WD |
348 | #endif |
349 | ||
c158bcac | 350 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600" |
10a36a98 | 351 | /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ |
10a36a98 WD |
352 | #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ |
353 | ||
354 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 355 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
10a36a98 | 356 | |
2835e518 | 357 | |
079a136c JL |
358 | /* |
359 | * BOOTP options | |
360 | */ | |
361 | #define CONFIG_BOOTP_BOOTFILESIZE | |
362 | #define CONFIG_BOOTP_BOOTPATH | |
363 | #define CONFIG_BOOTP_GATEWAY | |
364 | #define CONFIG_BOOTP_HOSTNAME | |
365 | ||
366 | ||
2835e518 JL |
367 | /* |
368 | * Command line configuration. | |
369 | */ | |
370 | #include <config_cmd_default.h> | |
371 | ||
372 | #define CONFIG_CMD_PING | |
373 | #define CONFIG_CMD_I2C | |
374 | ||
375 | #if defined(CONFIG_PCI) | |
376 | #define CONFIG_CMD_PCI | |
377 | #endif | |
378 | ||
379 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
380 | #define CONFIG_CMD_MII | |
381 | #endif | |
382 | ||
6d0f6bcf | 383 | #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) |
2835e518 JL |
384 | #undef CONFIG_CMD_ENV |
385 | #undef CONFIG_CMD_LOADS | |
10a36a98 WD |
386 | #endif |
387 | ||
10a36a98 WD |
388 | |
389 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
390 | ||
391 | /* | |
392 | * Miscellaneous configurable options | |
393 | */ | |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
395 | #define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */ | |
2835e518 | 396 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 397 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
10a36a98 | 398 | #else |
6d0f6bcf | 399 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
10a36a98 | 400 | #endif |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
402 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
403 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
404 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ | |
405 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
10a36a98 WD |
406 | |
407 | /* | |
408 | * For booting Linux, the board info and command line data | |
409 | * have to be in the first 8 MB of memory, since this is | |
410 | * the maximum mapped by the Linux kernel during initialization. | |
411 | */ | |
6d0f6bcf | 412 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
10a36a98 | 413 | |
10a36a98 WD |
414 | /* |
415 | * Internal Definitions | |
416 | * | |
417 | * Boot Flags | |
418 | */ | |
419 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
420 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
421 | ||
2835e518 | 422 | #if defined(CONFIG_CMD_KGDB) |
37fef499 PG |
423 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
424 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
10a36a98 WD |
425 | #endif |
426 | ||
10a36a98 | 427 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
c158bcac PG |
428 | #define CONFIG_HAS_ETH0 |
429 | #define CONFIG_HAS_ETH1 | |
10a36a98 WD |
430 | #endif |
431 | ||
c158bcac PG |
432 | /* You can compile in a MAC address and your custom net settings by using |
433 | * the following syntax. Your board should be marked with the assigned | |
434 | * MAC addresses directly on it. | |
435 | * | |
436 | * #define CONFIG_ETHADDR de:ad:be:ef:00:00 | |
437 | * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s! | |
438 | * #define CONFIG_SERVERIP <server ip> | |
439 | * #define CONFIG_IPADDR <board ip> | |
440 | * #define CONFIG_GATEWAYIP <gateway ip> | |
441 | * #define CONFIG_NETMASK <your netmask> | |
442 | */ | |
443 | ||
10a36a98 WD |
444 | #define CONFIG_HOSTNAME SBC8560 |
445 | #define CONFIG_ROOTPATH /home/ppc | |
37fef499 PG |
446 | #define CONFIG_BOOTFILE uImage |
447 | ||
448 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
449 | "netdev=eth0\0" \ | |
450 | "consoledev=ttyS0\0" \ | |
451 | "ramdiskaddr=2000000\0" \ | |
452 | "ramdiskfile=ramdisk.uboot\0" \ | |
453 | "fdtaddr=c00000\0" \ | |
454 | "fdtfile=sbc8560.dtb\0" | |
455 | ||
456 | #define CONFIG_NFSBOOTCOMMAND \ | |
457 | "setenv bootargs root=/dev/nfs rw " \ | |
458 | "nfsroot=$serverip:$rootpath " \ | |
459 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
460 | "console=$consoledev,$baudrate $othbootargs;" \ | |
461 | "tftp $loadaddr $bootfile;" \ | |
462 | "tftp $fdtaddr $fdtfile;" \ | |
463 | "bootm $loadaddr - $fdtaddr" | |
464 | ||
465 | ||
466 | #define CONFIG_RAMBOOTCOMMAND \ | |
467 | "setenv bootargs root=/dev/ram rw " \ | |
468 | "console=$consoledev,$baudrate $othbootargs;" \ | |
469 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
470 | "tftp $loadaddr $bootfile;" \ | |
471 | "tftp $fdtaddr $fdtfile;" \ | |
472 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
473 | ||
474 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
10a36a98 WD |
475 | |
476 | #endif /* __CONFIG_H */ |