[people/ms/u-boot.git] / include / configs / sbc8560.h

/*
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
 * Added support for Wind River SBC8560 board
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* mpc8560ads board configuration file */
/* please refer to doc/README.mpc85xx for more info */
/* make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE			*/
#define CONFIG_E500		1	/* BOOKE e500 family		*/
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/


#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_SBC8560		1	/* configuration for SBC8560 board */

/* XXX flagging this as something I might want to delete */
#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific	*/

#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
#undef	CONFIG_PCI			/* pci ethernet support		*/
#undef  CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#define CONFIG_ENV_OVERWRITE

/* Using Localbus SDRAM to emulate flash before we can program the flash,
 * normally you need a flash-boot image(u-boot.bin), if so undef this.
 */
#undef CONFIG_RAM_AS_FLASH

#if defined(CONFIG_PCI_66)		/* some PCI card is 33Mhz only	*/
  #define CONFIG_SYS_CLK_FREQ	66000000/* sysclk for MPC85xx		*/
#else
  #define CONFIG_SYS_CLK_FREQ	33000000/* most pci cards are 33Mhz	*/
#endif

/* below can be toggled for performance analysis. otherwise use default */
#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
#undef	CONFIG_BTB			    /* toggle branch predition	*/
#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/

#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
#define CFG_MEMTEST_START	0x00200000  /* memtest region */
#define CFG_MEMTEST_END		0x00400000

#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
#endif

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/

#if XXX
  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
#else
  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
#endif
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/

#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */

#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */

#if defined(CONFIG_MPC85xx_REV1)
  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
#endif

#undef CONFIG_CLOCKS_IN_MHZ

#if defined(CONFIG_RAM_AS_FLASH)
  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
#else /* Boot from real Flash */
  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
#endif
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/

/* local bus definitions */
#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
#define CFG_OR1_PRELIM		0xfc000ff7

#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
#define CFG_OR2_PRELIM		0x00000000

#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
#define CFG_OR3_PRELIM		0xfc000cc1

#if defined(CONFIG_RAM_AS_FLASH)
  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
#else
  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
#endif
#define CFG_OR4_PRELIM		0xfc000cc1

#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
#if 1
  #define CFG_OR5_PRELIM	0xff000ff7
#else
  #define CFG_OR5_PRELIM	0xff0000f0
#endif

#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
#define CFG_OR6_PRELIM		0xfc000ff7
#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
#define CFG_LBC_LBCR		0x00000000
#define CFG_LBC_LSRT		0x20000000
#define CFG_LBC_MRTPR		0x20000000
#define CFG_LBC_LSDMR_1		0x2861b723
#define CFG_LBC_LSDMR_2		0x0861b723
#define CFG_LBC_LSDMR_3		0x0861b723
#define CFG_LBC_LSDMR_4		0x1861b723
#define CFG_LBC_LSDMR_5		0x4061b723

/* just hijack the MOT BCSR def for SBC8560 misc devices */
#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
/* the size of CS5 needs to be >= 16M for TLB and LAW setups */

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
#undef	CONFIG_CONS_NONE			/* define if console on something else */

#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
#define CONFIG_BAUDRATE		9600

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000

#define CFG_PCI_MEM_BASE	0xC0000000
#define CFG_PCI_MEM_PHYS	0xC0000000
#define CFG_PCI_MEM_SIZE	0x10000000

#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */

#  define CONFIG_NET_MULTI	1
#  define CONFIG_MII		1	/* MII PHY management		*/
#  define CONFIG_MPC85xx_TSEC1
#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
#  define TSEC1_PHY_ADDR	25
#  define TSEC1_PHYIDX		0
/* Options are: TSEC0 */
#  define CONFIG_ETHPRIME		"TSEC0"

#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

  #undef  CONFIG_ETHER_NONE		/* define if ether on something else */
  #define CONFIG_ETHER_ON_FCC2		/* cpm FCC ethernet support	*/
  #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */

  #if (CONFIG_ETHER_INDEX == 2)
    /*
     * - Rx-CLK is CLK13
     * - Tx-CLK is CLK14
     * - Select bus for bd/buffers
     * - Full duplex
     */
    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
    #define CFG_CPMFCR_RAMTYPE	0
    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)

  #elif (CONFIG_ETHER_INDEX == 3)
    /* need more definitions here for FE3 */
  #endif				/* CONFIG_ETHER_INDEX */

  #define CONFIG_MII			/* MII PHY management */
  #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
  /*
   * GPIO pins used for bit-banged MII communications
   */
  #define MDIO_PORT	2		/* Port C */
  #define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
  #define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
  #define MDIO_READ	((iop->pdat &  0x00400000) != 0)

  #define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

  #define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

  #define MIIDELAY	udelay(1)

#endif

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
#if 0
#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
#endif
#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/

#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/

#if 0
/* XXX This doesn't work and I don't want to fix it */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  #define CFG_RAMBOOT
#else
  #undef  CFG_RAMBOOT
#endif
#endif

/* Environment */
#if !defined(CFG_RAMBOOT)
  #if defined(CONFIG_RAM_AS_FLASH)
    #define CFG_ENV_IS_NOWHERE
    #define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
    #define CFG_ENV_SIZE	0x2000
  #else
    #define CFG_ENV_IS_IN_FLASH	1
    #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
    #define CFG_ENV_ADDR	(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
    #define CFG_ENV_SIZE	0x2000 /* CFG_ENV_SECT_SIZE */
  #endif
#else
  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
  #define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif

#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"SBC8560=> " /* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x1000000	/* default load address */
#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#  define CONFIG_ETHADDR	00:01:af:07:9b:8a
#  define CONFIG_HAS_ETH1
#  define CONFIG_ETH1ADDR	00:01:af:07:9b:8b
#  define CONFIG_HAS_ETH2
#  define CONFIG_ETH2ADDR	00:01:af:07:9b:8c
#endif

#define CONFIG_SERVERIP		192.168.0.131
#define CONFIG_IPADDR		192.168.0.105
#define CONFIG_GATEWAYIP	0.0.0.0
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_HOSTNAME		SBC8560
#define CONFIG_ROOTPATH		/home/ppc
#define CONFIG_BOOTFILE		pImage

#endif	/* __CONFIG_H */
Commit	Line	Data
10a36a98 WD	1	/*
	2	* (C) Copyright 2002,2003 Motorola,Inc.
	3	* Xianghua Xiao <X.Xiao@motorola.com>
	4	*
	5	* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
	6	* Added support for Wind River SBC8560 board
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/* mpc8560ads board configuration file */
	28	/* please refer to doc/README.mpc85xx for more info */
	29	/* make sure you change the MAC address and other network params first,
	30	* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	/* High Level Configuration Options */
	37	#define CONFIG_BOOKE 1 /* BOOKE */
	38	#define CONFIG_E500 1 /* BOOKE e500 family */
	39	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	40	#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
	41
	42
9c4c5ae3	43	#define CONFIG_CPM2 1 /* has CPM2 */
10a36a98 WD	44	#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
	45
	46	/* XXX flagging this as something I might want to delete */
	47	#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
	48
	49	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	50	#undef CONFIG_PCI /* pci ethernet support */
	51	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
	52
e2b159d0	53	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
10a36a98 WD	54
	55	#define CONFIG_ENV_OVERWRITE
	56
	57	/* Using Localbus SDRAM to emulate flash before we can program the flash,
	58	* normally you need a flash-boot image(u-boot.bin), if so undef this.
	59	*/
	60	#undef CONFIG_RAM_AS_FLASH
	61
	62	#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
	63	#define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
	64	#else
	65	#define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
	66	#endif
	67
	68	/* below can be toggled for performance analysis. otherwise use default */
	69	#define CONFIG_L2_CACHE /* toggle L2 cache */
	70	#undef CONFIG_BTB /* toggle branch predition */
	71	#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
	72
	73	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	74
	75	#undef CFG_DRAM_TEST /* memory test, takes time */
	76	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
	77	#define CFG_MEMTEST_END 0x00400000
	78
	79	#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) \|\| \
	80	defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) \|\| \
	81	defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
	82	#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
	83	#endif
	84
	85	/*
	86	* Base addresses -- Note these are effective addresses where the
	87	* actual resources get mapped (not physical addresses)
	88	*/
	89	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	90
	91	#if XXX
	92	#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
	93	#else
	94	#define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
	95	#endif
	96	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
	97
	98	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
	99	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	100	#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
	101	#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
	102
	103	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	104	#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	105
	106	#if defined(CONFIG_MPC85xx_REV1)
	107	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	108	#endif
	109
	110	#undef CONFIG_CLOCKS_IN_MHZ
	111
	112	#if defined(CONFIG_RAM_AS_FLASH)
	113	#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
	114	#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
	115	#define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
	116	#define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
	117	#else /* Boot from real Flash */
118	#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
119	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
120	#define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
121	#define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
122	#endif
123	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
124
125	/* local bus definitions */
126	#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
127	#define CFG_OR1_PRELIM 0xfc000ff7
128
129	#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
130	#define CFG_OR2_PRELIM 0x00000000
131
132	#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
133	#define CFG_OR3_PRELIM 0xfc000cc1
134
135	#if defined(CONFIG_RAM_AS_FLASH)
136	#define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
137	#else
138	#define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
139	#endif
140	#define CFG_OR4_PRELIM 0xfc000cc1
141
142	#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
143	#if 1
144	#define CFG_OR5_PRELIM 0xff000ff7
145	#else
146	#define CFG_OR5_PRELIM 0xff0000f0
147	#endif
148
149	#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
150	#define CFG_OR6_PRELIM 0xfc000ff7
151	#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
152	#define CFG_LBC_LBCR 0x00000000
153	#define CFG_LBC_LSRT 0x20000000
154	#define CFG_LBC_MRTPR 0x20000000
155	#define CFG_LBC_LSDMR_1 0x2861b723
156	#define CFG_LBC_LSDMR_2 0x0861b723
157	#define CFG_LBC_LSDMR_3 0x0861b723
158	#define CFG_LBC_LSDMR_4 0x1861b723
159	#define CFG_LBC_LSDMR_5 0x4061b723
160
161	/* just hijack the MOT BCSR def for SBC8560 misc devices */
162	#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)\|0x00400000)
163	/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
164
165	#define CONFIG_L1_INIT_RAM
166	#define CFG_INIT_RAM_LOCK 1
167	#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
168	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
169
170	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
171	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
172	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
173
174	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
175	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
176
177	/* Serial Port */
178	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
179	#undef CONFIG_CONS_NONE /* define if console on something else */
180
181	#define CONFIG_CONS_INDEX 1
182	#undef CONFIG_SERIAL_SOFTWARE_FIFO
183	#define CFG_NS16550
184	#define CFG_NS16550_SERIAL
185	#define CFG_NS16550_REG_SIZE 1
186	#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
187	#define CONFIG_BAUDRATE 9600
188
189	#define CFG_BAUDRATE_TABLE \
190	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
191
192	#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
193	#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
194
195	/* Use the HUSH parser */
196	#define CFG_HUSH_PARSER
197	#ifdef CFG_HUSH_PARSER
198	#define CFG_PROMPT_HUSH_PS2 "> "
199	#endif
200
20476726 JL	201	/*
	202	* I2C
	203	*/
	204	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	205	#define CONFIG_HARD_I2C /* I2C with hardware support*/
10a36a98 WD	206	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	207	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	208	#define CFG_I2C_SLAVE 0x7F
	209	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
20476726	210	#define CFG_I2C_OFFSET 0x3000
10a36a98 WD	211
	212	#define CFG_PCI_MEM_BASE 0xC0000000
	213	#define CFG_PCI_MEM_PHYS 0xC0000000
	214	#define CFG_PCI_MEM_SIZE 0x10000000
	215
	216	#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
	217
d9b94f28 JL	218	# define CONFIG_NET_MULTI 1
	219	# define CONFIG_MII 1 /* MII PHY management */
	220	# define CONFIG_MPC85xx_TSEC1
	221	# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
	222	# define TSEC1_PHY_ADDR 25
	223	# define TSEC1_PHYIDX 0
	224	/* Options are: TSEC0 */
	225	# define CONFIG_ETHPRIME "TSEC0"
10a36a98 WD	226
	227	#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
	228
	229	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	230	#define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
	231	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
	232
	233	#if (CONFIG_ETHER_INDEX == 2)
	234	/*
	235	* - Rx-CLK is CLK13
	236	* - Tx-CLK is CLK14
	237	* - Select bus for bd/buffers
	238	* - Full duplex
	239	*/
	240	#define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	241	#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	242	#define CFG_CPMFCR_RAMTYPE 0
	243	#define CFG_FCC_PSMR (FCC_PSMR_FDE)
	244
	245	#elif (CONFIG_ETHER_INDEX == 3)
	246	/* need more definitions here for FE3 */
	247	#endif /* CONFIG_ETHER_INDEX */
	248
	249	#define CONFIG_MII /* MII PHY management */
	250	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	251	/*
	252	* GPIO pins used for bit-banged MII communications
	253	*/
	254	#define MDIO_PORT 2 /* Port C */
	255	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	256	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	257	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	258
	259	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	260	else iop->pdat &= ~0x00400000
	261
	262	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	263	else iop->pdat &= ~0x00200000
	264
	265	#define MIIDELAY udelay(1)
	266
	267	#endif
	268
	269	/*-----------------------------------------------------------------------
	270	* FLASH and environment organization
	271	*/
	272
	273	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
	274	#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
	275	#if 0
	276	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	277	#define CFG_FLASH_PROTECTION /* use hardware protection */
	278	#endif
	279	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	280	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	281
	282	#undef CFG_FLASH_CHECKSUM
	283	#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
	284	#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
	285
	286	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	287
	288	#if 0
	289	/* XXX This doesn't work and I don't want to fix it */
290	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
291	#define CFG_RAMBOOT
292	#else
293	#undef CFG_RAMBOOT
294	#endif
295	#endif
296
297	/* Environment */
298	#if !defined(CFG_RAMBOOT)
299	#if defined(CONFIG_RAM_AS_FLASH)
300	#define CFG_ENV_IS_NOWHERE
301	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
302	#define CFG_ENV_SIZE 0x2000
303	#else
304	#define CFG_ENV_IS_IN_FLASH 1
305	#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
306	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
307	#define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
308	#endif
309	#else
310	#define CFG_NO_FLASH 1 /* Flash is not usable now */
311	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
312	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
313	#define CFG_ENV_SIZE 0x2000
314	#endif
315
316	#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
317	/#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"/
318	#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
319	#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
320
321	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
322	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
323
2835e518	324
079a136c JL	325	/*
	326	* BOOTP options
	327	*/
	328	#define CONFIG_BOOTP_BOOTFILESIZE
	329	#define CONFIG_BOOTP_BOOTPATH
	330	#define CONFIG_BOOTP_GATEWAY
	331	#define CONFIG_BOOTP_HOSTNAME
	332
	333
2835e518 JL	334	/*
	335	* Command line configuration.
	336	*/
	337	#include <config_cmd_default.h>
	338
	339	#define CONFIG_CMD_PING
	340	#define CONFIG_CMD_I2C
	341
	342	#if defined(CONFIG_PCI)
	343	#define CONFIG_CMD_PCI
	344	#endif
	345
	346	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
	347	#define CONFIG_CMD_MII
	348	#endif
	349
10a36a98	350	#if defined(CFG_RAMBOOT) \|\| defined(CONFIG_RAM_AS_FLASH)
2835e518 JL	351	#undef CONFIG_CMD_ENV
2835e518 JL	352	#undef CONFIG_CMD_LOADS
10a36a98 WD	353	#endif
10a36a98 WD	354
10a36a98 WD	355
	356	#undef CONFIG_WATCHDOG /* watchdog disabled */
	357
	358	/*
	359	* Miscellaneous configurable options
	360	*/
	361	#define CFG_LONGHELP /* undef to save memory */
	362	#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
2835e518	363	#if defined(CONFIG_CMD_KGDB)
10a36a98 WD	364	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	365	#else
	366	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	367	#endif
	368	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	369	#define CFG_MAXARGS 16 /* max number of command args */
	370	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	371	#define CFG_LOAD_ADDR 0x1000000 /* default load address */
	372	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	373
	374	/*
	375	* For booting Linux, the board info and command line data
	376	* have to be in the first 8 MB of memory, since this is
	377	* the maximum mapped by the Linux kernel during initialization.
	378	*/
	379	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	380
10a36a98 WD	381	/*
	382	* Internal Definitions
	383	*
	384	* Boot Flags
	385	*/
	386	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	387	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	388
2835e518	389	#if defined(CONFIG_CMD_KGDB)
10a36a98 WD	390	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	391	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	392	#endif
	393
	394	/Note: change below for your network setting!!! /
	395	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
e2ffd59b WD	396	# define CONFIG_ETHADDR 00:01:af:07:9b:8a
	397	# define CONFIG_HAS_ETH1
	398	# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
	399	# define CONFIG_HAS_ETH2
	400	# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
10a36a98 WD	401	#endif
	402
	403	#define CONFIG_SERVERIP 192.168.0.131
	404	#define CONFIG_IPADDR 192.168.0.105
	405	#define CONFIG_GATEWAYIP 0.0.0.0
	406	#define CONFIG_NETMASK 255.255.255.0
	407	#define CONFIG_HOSTNAME SBC8560
	408	#define CONFIG_ROOTPATH /home/ppc
	409	#define CONFIG_BOOTFILE pImage
	410
	411	#endif /* __CONFIG_H */