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ca43ba18 HS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, <hs@denx.de>. | |
4 | * | |
5 | * From: | |
6 | * (C) Copyright 2003 | |
7 | * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
ca43ba18 HS |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | #undef USE_VGA_GRAPHICS | |
16 | ||
17 | /* Memory Map | |
6d3e0107 WD |
18 | * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB) |
19 | * 0x74000000 .... 0x740FFFFF -> CS#6 | |
20 | * 0x74100000 .... 0x741FFFFF -> CS#7 | |
21 | * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB | |
22 | * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE | |
23 | * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB) | |
24 | * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB) | |
25 | * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB) | |
26 | * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB) | |
27 | * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored) | |
28 | * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB) | |
29 | * | |
30 | * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1) | |
31 | * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF) | |
32 | * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF) | |
33 | * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF) | |
34 | * 0xEED00000 .... 0xEED00003 -> PCI-Bus | |
35 | * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers | |
36 | * 0xEF40003F .... 0xEF5FFFFF -> reserved | |
37 | * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB) | |
38 | * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB) | |
39 | * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices | |
40 | * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB) | |
41 | * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices | |
42 | * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB) | |
43 | */ | |
ca43ba18 | 44 | |
9045f33c | 45 | #define CONFIG_SC3 1 |
ca43ba18 HS |
46 | #define CONFIG_4xx 1 |
47 | #define CONFIG_405GP 1 | |
48 | ||
2ae18241 WD |
49 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
50 | ||
ca43ba18 | 51 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
3a8f28d0 | 52 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ |
ca43ba18 HS |
53 | |
54 | /* | |
6d3e0107 WD |
55 | * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range |
56 | * If undefined, IDE access uses a seperat emulation with higher access speed. | |
ca43ba18 | 57 | * Consider to inform your Linux IDE driver about the different addresses! |
639221c7 | 58 | * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE! |
ca43ba18 HS |
59 | */ |
60 | #define IDE_USES_ISA_EMULATION | |
61 | ||
62 | /*----------------------------------------------------------------------- | |
63 | * Serial Port | |
64 | *----------------------------------------------------------------------*/ | |
550650dd SR |
65 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
66 | #define CONFIG_SYS_NS16550 | |
67 | #define CONFIG_SYS_NS16550_SERIAL | |
68 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
69 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
ca43ba18 HS |
70 | |
71 | /* | |
72 | * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz | |
73 | */ | |
74 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
75 | ||
76 | /* | |
77 | * define CONFIG_BAUDRATE to the baudrate value you want to use as default | |
78 | */ | |
79 | #define CONFIG_BAUDRATE 115200 | |
f11033e7 | 80 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
ca43ba18 | 81 | |
1bbbbdd2 | 82 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 83 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
1bbbbdd2 WD |
84 | "echo" |
85 | ||
86 | #undef CONFIG_BOOTARGS | |
87 | ||
88 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
89 | "netdev=eth0\0" \ | |
90 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
91 | "nfsroot=${serverip}:${rootpath}\0" \ | |
92 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
cb482072 HS |
93 | "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \ |
94 | "rootfstype=jffs2\0" \ | |
1bbbbdd2 WD |
95 | "addip=setenv bootargs ${bootargs} " \ |
96 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
97 | ":${hostname}:${netdev}:off panic=1\0" \ | |
a7090b99 WD |
98 | "addcons=setenv bootargs ${bootargs} " \ |
99 | "console=ttyS0,${baudrate}\0" \ | |
100 | "flash_nfs=run nfsargs addip addcons;" \ | |
1bbbbdd2 | 101 | "bootm ${kernel_addr}\0" \ |
a7090b99 WD |
102 | "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \ |
103 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ | |
104 | "bootm\0" \ | |
1bbbbdd2 WD |
105 | "rootpath=/opt/eldk/ppc_4xx\0" \ |
106 | "bootfile=/tftpboot/sc3/uImage\0" \ | |
d0b6e140 | 107 | "u-boot=/tftpboot/sc3/u-boot.bin\0" \ |
74de7aef | 108 | "setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0" \ |
1bbbbdd2 WD |
109 | "kernel_addr=FFE08000\0" \ |
110 | "" | |
111 | #undef CONFIG_BOOTCOMMAND | |
112 | ||
ca43ba18 | 113 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
6d0f6bcf | 114 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
ca43ba18 HS |
115 | |
116 | #if 1 /* feel free to disable for development */ | |
117 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ | |
c37207d7 WD |
118 | #define CONFIG_AUTOBOOT_PROMPT \ |
119 | "\nSC3 - booting... stop with ENTER\n" | |
9045f33c WD |
120 | #define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */ |
121 | #define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */ | |
ca43ba18 HS |
122 | #endif |
123 | ||
124 | /* | |
125 | * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after | |
126 | * the CONFIG_BOOTDELAY delay to boot your machine | |
127 | */ | |
128 | #define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm" | |
129 | ||
130 | /* | |
131 | * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't | |
132 | * set different values at the u-boot prompt | |
133 | */ | |
134 | #ifdef USE_VGA_GRAPHICS | |
135 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re" | |
136 | #else | |
137 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp" | |
138 | #endif | |
139 | /* | |
140 | * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT | |
141 | * This reserves memory bank #4 for this purpose | |
142 | */ | |
143 | #undef CONFIG_ISP1161_PRESENT | |
144 | ||
145 | #undef CONFIG_LOADS_ECHO /* no echo on for serial download */ | |
6d0f6bcf | 146 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
ca43ba18 | 147 | |
ca43ba18 HS |
148 | /* #define CONFIG_EEPRO100_SROM_WRITE */ |
149 | /* #define CONFIG_SHOW_MAC */ | |
150 | #define CONFIG_EEPRO100 | |
96e21f86 BW |
151 | |
152 | #define CONFIG_PPC4xx_EMAC | |
ca43ba18 HS |
153 | #define CONFIG_MII 1 /* add 405GP MII PHY management */ |
154 | #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ | |
155 | ||
079a136c JL |
156 | /* |
157 | * BOOTP options | |
158 | */ | |
159 | #define CONFIG_BOOTP_BOOTFILESIZE | |
160 | #define CONFIG_BOOTP_BOOTPATH | |
161 | #define CONFIG_BOOTP_GATEWAY | |
162 | #define CONFIG_BOOTP_HOSTNAME | |
163 | ||
164 | ||
46da1e96 JL |
165 | /* |
166 | * Command line configuration. | |
167 | */ | |
168 | #include <config_cmd_default.h> | |
169 | ||
170 | ||
74de7aef | 171 | #define CONFIG_CMD_CACHE |
46da1e96 JL |
172 | #define CONFIG_CMD_DATE |
173 | #define CONFIG_CMD_DHCP | |
46da1e96 | 174 | #define CONFIG_CMD_ELF |
74de7aef WD |
175 | #define CONFIG_CMD_I2C |
176 | #define CONFIG_CMD_IDE | |
177 | #define CONFIG_CMD_IRQ | |
178 | #define CONFIG_CMD_JFFS2 | |
179 | #define CONFIG_CMD_MII | |
180 | #define CONFIG_CMD_NAND | |
181 | #define CONFIG_CMD_NET | |
182 | #define CONFIG_CMD_PCI | |
183 | #define CONFIG_CMD_PING | |
184 | #define CONFIG_CMD_SOURCE | |
46da1e96 | 185 | |
ca43ba18 HS |
186 | |
187 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
188 | ||
189 | /* | |
190 | * Miscellaneous configurable options | |
191 | */ | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
193 | #define CONFIG_SYS_PROMPT "SC3> " /* Monitor Command Prompt */ | |
194 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
ca43ba18 | 195 | |
6d0f6bcf | 196 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
ca43ba18 | 197 | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
199 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
ca43ba18 | 200 | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
202 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
ca43ba18 HS |
203 | |
204 | /* | |
6d0f6bcf JCPV |
205 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
206 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
207 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
ca43ba18 HS |
208 | * The Linux BASE_BAUD define should match this configuration. |
209 | * baseBaud = cpuClock/(uartDivisor*16) | |
6d0f6bcf | 210 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
ca43ba18 HS |
211 | * set Linux BASE_BAUD to 403200. |
212 | * | |
213 | * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to | |
214 | * (see 405GP datasheet for descritpion) | |
215 | */ | |
6d0f6bcf JCPV |
216 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
217 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
218 | #define CONFIG_SYS_BASE_BAUD 921600 /* internal clock */ | |
ca43ba18 HS |
219 | |
220 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 221 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
ca43ba18 HS |
222 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
223 | ||
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
225 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
ca43ba18 | 226 | |
6d0f6bcf | 227 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
ca43ba18 HS |
228 | |
229 | /*----------------------------------------------------------------------- | |
230 | * IIC stuff | |
231 | *----------------------------------------------------------------------- | |
232 | */ | |
880540de DE |
233 | #define CONFIG_SYS_I2C |
234 | #define CONFIG_SYS_I2C_PPC4XX | |
235 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
ca43ba18 HS |
236 | |
237 | #define I2C_INIT | |
238 | #define I2C_ACTIVE 0 | |
239 | #define I2C_TRISTATE 0 | |
240 | ||
880540de DE |
241 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
242 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* mask valid bits */ | |
ca43ba18 HS |
243 | |
244 | #define CONFIG_RTC_DS1337 | |
6d0f6bcf | 245 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
ca43ba18 HS |
246 | |
247 | /*----------------------------------------------------------------------- | |
248 | * PCI stuff | |
249 | *----------------------------------------------------------------------- | |
250 | */ | |
f11033e7 WD |
251 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
252 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
253 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
ca43ba18 | 254 | |
f11033e7 | 255 | #define CONFIG_PCI /* include pci support */ |
842033e6 | 256 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
f11033e7 WD |
257 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
258 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
259 | /* resource configuration */ | |
ca43ba18 HS |
260 | |
261 | /* If you want to see, whats connected to your PCI bus */ | |
262 | /* #define CONFIG_PCI_SCAN_SHOW */ | |
263 | ||
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
265 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
266 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
267 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
268 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
269 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
270 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
271 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
ca43ba18 HS |
272 | |
273 | /*----------------------------------------------------------------------- | |
274 | * External peripheral base address | |
275 | *----------------------------------------------------------------------- | |
276 | */ | |
46da1e96 | 277 | #if !defined(CONFIG_CMD_IDE) |
ca43ba18 | 278 | |
f11033e7 WD |
279 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
280 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
ca43ba18 HS |
281 | |
282 | /*----------------------------------------------------------------------- | |
283 | * IDE/ATA stuff | |
284 | *----------------------------------------------------------------------- | |
285 | */ | |
46da1e96 | 286 | #else |
ca43ba18 HS |
287 | #define CONFIG_START_IDE 1 /* check, if use IDE */ |
288 | ||
f11033e7 WD |
289 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
290 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
291 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
ca43ba18 HS |
292 | |
293 | #define CONFIG_ATAPI | |
294 | #define CONFIG_DOS_PARTITION | |
6d0f6bcf | 295 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ |
ca43ba18 HS |
296 | |
297 | #ifndef IDE_USES_ISA_EMULATION | |
298 | ||
299 | /* New and faster access */ | |
6d0f6bcf | 300 | #define CONFIG_SYS_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */ |
ca43ba18 HS |
301 | |
302 | /* How many IDE busses are available */ | |
6d0f6bcf | 303 | #define CONFIG_SYS_IDE_MAXBUS 1 |
ca43ba18 HS |
304 | |
305 | /* What IDE ports are available */ | |
6d0f6bcf JCPV |
306 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x000 /* first is available */ |
307 | #undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ | |
ca43ba18 HS |
308 | |
309 | /* access to the data port is calculated: | |
6d0f6bcf JCPV |
310 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ |
311 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
ca43ba18 HS |
312 | |
313 | /* access to the registers is calculated: | |
6d0f6bcf JCPV |
314 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ |
315 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
ca43ba18 HS |
316 | |
317 | /* access to the alternate register is calculated: | |
6d0f6bcf JCPV |
318 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ |
319 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */ | |
ca43ba18 HS |
320 | |
321 | #else /* IDE_USES_ISA_EMULATION */ | |
322 | ||
6d0f6bcf | 323 | #define CONFIG_SYS_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */ |
ca43ba18 HS |
324 | |
325 | /* How many IDE busses are available */ | |
6d0f6bcf | 326 | #define CONFIG_SYS_IDE_MAXBUS 1 |
ca43ba18 HS |
327 | |
328 | /* What IDE ports are available */ | |
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* first is available */ |
330 | #undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ | |
ca43ba18 HS |
331 | |
332 | /* access to the data port is calculated: | |
6d0f6bcf JCPV |
333 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ |
334 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
ca43ba18 HS |
335 | |
336 | /* access to the registers is calculated: | |
6d0f6bcf JCPV |
337 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ |
338 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
ca43ba18 HS |
339 | |
340 | /* access to the alternate register is calculated: | |
6d0f6bcf JCPV |
341 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ |
342 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */ | |
ca43ba18 HS |
343 | |
344 | #endif /* IDE_USES_ISA_EMULATION */ | |
345 | ||
46da1e96 | 346 | #endif |
ca43ba18 HS |
347 | |
348 | /* | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
350 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 | |
351 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 | |
ca43ba18 HS |
352 | */ |
353 | ||
354 | /*----------------------------------------------------------------------- | |
355 | * Start addresses for the final memory configuration | |
356 | * (Set up by the startup code) | |
6d0f6bcf | 357 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
ca43ba18 | 358 | * |
6d0f6bcf JCPV |
359 | * CONFIG_SYS_FLASH_BASE -> start address of internal flash |
360 | * CONFIG_SYS_MONITOR_BASE -> start of u-boot | |
ca43ba18 | 361 | */ |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
363 | #define CONFIG_SYS_FLASH_BASE 0xFFE00000 | |
5bea7e6c | 364 | |
14d0a02a | 365 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ |
5bea7e6c | 366 | #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) |
6d0f6bcf | 367 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ |
ca43ba18 HS |
368 | |
369 | /* | |
370 | * For booting Linux, the board info and command line data | |
371 | * have to be in the first 8 MiB of memory, since this is | |
372 | * the maximum mapped by the Linux kernel during initialization. | |
373 | */ | |
6d0f6bcf | 374 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
ca43ba18 | 375 | /*----------------------------------------------------------------------- |
f11033e7 | 376 | * FLASH organization ## FIXME: lookup in datasheet |
ca43ba18 | 377 | */ |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
379 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
ca43ba18 | 380 | |
6d0f6bcf | 381 | #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ |
00b1883a | 382 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ |
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
384 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ | |
385 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
386 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
387 | #define CONFIG_SYS_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */ | |
ca43ba18 | 388 | |
5a1aceb0 JCPV |
389 | #define CONFIG_ENV_IS_IN_FLASH 1 |
390 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
0e8d1586 JCPV |
391 | #define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */ |
392 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
393 | #define CONFIG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ | |
6d3e0107 WD |
394 | |
395 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
396 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
397 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
6d3e0107 | 398 | |
ca43ba18 HS |
399 | #endif |
400 | /* let us changing anything in our environment */ | |
401 | #define CONFIG_ENV_OVERWRITE | |
402 | ||
403 | /* | |
404 | * NAND-FLASH stuff | |
405 | */ | |
6d0f6bcf | 406 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
6d0f6bcf | 407 | #define CONFIG_SYS_NAND_BASE 0x77D00000 |
ca43ba18 | 408 | |
cb482072 HS |
409 | #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ |
410 | ||
51056dd9 | 411 | /* No command line, one static partition */ |
68d7d651 | 412 | #undef CONFIG_CMD_MTDPARTS |
cb482072 | 413 | #define CONFIG_JFFS2_DEV "nand0" |
51056dd9 WD |
414 | #define CONFIG_JFFS2_PART_SIZE 0x01000000 |
415 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
cb482072 | 416 | |
ca43ba18 HS |
417 | /* |
418 | * Init Memory Controller: | |
419 | * | |
420 | */ | |
421 | ||
6d0f6bcf | 422 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE |
ca43ba18 HS |
423 | #define FLASH_BASE1_PRELIM 0 |
424 | ||
425 | /*----------------------------------------------------------------------- | |
426 | * Some informations about the internal SRAM (OCM=On Chip Memory) | |
427 | * | |
6d0f6bcf JCPV |
428 | * CONFIG_SYS_OCM_DATA_ADDR -> location |
429 | * CONFIG_SYS_OCM_DATA_SIZE -> size | |
ca43ba18 HS |
430 | */ |
431 | ||
6d0f6bcf JCPV |
432 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
433 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
434 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
ca43ba18 HS |
435 | |
436 | /*----------------------------------------------------------------------- | |
437 | * Definitions for initial stack pointer and data area (in DPRAM): | |
438 | * - we are using the internal 4k SRAM, so we don't need data cache mapping | |
6d0f6bcf | 439 | * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR |
ca43ba18 | 440 | * - Stackpointer will be located to |
6d0f6bcf | 441 | * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF) |
a47a12be | 442 | * in arch/powerpc/cpu/ppc4xx/start.S |
ca43ba18 HS |
443 | */ |
444 | ||
6d0f6bcf | 445 | #undef CONFIG_SYS_INIT_DCACHE_CS |
ca43ba18 | 446 | /* Where the internal SRAM starts */ |
6d0f6bcf | 447 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR |
ca43ba18 | 448 | /* Where the internal SRAM ends (only offset) */ |
553f0982 | 449 | #define CONFIG_SYS_INIT_RAM_SIZE 0x0F00 |
ca43ba18 HS |
450 | |
451 | /* | |
452 | ||
6d0f6bcf | 453 | CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address |
f11033e7 WD |
454 | | | |
455 | | ^ | | |
456 | | | | | |
457 | | | Stack | | |
6d0f6bcf | 458 | CONFIG_SYS_GBL_DATA_OFFSET ----> ------------ |
f11033e7 WD |
459 | | | |
460 | | 64 Bytes | | |
461 | | | | |
553f0982 | 462 | CONFIG_SYS_INIT_RAM_SIZE ------> ------------ higher address |
ca43ba18 HS |
463 | (offset only) |
464 | ||
465 | */ | |
25ddd1fb | 466 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
ca43ba18 | 467 | /* Initial value of the stack pointern in internal SRAM */ |
6d0f6bcf | 468 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
ca43ba18 | 469 | |
ca43ba18 | 470 | /* ################################################################################### */ |
a47a12be | 471 | /* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */ |
ca43ba18 HS |
472 | /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ |
473 | ||
474 | /* This chip select accesses the boot device */ | |
475 | /* It depends on boot select switch if this device is 16 or 8 bit */ | |
476 | ||
6d0f6bcf JCPV |
477 | #undef CONFIG_SYS_EBC_PB0AP |
478 | #undef CONFIG_SYS_EBC_PB0CR | |
ca43ba18 | 479 | |
6d0f6bcf JCPV |
480 | #undef CONFIG_SYS_EBC_PB1AP |
481 | #undef CONFIG_SYS_EBC_PB1CR | |
ca43ba18 | 482 | |
6d0f6bcf JCPV |
483 | #undef CONFIG_SYS_EBC_PB2AP |
484 | #undef CONFIG_SYS_EBC_PB2CR | |
ca43ba18 | 485 | |
6d0f6bcf JCPV |
486 | #undef CONFIG_SYS_EBC_PB3AP |
487 | #undef CONFIG_SYS_EBC_PB3CR | |
ca43ba18 | 488 | |
6d0f6bcf JCPV |
489 | #undef CONFIG_SYS_EBC_PB4AP |
490 | #undef CONFIG_SYS_EBC_PB4CR | |
ca43ba18 | 491 | |
6d0f6bcf JCPV |
492 | #undef CONFIG_SYS_EBC_PB5AP |
493 | #undef CONFIG_SYS_EBC_PB5CR | |
ca43ba18 | 494 | |
6d0f6bcf JCPV |
495 | #undef CONFIG_SYS_EBC_PB6AP |
496 | #undef CONFIG_SYS_EBC_PB6CR | |
ca43ba18 | 497 | |
6d0f6bcf JCPV |
498 | #undef CONFIG_SYS_EBC_PB7AP |
499 | #undef CONFIG_SYS_EBC_PB7CR | |
ca43ba18 | 500 | |
6d0f6bcf | 501 | #define CONFIG_SYS_EBC_CFG 0xb84ef000 |
cb482072 | 502 | |
ee8028b7 | 503 | #undef CONFIG_SDRAM_BANK0 /* use private SDRAM initialization */ |
ca43ba18 HS |
504 | #undef CONFIG_SPD_EEPROM |
505 | ||
506 | /* | |
507 | * Define this to get more information about system configuration | |
508 | */ | |
509 | /* #define SC3_DEBUGOUT */ | |
510 | #undef SC3_DEBUGOUT | |
511 | ||
512 | /*********************************************************************** | |
513 | * External peripheral base address | |
514 | ***********************************************************************/ | |
515 | ||
6d0f6bcf | 516 | #define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000 |
ca43ba18 | 517 | /* |
fa82f871 | 518 | Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu. |
ca43ba18 | 519 | Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die |
fa82f871 | 520 | das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen |
ca43ba18 HS |
521 | auf ISA- und PCI-Zyklen) |
522 | */ | |
6d0f6bcf JCPV |
523 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 |
524 | /*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0x79000000 */ | |
ca43ba18 HS |
525 | |
526 | /************************************************************ | |
527 | * Video support | |
528 | ************************************************************/ | |
529 | ||
530 | #ifdef USE_VGA_GRAPHICS | |
531 | #define CONFIG_VIDEO /* To enable video controller support */ | |
532 | #define CONFIG_VIDEO_CT69000 | |
533 | #define CONFIG_CFB_CONSOLE | |
534 | /* #define CONFIG_VIDEO_LOGO */ | |
535 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
536 | #define CONFIG_VIDEO_SW_CURSOR | |
537 | /* #define CONFIG_VIDEO_HW_CURSOR */ | |
538 | #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ | |
539 | ||
540 | #define VIDEO_HW_RECTFILL | |
541 | #define VIDEO_HW_BITBLT | |
542 | ||
543 | #endif | |
544 | ||
545 | /************************************************************ | |
546 | * Ident | |
547 | ************************************************************/ | |
548 | #define CONFIG_SC3_VERSION "r1.4" | |
549 | ||
550 | #define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x) | |
551 | ||
552 | #endif /* __CONFIG_H */ |