[people/ms/u-boot.git] / include / configs / scb9328.h

/*
 * Copyright (C) 2003 ETC s.r.o.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Written by Peter Figuli <peposh@etc.sk>, 2003.
 *
 * 2003/13/06 Initial MP10 Support copied from wepep250
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARM920T		1     /* this is an ARM920T CPU	    */
#define CONFIG_IMX		1     /* in a Motorola MC9328MXL Chip */
#define CONFIG_SCB9328		1     /* on a scb9328tronix board */
#undef	CONFIG_USE_IRQ		      /* don't need use IRQ/FIQ	   */

#define CONFIG_IMX_SERIAL
#define CONFIG_IMX_SERIAL1
/*
 * Select serial console configuration
 */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP

#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_SOURCE

/*
 * Boot options. Setting delay to -1 stops autostart count down.
 * NOTE: Sending parameters to kernel depends on kernel version and
 * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
 * parameters at all! Do not get confused by them so.
 */
#define CONFIG_BOOTDELAY   -1
#define CONFIG_BOOTARGS	   "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
#define CONFIG_BOOTCOMMAND "bootm 10040000"
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ETHADDR		80:81:82:83:84:85
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		10.10.10.9
#define CONFIG_SERVERIP		10.10.10.10

/*
 * General options for u-boot. Modify to save memory foot print
 */
#define CONFIG_SYS_LONGHELP				      /* undef saves memory  */
#define CONFIG_SYS_PROMPT		"scb9328> "	      /* prompt string	     */
#define CONFIG_SYS_CBSIZE		256		      /* console I/O buffer  */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
#define CONFIG_SYS_MAXARGS		16		      /* max command args    */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	      /* boot args buf size  */

#define CONFIG_SYS_MEMTEST_START	0x08100000	      /* memtest test area   */
#define CONFIG_SYS_MEMTEST_END		0x08F00000

#define CONFIG_SYS_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
#define CONFIG_SYS_CPUSPEED		0x141	     /* core clock - register value  */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BAUDRATE 115200
/*
 * Definitions related to passing arguments to kernel.
 */
#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
#define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */

/*
 * Malloc pool need to host env + 128 Kb reserve for other allocations.
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10) )

#define CONFIG_STACKSIZE	(120<<10)      /* stack size		     */

#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4<<10)	       /* IRQ stack		     */
#define CONFIG_STACKSIZE_FIQ	(4<<10)	       /* FIQ stack		     */
#endif

/* SDRAM Setup Values
0x910a8300 Precharge Command CAS 3
0x910a8200 Precharge Command CAS 2

0xa10a8300 AutoRefresh Command CAS 3
0xa10a8200 Set AutoRefresh Command CAS 2 */

#define PRECHARGE_CMD 0x910a8200
#define AUTOREFRESH_CMD 0xa10a8200

/*
 * SDRAM Memory Map
 */
/* SH FIXME */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM */
#define SCB9328_SDRAM_1		0x08000000	/* SDRAM bank #1	   */
#define SCB9328_SDRAM_1_SIZE	0x01000000	/* 16 MB		   */

#define CONFIG_SYS_TEXT_BASE	0x10000000

#define CONFIG_SYS_SDRAM_BASE	SCB9328_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR	(SCB9328_SDRAM_1 + 0xf00000)

/*
 * Configuration for FLASH memory for the Synertronixx board
 */

/* #define SCB9328_FLASH_32M */

/* 32MB */
#ifdef SCB9328_FLASH_32M
#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
#define CONFIG_SYS_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
#define SCB9328_FLASH_BANK_SIZE	 0x02000000	/* size of one flash bank	     */
#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
#else

/* 16MB */
#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
#define CONFIG_SYS_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
#define SCB9328_FLASH_BANK_SIZE	 0x01000000	/* size of one flash bank	     */
#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
#endif /* SCB9328_FLASH_32M */

/* This should be defined if CFI FLASH device is present. Actually benefit
   is not so clear to me. In other words we can provide more informations
   to user, but this expects more complex flash handling we do not provide
   now.*/
#undef	CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Write operation */

#define CONFIG_SYS_FLASH_BASE		SCB9328_FLASH_BASE

/*
 * This is setting for JFFS2 support in u-boot.
 * Right now there is no gain for user, but later on booting kernel might be
 * possible. Consider using XIP kernel running from flash to save RAM
 * footprint.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#define CONFIG_SYS_JFFS2_FIRST_BANK		0
#define CONFIG_SYS_JFFS2_FIRST_SECTOR		5
#define CONFIG_SYS_JFFS2_NUM_BANKS		1

/*
 * Environment setup. Definitions of monitor location and size with
 * definition of environment setup ends up in 2 possibilities.
 * 1. Embeded environment - in u-boot code is space for environment
 * 2. Environment is read from predefined sector of flash
 * Right now we support 2. possiblity, but expecting no env placed
 * on mentioned address right now. This also needs to provide whole
 * sector for it - for us 256Kb is really waste of memory. U-boot uses
 * default env. and until kernel parameters could be sent to kernel
 * env. has no sense to us.
 */

/* Setup for PA23 which is Reset Default PA23 but has to become
   CS5 */

#define CONFIG_SYS_GPR_A_VAL		0x00800000
#define CONFIG_SYS_GIUS_A_VAL		0x0043fffe

#define CONFIG_SYS_MONITOR_BASE	0x10000000
#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0x10020000	/* absolute address for now  */
#define CONFIG_ENV_SIZE		0x20000

#define	 CONFIG_ENV_OVERWRITE  1		/* env is not writable now   */

/*
 * CSxU_VAL:
 * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
 *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
 *
 * CSxL_VAL:
 * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
 *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
 */

#define CONFIG_SYS_CS0U_VAL 0x000F2000
#define CONFIG_SYS_CS0L_VAL 0x11110d01
#define CONFIG_SYS_CS1U_VAL 0x000F0a00
#define CONFIG_SYS_CS1L_VAL 0x11110601
#define CONFIG_SYS_CS2U_VAL 0x0
#define CONFIG_SYS_CS2L_VAL 0x0

#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
#define CONFIG_SYS_CS3L_VAL 0x00000303

#define CONFIG_SYS_CS4U_VAL 0x000F0a00
#define CONFIG_SYS_CS4L_VAL 0x11110301

/* CNC == 3 too long
   #define CONFIG_SYS_CS5U_VAL 0x0000C210 */

/* #define CONFIG_SYS_CS5U_VAL 0x00008400
   mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
   kaum langsamer ist */
/* #define CONFIG_SYS_CS5U_VAL 0x00009400
   #define CONFIG_SYS_CS5L_VAL 0x11010D03 */

#define CONFIG_SYS_CS5U_VAL 0x00008400
#define CONFIG_SYS_CS5L_VAL 0x00000D03

#define CONFIG_DRIVER_DM9000		1
#define CONFIG_DM9000_BASE		0x16000000
#define DM9000_IO			CONFIG_DM9000_BASE
#define DM9000_DATA			(CONFIG_DM9000_BASE+4)

/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
   f_ref=16,777MHz

   0x002a141f: 191,9944MHz
   0x040b2007: 144MHz
   0x042a141f: 96MHz
   0x0811140d: 64MHz
   0x040e200e: 150MHz
   0x00321431: 200MHz

   0x08001800: 64MHz mit 16er Quarz
   0x04001800: 96MHz mit 16er Quarz
   0x04002400: 144MHz mit 16er Quarz

   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */

#define CPU200

#ifdef CPU200
#define CONFIG_SYS_MPCTL0_VAL 0x00321431
#else
#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
#endif

/* #define BUS64 */
#define BUS72

#ifdef BUS72
#define CONFIG_SYS_SPCTL0_VAL 0x04002400
#endif

#ifdef BUS96
#define CONFIG_SYS_SPCTL0_VAL 0x04001800
#endif

#ifdef BUS64
#define CONFIG_SYS_SPCTL0_VAL 0x08001800
#endif

/* Das ist der BCLK Divider, der aus der System PLL
   BCLK und HCLK erzeugt:
   31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
   0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
   0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
   0x2f001003 : 192MHz/5=38,4MHz
   0x2f000003 : 64MHz/1
   Bit 22: SPLL Restart
   Bit 21: MPLL Restart */

#ifdef BUS64
#define CONFIG_SYS_CSCR_VAL 0x2f030003
#endif

#ifdef BUS72
#define CONFIG_SYS_CSCR_VAL 0x2f030403
#endif

/*
 * Well this has to be defined, but on the other hand it is used differently
 * one may expect. For instance loadb command do not cares :-)
 * So advice is - do not relay on this...
 */
#define CONFIG_SYS_LOAD_ADDR 0x08400000

#define MHZ16QUARZINUSE

#ifdef MHZ16QUARZINUSE
#define CONFIG_SYSPLL_CLK_FREQ 16000000
#else
#define CONFIG_SYSPLL_CLK_FREQ 16780000
#endif

#define CONFIG_SYS_CLK_FREQ 16780000

/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
#define CONFIG_SYS_FMCR_VAL 0x00000001

/* Bit[0:3] contain PERCLK1DIV for UART 1
   0x000b00b ->b<- -> 192MHz/12=16MHz
   0x000b00b ->8<- -> 144MHz/09=16MHz
   0x000b00b ->3<- -> 64MHz/4=16MHz */

#ifdef BUS96
#define CONFIG_SYS_PCDR_VAL 0x000b00b5
#endif

#ifdef BUS64
#define CONFIG_SYS_PCDR_VAL 0x000b00b3
#endif

#ifdef BUS72
#define CONFIG_SYS_PCDR_VAL 0x000b00b8
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
281e00a3 WD	1	/*
	2	* Copyright (C) 2003 ETC s.r.o.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*
	19	* Written by Peter Figuli <peposh@etc.sk>, 2003.
	20	*
	21	* 2003/13/06 Initial MP10 Support copied from wepep250
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
	28	#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
	29	#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
	30	#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
	31
d3e55d07	32	#define CONFIG_IMX_SERIAL
281e00a3 WD	33	#define CONFIG_IMX_SERIAL1
	34	/*
	35	* Select serial console configuration
	36	*/
	37
079a136c JL	38	/*
	39	* BOOTP options
	40	*/
	41	#define CONFIG_BOOTP_BOOTFILESIZE
	42	#define CONFIG_BOOTP_BOOTPATH
	43	#define CONFIG_BOOTP_GATEWAY
	44	#define CONFIG_BOOTP_HOSTNAME
	45
281e00a3	46	/*
46da1e96	47	* Command line configuration.
281e00a3	48	*/
46da1e96 JL	49	#include <config_cmd_default.h>
	50
	51	#define CONFIG_CMD_NET
	52	#define CONFIG_CMD_PING
	53	#define CONFIG_CMD_DHCP
	54
46da1e96	55	#undef CONFIG_CMD_CONSOLE
74de7aef WD	56	#undef CONFIG_CMD_LOADS
74de7aef WD	57	#undef CONFIG_CMD_SOURCE
46da1e96	58
281e00a3 WD	59	/*
	60	* Boot options. Setting delay to -1 stops autostart count down.
	61	* NOTE: Sending parameters to kernel depends on kernel version and
	62	* 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
	63	* parameters at all! Do not get confused by them so.
	64	*/
	65	#define CONFIG_BOOTDELAY -1
	66	#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
	67	#define CONFIG_BOOTCOMMAND "bootm 10040000"
	68	#define CONFIG_SHOW_BOOT_PROGRESS
	69	#define CONFIG_ETHADDR 80:81:82:83:84:85
	70	#define CONFIG_NETMASK 255.255.255.0
	71	#define CONFIG_IPADDR 10.10.10.9
	72	#define CONFIG_SERVERIP 10.10.10.10
	73
	74	/*
	75	* General options for u-boot. Modify to save memory foot print
	76	*/
6d0f6bcf JCPV	77	#define CONFIG_SYS_LONGHELP /* undef saves memory */
	78	#define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */
	79	#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
	80	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
	81	#define CONFIG_SYS_MAXARGS 16 /* max command args */
	82	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
281e00a3	83
6d0f6bcf JCPV	84	#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
6d0f6bcf JCPV	85	#define CONFIG_SYS_MEMTEST_END 0x08F00000
281e00a3	86
6d0f6bcf JCPV	87	#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
6d0f6bcf JCPV	88	#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
281e00a3	89
6d0f6bcf	90	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
281e00a3 WD	91	#define CONFIG_BAUDRATE 115200
	92	/*
	93	* Definitions related to passing arguments to kernel.
	94	*/
	95	#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
	96	#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
	97	#define CONFIG_INITRD_TAG 1 /* send initrd params */
281e00a3	98
281e00a3 WD	99	/*
	100	* Malloc pool need to host env + 128 Kb reserve for other allocations.
	101	*/
6d0f6bcf	102	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
281e00a3	103
281e00a3 WD	104	#define CONFIG_STACKSIZE (120<<10) /* stack size */
	105
	106	#ifdef CONFIG_USE_IRQ
	107	#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
	108	#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
	109	#endif
	110
	111	/* SDRAM Setup Values
	112	0x910a8300 Precharge Command CAS 3
	113	0x910a8200 Precharge Command CAS 2
	114
	115	0xa10a8300 AutoRefresh Command CAS 3
	116	0xa10a8200 Set AutoRefresh Command CAS 2 */
	117
	118	#define PRECHARGE_CMD 0x910a8200
	119	#define AUTOREFRESH_CMD 0xa10a8200
281e00a3 WD	120
	121	/*
	122	* SDRAM Memory Map
	123	*/
	124	/* SH FIXME */
	125	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
	126	#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
	127	#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
	128
386393c6 TK	129	#define CONFIG_SYS_TEXT_BASE 0x10000000
	130
	131	#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
	132	#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
	133
281e00a3 WD	134	/*
	135	* Configuration for FLASH memory for the Synertronixx board
	136	*/
	137
	138	/* #define SCB9328_FLASH_32M */
	139
	140	/* 32MB */
	141	#ifdef SCB9328_FLASH_32M
6d0f6bcf JCPV	142	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
6d0f6bcf JCPV	143	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
281e00a3 WD	144	#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
	145	#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
	146	#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
	147	#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
	148	#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
	149	#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
	150	#else
	151
	152	/* 16MB */
6d0f6bcf JCPV	153	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
281e00a3 WD	155	#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
	156	#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
	157	#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
	158	#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
	159	#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
	160	#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
	161	#endif /* SCB9328_FLASH_32M */
	162
	163	/* This should be defined if CFI FLASH device is present. Actually benefit
	164	is not so clear to me. In other words we can provide more informations
	165	to user, but this expects more complex flash handling we do not provide
	166	now.*/
6d0f6bcf	167	#undef CONFIG_SYS_FLASH_CFI
281e00a3	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_FLASH_ERASE_TOUT (2CONFIG_SYS_HZ) / timeout for Erase operation */
6d0f6bcf JCPV	170	#define CONFIG_SYS_FLASH_WRITE_TOUT (2CONFIG_SYS_HZ) / timeout for Write operation */
281e00a3	171
6d0f6bcf	172	#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
281e00a3 WD	173
	174	/*
	175	* This is setting for JFFS2 support in u-boot.
	176	* Right now there is no gain for user, but later on booting kernel might be
	177	* possible. Consider using XIP kernel running from flash to save RAM
	178	* footprint.
079a136c	179	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
281e00a3	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	182	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
	183	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
281e00a3 WD	184
	185	/*
	186	* Environment setup. Definitions of monitor location and size with
	187	* definition of environment setup ends up in 2 possibilities.
	188	* 1. Embeded environment - in u-boot code is space for environment
	189	* 2. Environment is read from predefined sector of flash
	190	* Right now we support 2. possiblity, but expecting no env placed
	191	* on mentioned address right now. This also needs to provide whole
	192	* sector for it - for us 256Kb is really waste of memory. U-boot uses
	193	* default env. and until kernel parameters could be sent to kernel
	194	* env. has no sense to us.
	195	*/
	196
	197	/* Setup for PA23 which is Reset Default PA23 but has to become
	198	CS5 */
	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_GPR_A_VAL 0x00800000
6d0f6bcf JCPV	201	#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
281e00a3	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_MONITOR_BASE 0x10000000
6d0f6bcf JCPV	204	#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
5a1aceb0	205	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	206	#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
0e8d1586 JCPV	207	#define CONFIG_ENV_SIZE 0x20000
281e00a3 WD	208
	209	#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
	210
	211	/*
	212	* CSxU_VAL:
	213	* 63\| x x x x \| x x x x \| x x x x \| x x x x \| x x x x \| x x x x \| x x x x \| x x x x\|32
	214	* \|DTACK_SEL\|0\|BCD \| BCS \| PSZ\|PME\|SYNC\| DOL \| CNC\| WSC \| 0\| WWS \| EDC \|
	215	*
	216	* CSxL_VAL:
	217	* 31\| x x x x \| x x x x \| x x x x \| x x x x \| x x x x \| x x x x \| x x x x \| x x x x\| 0
	218	* \| OEA \| OEN \| WEA \| WEN \| CSA \|EBC\| DSZ \| 0\|SP\|0\|WP\| 0 0\|PA\|CSEN\|
	219	*/
	220
6d0f6bcf JCPV	221	#define CONFIG_SYS_CS0U_VAL 0x000F2000
	222	#define CONFIG_SYS_CS0L_VAL 0x11110d01
	223	#define CONFIG_SYS_CS1U_VAL 0x000F0a00
	224	#define CONFIG_SYS_CS1L_VAL 0x11110601
	225	#define CONFIG_SYS_CS2U_VAL 0x0
	226	#define CONFIG_SYS_CS2L_VAL 0x0
281e00a3	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
6d0f6bcf JCPV	229	#define CONFIG_SYS_CS3L_VAL 0x00000303
281e00a3	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_CS4U_VAL 0x000F0a00
6d0f6bcf JCPV	232	#define CONFIG_SYS_CS4L_VAL 0x11110301
281e00a3 WD	233
281e00a3 WD	234	/* CNC == 3 too long
6d0f6bcf	235	#define CONFIG_SYS_CS5U_VAL 0x0000C210 */
281e00a3	236
6d0f6bcf	237	/* #define CONFIG_SYS_CS5U_VAL 0x00008400
281e00a3 WD	238	mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
281e00a3 WD	239	kaum langsamer ist */
6d0f6bcf JCPV	240	/* #define CONFIG_SYS_CS5U_VAL 0x00009400
6d0f6bcf JCPV	241	#define CONFIG_SYS_CS5L_VAL 0x11010D03 */
281e00a3	242
6d0f6bcf JCPV	243	#define CONFIG_SYS_CS5U_VAL 0x00008400
6d0f6bcf JCPV	244	#define CONFIG_SYS_CS5L_VAL 0x00000D03
281e00a3	245
281e00a3 WD	246	#define CONFIG_DRIVER_DM9000 1
	247	#define CONFIG_DM9000_BASE 0x16000000
	248	#define DM9000_IO CONFIG_DM9000_BASE
	249	#define DM9000_DATA (CONFIG_DM9000_BASE+4)
281e00a3 WD	250
	251	/* f_{dpll}=2f{ref}(MFI+MFN/(MFD+1))/(PD+1)
	252	f_ref=16,777MHz
	253
	254	0x002a141f: 191,9944MHz
	255	0x040b2007: 144MHz
	256	0x042a141f: 96MHz
	257	0x0811140d: 64MHz
	258	0x040e200e: 150MHz
	259	0x00321431: 200MHz
	260
	261	0x08001800: 64MHz mit 16er Quarz
	262	0x04001800: 96MHz mit 16er Quarz
	263	0x04002400: 144MHz mit 16er Quarz
	264
	265	31 \|x x x x\|x x x x\|x x x x\|x x x x\|x x x x\|x x x x\|x x x x\|x x x x\| 0
	266	\|XXX\|--PD---\|-------MFD---------\|XXX\|--MFI--\|-----MFN-----------\| */
	267
	268	#define CPU200
	269
	270	#ifdef CPU200
6d0f6bcf	271	#define CONFIG_SYS_MPCTL0_VAL 0x00321431
281e00a3	272	#else
6d0f6bcf	273	#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
281e00a3 WD	274	#endif
	275
	276	/* #define BUS64 */
	277	#define BUS72
	278
	279	#ifdef BUS72
6d0f6bcf	280	#define CONFIG_SYS_SPCTL0_VAL 0x04002400
281e00a3 WD	281	#endif
	282
	283	#ifdef BUS96
6d0f6bcf	284	#define CONFIG_SYS_SPCTL0_VAL 0x04001800
281e00a3 WD	285	#endif
	286
	287	#ifdef BUS64
6d0f6bcf	288	#define CONFIG_SYS_SPCTL0_VAL 0x08001800
281e00a3 WD	289	#endif
	290
	291	/* Das ist der BCLK Divider, der aus der System PLL
	292	BCLK und HCLK erzeugt:
	293	31 \| xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx \| 0
	294	0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
	295	0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
	296	0x2f001003 : 192MHz/5=38,4MHz
	297	0x2f000003 : 64MHz/1
	298	Bit 22: SPLL Restart
	299	Bit 21: MPLL Restart */
	300
	301	#ifdef BUS64
6d0f6bcf	302	#define CONFIG_SYS_CSCR_VAL 0x2f030003
281e00a3 WD	303	#endif
	304
	305	#ifdef BUS72
6d0f6bcf	306	#define CONFIG_SYS_CSCR_VAL 0x2f030403
281e00a3 WD	307	#endif
	308
	309	/*
	310	* Well this has to be defined, but on the other hand it is used differently
	311	* one may expect. For instance loadb command do not cares :-)
	312	* So advice is - do not relay on this...
	313	*/
6d0f6bcf	314	#define CONFIG_SYS_LOAD_ADDR 0x08400000
281e00a3 WD	315
	316	#define MHZ16QUARZINUSE
	317
	318	#ifdef MHZ16QUARZINUSE
	319	#define CONFIG_SYSPLL_CLK_FREQ 16000000
	320	#else
	321	#define CONFIG_SYSPLL_CLK_FREQ 16780000
	322	#endif
	323
	324	#define CONFIG_SYS_CLK_FREQ 16780000
	325
	326	/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
6d0f6bcf	327	#define CONFIG_SYS_FMCR_VAL 0x00000001
281e00a3 WD	328
	329	/* Bit[0:3] contain PERCLK1DIV for UART 1
	330	0x000b00b ->b<- -> 192MHz/12=16MHz
	331	0x000b00b ->8<- -> 144MHz/09=16MHz
	332	0x000b00b ->3<- -> 64MHz/4=16MHz */
	333
	334	#ifdef BUS96
6d0f6bcf	335	#define CONFIG_SYS_PCDR_VAL 0x000b00b5
281e00a3 WD	336	#endif
	337
	338	#ifdef BUS64
6d0f6bcf	339	#define CONFIG_SYS_PCDR_VAL 0x000b00b3
281e00a3 WD	340	#endif
	341
	342	#ifdef BUS72
6d0f6bcf	343	#define CONFIG_SYS_PCDR_VAL 0x000b00b8
281e00a3 WD	344	#endif
	345
	346	#endif /* __CONFIG_H */