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281e00a3 WD |
1 | /* |
2 | * Copyright (C) 2003 ETC s.r.o. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | * | |
19 | * Written by Peter Figuli <peposh@etc.sk>, 2003. | |
20 | * | |
21 | * 2003/13/06 Initial MP10 Support copied from wepep250 | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ | |
28 | #define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ | |
29 | #define CONFIG_SCB9328 1 /* on a scb9328tronix board */ | |
30 | #undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ | |
31 | ||
d3e55d07 | 32 | #define CONFIG_IMX_SERIAL |
281e00a3 WD |
33 | #define CONFIG_IMX_SERIAL1 |
34 | /* | |
35 | * Select serial console configuration | |
36 | */ | |
37 | ||
38 | ||
079a136c JL |
39 | /* |
40 | * BOOTP options | |
41 | */ | |
42 | #define CONFIG_BOOTP_BOOTFILESIZE | |
43 | #define CONFIG_BOOTP_BOOTPATH | |
44 | #define CONFIG_BOOTP_GATEWAY | |
45 | #define CONFIG_BOOTP_HOSTNAME | |
46 | ||
47 | ||
281e00a3 | 48 | /* |
46da1e96 | 49 | * Command line configuration. |
281e00a3 | 50 | */ |
46da1e96 JL |
51 | #include <config_cmd_default.h> |
52 | ||
53 | #define CONFIG_CMD_NET | |
54 | #define CONFIG_CMD_PING | |
55 | #define CONFIG_CMD_DHCP | |
56 | ||
46da1e96 | 57 | #undef CONFIG_CMD_CONSOLE |
74de7aef WD |
58 | #undef CONFIG_CMD_LOADS |
59 | #undef CONFIG_CMD_SOURCE | |
46da1e96 | 60 | |
281e00a3 WD |
61 | |
62 | /* | |
63 | * Boot options. Setting delay to -1 stops autostart count down. | |
64 | * NOTE: Sending parameters to kernel depends on kernel version and | |
65 | * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept | |
66 | * parameters at all! Do not get confused by them so. | |
67 | */ | |
68 | #define CONFIG_BOOTDELAY -1 | |
69 | #define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" | |
70 | #define CONFIG_BOOTCOMMAND "bootm 10040000" | |
71 | #define CONFIG_SHOW_BOOT_PROGRESS | |
72 | #define CONFIG_ETHADDR 80:81:82:83:84:85 | |
73 | #define CONFIG_NETMASK 255.255.255.0 | |
74 | #define CONFIG_IPADDR 10.10.10.9 | |
75 | #define CONFIG_SERVERIP 10.10.10.10 | |
76 | ||
77 | /* | |
78 | * General options for u-boot. Modify to save memory foot print | |
79 | */ | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_LONGHELP /* undef saves memory */ |
81 | #define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */ | |
82 | #define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ | |
83 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ | |
84 | #define CONFIG_SYS_MAXARGS 16 /* max command args */ | |
85 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ | |
281e00a3 | 86 | |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ |
88 | #define CONFIG_SYS_MEMTEST_END 0x08F00000 | |
281e00a3 | 89 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
91 | #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ | |
281e00a3 | 92 | |
6d0f6bcf | 93 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
281e00a3 WD |
94 | #define CONFIG_BAUDRATE 115200 |
95 | /* | |
96 | * Definitions related to passing arguments to kernel. | |
97 | */ | |
98 | #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ | |
99 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ | |
100 | #define CONFIG_INITRD_TAG 1 /* send initrd params */ | |
101 | #undef CONFIG_VFD /* do not send framebuffer setup */ | |
102 | ||
103 | ||
104 | /* | |
105 | * Malloc pool need to host env + 128 Kb reserve for other allocations. | |
106 | */ | |
6d0f6bcf | 107 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) |
281e00a3 WD |
108 | |
109 | ||
6d0f6bcf | 110 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
281e00a3 WD |
111 | |
112 | #define CONFIG_STACKSIZE (120<<10) /* stack size */ | |
113 | ||
114 | #ifdef CONFIG_USE_IRQ | |
115 | #define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ | |
116 | #define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ | |
117 | #endif | |
118 | ||
119 | /* SDRAM Setup Values | |
120 | 0x910a8300 Precharge Command CAS 3 | |
121 | 0x910a8200 Precharge Command CAS 2 | |
122 | ||
123 | 0xa10a8300 AutoRefresh Command CAS 3 | |
124 | 0xa10a8200 Set AutoRefresh Command CAS 2 */ | |
125 | ||
126 | #define PRECHARGE_CMD 0x910a8200 | |
127 | #define AUTOREFRESH_CMD 0xa10a8200 | |
281e00a3 WD |
128 | |
129 | /* | |
130 | * SDRAM Memory Map | |
131 | */ | |
132 | /* SH FIXME */ | |
133 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ | |
134 | #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ | |
135 | #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ | |
136 | ||
137 | /* | |
138 | * Flash Controller settings | |
139 | */ | |
140 | ||
141 | /* | |
142 | * Hardware drivers | |
143 | */ | |
144 | ||
145 | ||
146 | /* | |
147 | * Configuration for FLASH memory for the Synertronixx board | |
148 | */ | |
149 | ||
150 | /* #define SCB9328_FLASH_32M */ | |
151 | ||
152 | /* 32MB */ | |
153 | #ifdef SCB9328_FLASH_32M | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
155 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ | |
281e00a3 WD |
156 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ |
157 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
158 | #define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ | |
159 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
160 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
161 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
162 | #else | |
163 | ||
164 | /* 16MB */ | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
166 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ | |
281e00a3 WD |
167 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ |
168 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
169 | #define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ | |
170 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
171 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
172 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
173 | #endif /* SCB9328_FLASH_32M */ | |
174 | ||
175 | /* This should be defined if CFI FLASH device is present. Actually benefit | |
176 | is not so clear to me. In other words we can provide more informations | |
177 | to user, but this expects more complex flash handling we do not provide | |
178 | now.*/ | |
6d0f6bcf | 179 | #undef CONFIG_SYS_FLASH_CFI |
281e00a3 | 180 | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ |
182 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ | |
281e00a3 | 183 | |
6d0f6bcf | 184 | #define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE |
281e00a3 WD |
185 | |
186 | /* | |
187 | * This is setting for JFFS2 support in u-boot. | |
188 | * Right now there is no gain for user, but later on booting kernel might be | |
189 | * possible. Consider using XIP kernel running from flash to save RAM | |
190 | * footprint. | |
079a136c | 191 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. |
281e00a3 | 192 | */ |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
194 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 5 | |
195 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
281e00a3 WD |
196 | |
197 | /* | |
198 | * Environment setup. Definitions of monitor location and size with | |
199 | * definition of environment setup ends up in 2 possibilities. | |
200 | * 1. Embeded environment - in u-boot code is space for environment | |
201 | * 2. Environment is read from predefined sector of flash | |
202 | * Right now we support 2. possiblity, but expecting no env placed | |
203 | * on mentioned address right now. This also needs to provide whole | |
204 | * sector for it - for us 256Kb is really waste of memory. U-boot uses | |
205 | * default env. and until kernel parameters could be sent to kernel | |
206 | * env. has no sense to us. | |
207 | */ | |
208 | ||
209 | /* Setup for PA23 which is Reset Default PA23 but has to become | |
210 | CS5 */ | |
211 | ||
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_GPR_A_VAL 0x00800000 |
213 | #define CONFIG_SYS_GIUS_A_VAL 0x0043fffe | |
281e00a3 | 214 | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_MONITOR_BASE 0x10000000 |
216 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ | |
5a1aceb0 | 217 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
218 | #define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ |
219 | #define CONFIG_ENV_SIZE 0x20000 | |
281e00a3 WD |
220 | |
221 | #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ | |
222 | ||
223 | /* | |
224 | * CSxU_VAL: | |
225 | * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 | |
226 | * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | | |
227 | * | |
228 | * CSxL_VAL: | |
229 | * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 | |
230 | * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| | |
231 | */ | |
232 | ||
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_CS0U_VAL 0x000F2000 |
234 | #define CONFIG_SYS_CS0L_VAL 0x11110d01 | |
235 | #define CONFIG_SYS_CS1U_VAL 0x000F0a00 | |
236 | #define CONFIG_SYS_CS1L_VAL 0x11110601 | |
237 | #define CONFIG_SYS_CS2U_VAL 0x0 | |
238 | #define CONFIG_SYS_CS2L_VAL 0x0 | |
281e00a3 | 239 | |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_CS3U_VAL 0x000FFFFF |
241 | #define CONFIG_SYS_CS3L_VAL 0x00000303 | |
281e00a3 | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_CS4U_VAL 0x000F0a00 |
244 | #define CONFIG_SYS_CS4L_VAL 0x11110301 | |
281e00a3 WD |
245 | |
246 | /* CNC == 3 too long | |
6d0f6bcf | 247 | #define CONFIG_SYS_CS5U_VAL 0x0000C210 */ |
281e00a3 | 248 | |
6d0f6bcf | 249 | /* #define CONFIG_SYS_CS5U_VAL 0x00008400 |
281e00a3 WD |
250 | mal laenger mahcen, ob der bei 150MHz laenger haelt dann und |
251 | kaum langsamer ist */ | |
6d0f6bcf JCPV |
252 | /* #define CONFIG_SYS_CS5U_VAL 0x00009400 |
253 | #define CONFIG_SYS_CS5L_VAL 0x11010D03 */ | |
281e00a3 | 254 | |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_CS5U_VAL 0x00008400 |
256 | #define CONFIG_SYS_CS5L_VAL 0x00000D03 | |
281e00a3 | 257 | |
60f61e6d | 258 | #define CONFIG_NET_MULTI 1 |
281e00a3 WD |
259 | #define CONFIG_DRIVER_DM9000 1 |
260 | #define CONFIG_DM9000_BASE 0x16000000 | |
261 | #define DM9000_IO CONFIG_DM9000_BASE | |
262 | #define DM9000_DATA (CONFIG_DM9000_BASE+4) | |
281e00a3 WD |
263 | |
264 | /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) | |
265 | f_ref=16,777MHz | |
266 | ||
267 | 0x002a141f: 191,9944MHz | |
268 | 0x040b2007: 144MHz | |
269 | 0x042a141f: 96MHz | |
270 | 0x0811140d: 64MHz | |
271 | 0x040e200e: 150MHz | |
272 | 0x00321431: 200MHz | |
273 | ||
274 | 0x08001800: 64MHz mit 16er Quarz | |
275 | 0x04001800: 96MHz mit 16er Quarz | |
276 | 0x04002400: 144MHz mit 16er Quarz | |
277 | ||
278 | 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 | |
279 | |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ | |
280 | ||
281 | #define CPU200 | |
282 | ||
283 | #ifdef CPU200 | |
6d0f6bcf | 284 | #define CONFIG_SYS_MPCTL0_VAL 0x00321431 |
281e00a3 | 285 | #else |
6d0f6bcf | 286 | #define CONFIG_SYS_MPCTL0_VAL 0x040e200e |
281e00a3 WD |
287 | #endif |
288 | ||
289 | /* #define BUS64 */ | |
290 | #define BUS72 | |
291 | ||
292 | #ifdef BUS72 | |
6d0f6bcf | 293 | #define CONFIG_SYS_SPCTL0_VAL 0x04002400 |
281e00a3 WD |
294 | #endif |
295 | ||
296 | #ifdef BUS96 | |
6d0f6bcf | 297 | #define CONFIG_SYS_SPCTL0_VAL 0x04001800 |
281e00a3 WD |
298 | #endif |
299 | ||
300 | #ifdef BUS64 | |
6d0f6bcf | 301 | #define CONFIG_SYS_SPCTL0_VAL 0x08001800 |
281e00a3 WD |
302 | #endif |
303 | ||
304 | /* Das ist der BCLK Divider, der aus der System PLL | |
305 | BCLK und HCLK erzeugt: | |
306 | 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 | |
307 | 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 | |
308 | 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 | |
309 | 0x2f001003 : 192MHz/5=38,4MHz | |
310 | 0x2f000003 : 64MHz/1 | |
311 | Bit 22: SPLL Restart | |
312 | Bit 21: MPLL Restart */ | |
313 | ||
314 | #ifdef BUS64 | |
6d0f6bcf | 315 | #define CONFIG_SYS_CSCR_VAL 0x2f030003 |
281e00a3 WD |
316 | #endif |
317 | ||
318 | #ifdef BUS72 | |
6d0f6bcf | 319 | #define CONFIG_SYS_CSCR_VAL 0x2f030403 |
281e00a3 WD |
320 | #endif |
321 | ||
322 | /* | |
323 | * Well this has to be defined, but on the other hand it is used differently | |
324 | * one may expect. For instance loadb command do not cares :-) | |
325 | * So advice is - do not relay on this... | |
326 | */ | |
6d0f6bcf | 327 | #define CONFIG_SYS_LOAD_ADDR 0x08400000 |
281e00a3 WD |
328 | |
329 | #define MHZ16QUARZINUSE | |
330 | ||
331 | #ifdef MHZ16QUARZINUSE | |
332 | #define CONFIG_SYSPLL_CLK_FREQ 16000000 | |
333 | #else | |
334 | #define CONFIG_SYSPLL_CLK_FREQ 16780000 | |
335 | #endif | |
336 | ||
337 | #define CONFIG_SYS_CLK_FREQ 16780000 | |
338 | ||
339 | /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ | |
6d0f6bcf | 340 | #define CONFIG_SYS_FMCR_VAL 0x00000001 |
281e00a3 WD |
341 | |
342 | /* Bit[0:3] contain PERCLK1DIV for UART 1 | |
343 | 0x000b00b ->b<- -> 192MHz/12=16MHz | |
344 | 0x000b00b ->8<- -> 144MHz/09=16MHz | |
345 | 0x000b00b ->3<- -> 64MHz/4=16MHz */ | |
346 | ||
347 | #ifdef BUS96 | |
6d0f6bcf | 348 | #define CONFIG_SYS_PCDR_VAL 0x000b00b5 |
281e00a3 WD |
349 | #endif |
350 | ||
351 | #ifdef BUS64 | |
6d0f6bcf | 352 | #define CONFIG_SYS_PCDR_VAL 0x000b00b3 |
281e00a3 WD |
353 | #endif |
354 | ||
355 | #ifdef BUS72 | |
6d0f6bcf | 356 | #define CONFIG_SYS_PCDR_VAL 0x000b00b8 |
281e00a3 WD |
357 | #endif |
358 | ||
359 | #endif /* __CONFIG_H */ |