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281e00a3 WD |
1 | /* |
2 | * Copyright (C) 2003 ETC s.r.o. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
281e00a3 WD |
5 | * Written by Peter Figuli <peposh@etc.sk>, 2003. |
6 | * | |
7 | * 2003/13/06 Initial MP10 Support copied from wepep250 | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
f2168440 | 13 | #define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */ |
281e00a3 | 14 | #define CONFIG_SCB9328 1 /* on a scb9328tronix board */ |
281e00a3 | 15 | |
d3e55d07 | 16 | #define CONFIG_IMX_SERIAL |
281e00a3 WD |
17 | #define CONFIG_IMX_SERIAL1 |
18 | /* | |
19 | * Select serial console configuration | |
20 | */ | |
21 | ||
079a136c JL |
22 | /* |
23 | * BOOTP options | |
24 | */ | |
25 | #define CONFIG_BOOTP_BOOTFILESIZE | |
26 | #define CONFIG_BOOTP_BOOTPATH | |
27 | #define CONFIG_BOOTP_GATEWAY | |
28 | #define CONFIG_BOOTP_HOSTNAME | |
29 | ||
281e00a3 | 30 | /* |
46da1e96 | 31 | * Command line configuration. |
281e00a3 | 32 | */ |
46da1e96 JL |
33 | #define CONFIG_CMD_PING |
34 | #define CONFIG_CMD_DHCP | |
35 | ||
281e00a3 WD |
36 | /* |
37 | * Boot options. Setting delay to -1 stops autostart count down. | |
38 | * NOTE: Sending parameters to kernel depends on kernel version and | |
39 | * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept | |
40 | * parameters at all! Do not get confused by them so. | |
41 | */ | |
42 | #define CONFIG_BOOTDELAY -1 | |
43 | #define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" | |
44 | #define CONFIG_BOOTCOMMAND "bootm 10040000" | |
45 | #define CONFIG_SHOW_BOOT_PROGRESS | |
281e00a3 WD |
46 | #define CONFIG_NETMASK 255.255.255.0 |
47 | #define CONFIG_IPADDR 10.10.10.9 | |
48 | #define CONFIG_SERVERIP 10.10.10.10 | |
49 | ||
50 | /* | |
51 | * General options for u-boot. Modify to save memory foot print | |
52 | */ | |
6d0f6bcf | 53 | #define CONFIG_SYS_LONGHELP /* undef saves memory */ |
6d0f6bcf JCPV |
54 | #define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ |
55 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ | |
56 | #define CONFIG_SYS_MAXARGS 16 /* max command args */ | |
57 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ | |
281e00a3 | 58 | |
6d0f6bcf JCPV |
59 | #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ |
60 | #define CONFIG_SYS_MEMTEST_END 0x08F00000 | |
281e00a3 | 61 | |
6d0f6bcf | 62 | #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ |
281e00a3 | 63 | |
281e00a3 WD |
64 | #define CONFIG_BAUDRATE 115200 |
65 | /* | |
66 | * Definitions related to passing arguments to kernel. | |
67 | */ | |
68 | #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ | |
69 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ | |
70 | #define CONFIG_INITRD_TAG 1 /* send initrd params */ | |
281e00a3 | 71 | |
281e00a3 WD |
72 | /* |
73 | * Malloc pool need to host env + 128 Kb reserve for other allocations. | |
74 | */ | |
6d0f6bcf | 75 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) |
281e00a3 | 76 | |
281e00a3 WD |
77 | /* SDRAM Setup Values |
78 | 0x910a8300 Precharge Command CAS 3 | |
79 | 0x910a8200 Precharge Command CAS 2 | |
80 | ||
81 | 0xa10a8300 AutoRefresh Command CAS 3 | |
82 | 0xa10a8200 Set AutoRefresh Command CAS 2 */ | |
83 | ||
84 | #define PRECHARGE_CMD 0x910a8200 | |
85 | #define AUTOREFRESH_CMD 0xa10a8200 | |
281e00a3 WD |
86 | |
87 | /* | |
88 | * SDRAM Memory Map | |
89 | */ | |
90 | /* SH FIXME */ | |
91 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ | |
92 | #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ | |
93 | #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ | |
94 | ||
386393c6 TK |
95 | #define CONFIG_SYS_TEXT_BASE 0x10000000 |
96 | ||
97 | #define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1 | |
98 | #define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000) | |
99 | ||
281e00a3 WD |
100 | /* |
101 | * Configuration for FLASH memory for the Synertronixx board | |
102 | */ | |
103 | ||
104 | /* #define SCB9328_FLASH_32M */ | |
105 | ||
106 | /* 32MB */ | |
107 | #ifdef SCB9328_FLASH_32M | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
109 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ | |
281e00a3 WD |
110 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ |
111 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
112 | #define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ | |
113 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
114 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
115 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
116 | #else | |
117 | ||
118 | /* 16MB */ | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
120 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ | |
281e00a3 WD |
121 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ |
122 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
123 | #define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ | |
124 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
125 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
126 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
127 | #endif /* SCB9328_FLASH_32M */ | |
128 | ||
129 | /* This should be defined if CFI FLASH device is present. Actually benefit | |
130 | is not so clear to me. In other words we can provide more informations | |
131 | to user, but this expects more complex flash handling we do not provide | |
132 | now.*/ | |
6d0f6bcf | 133 | #undef CONFIG_SYS_FLASH_CFI |
281e00a3 | 134 | |
f90aea2a MV |
135 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */ |
136 | #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */ | |
281e00a3 | 137 | |
6d0f6bcf | 138 | #define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE |
281e00a3 WD |
139 | |
140 | /* | |
141 | * This is setting for JFFS2 support in u-boot. | |
142 | * Right now there is no gain for user, but later on booting kernel might be | |
143 | * possible. Consider using XIP kernel running from flash to save RAM | |
144 | * footprint. | |
079a136c | 145 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. |
281e00a3 | 146 | */ |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
148 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 5 | |
149 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
281e00a3 WD |
150 | |
151 | /* | |
152 | * Environment setup. Definitions of monitor location and size with | |
153 | * definition of environment setup ends up in 2 possibilities. | |
154 | * 1. Embeded environment - in u-boot code is space for environment | |
155 | * 2. Environment is read from predefined sector of flash | |
156 | * Right now we support 2. possiblity, but expecting no env placed | |
157 | * on mentioned address right now. This also needs to provide whole | |
158 | * sector for it - for us 256Kb is really waste of memory. U-boot uses | |
159 | * default env. and until kernel parameters could be sent to kernel | |
160 | * env. has no sense to us. | |
161 | */ | |
162 | ||
163 | /* Setup for PA23 which is Reset Default PA23 but has to become | |
164 | CS5 */ | |
165 | ||
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_GPR_A_VAL 0x00800000 |
167 | #define CONFIG_SYS_GIUS_A_VAL 0x0043fffe | |
281e00a3 | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_MONITOR_BASE 0x10000000 |
170 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ | |
5a1aceb0 | 171 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
172 | #define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ |
173 | #define CONFIG_ENV_SIZE 0x20000 | |
281e00a3 WD |
174 | |
175 | #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ | |
176 | ||
177 | /* | |
178 | * CSxU_VAL: | |
179 | * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 | |
180 | * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | | |
181 | * | |
182 | * CSxL_VAL: | |
183 | * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 | |
184 | * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| | |
185 | */ | |
186 | ||
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_CS0U_VAL 0x000F2000 |
188 | #define CONFIG_SYS_CS0L_VAL 0x11110d01 | |
189 | #define CONFIG_SYS_CS1U_VAL 0x000F0a00 | |
190 | #define CONFIG_SYS_CS1L_VAL 0x11110601 | |
191 | #define CONFIG_SYS_CS2U_VAL 0x0 | |
192 | #define CONFIG_SYS_CS2L_VAL 0x0 | |
281e00a3 | 193 | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_CS3U_VAL 0x000FFFFF |
195 | #define CONFIG_SYS_CS3L_VAL 0x00000303 | |
281e00a3 | 196 | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_CS4U_VAL 0x000F0a00 |
198 | #define CONFIG_SYS_CS4L_VAL 0x11110301 | |
281e00a3 WD |
199 | |
200 | /* CNC == 3 too long | |
6d0f6bcf | 201 | #define CONFIG_SYS_CS5U_VAL 0x0000C210 */ |
281e00a3 | 202 | |
6d0f6bcf | 203 | /* #define CONFIG_SYS_CS5U_VAL 0x00008400 |
281e00a3 WD |
204 | mal laenger mahcen, ob der bei 150MHz laenger haelt dann und |
205 | kaum langsamer ist */ | |
6d0f6bcf JCPV |
206 | /* #define CONFIG_SYS_CS5U_VAL 0x00009400 |
207 | #define CONFIG_SYS_CS5L_VAL 0x11010D03 */ | |
281e00a3 | 208 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_CS5U_VAL 0x00008400 |
210 | #define CONFIG_SYS_CS5L_VAL 0x00000D03 | |
281e00a3 | 211 | |
281e00a3 WD |
212 | #define CONFIG_DRIVER_DM9000 1 |
213 | #define CONFIG_DM9000_BASE 0x16000000 | |
214 | #define DM9000_IO CONFIG_DM9000_BASE | |
215 | #define DM9000_DATA (CONFIG_DM9000_BASE+4) | |
281e00a3 WD |
216 | |
217 | /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) | |
218 | f_ref=16,777MHz | |
219 | ||
220 | 0x002a141f: 191,9944MHz | |
221 | 0x040b2007: 144MHz | |
222 | 0x042a141f: 96MHz | |
223 | 0x0811140d: 64MHz | |
224 | 0x040e200e: 150MHz | |
225 | 0x00321431: 200MHz | |
226 | ||
227 | 0x08001800: 64MHz mit 16er Quarz | |
228 | 0x04001800: 96MHz mit 16er Quarz | |
229 | 0x04002400: 144MHz mit 16er Quarz | |
230 | ||
231 | 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 | |
232 | |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ | |
233 | ||
234 | #define CPU200 | |
235 | ||
236 | #ifdef CPU200 | |
6d0f6bcf | 237 | #define CONFIG_SYS_MPCTL0_VAL 0x00321431 |
281e00a3 | 238 | #else |
6d0f6bcf | 239 | #define CONFIG_SYS_MPCTL0_VAL 0x040e200e |
281e00a3 WD |
240 | #endif |
241 | ||
242 | /* #define BUS64 */ | |
243 | #define BUS72 | |
244 | ||
245 | #ifdef BUS72 | |
6d0f6bcf | 246 | #define CONFIG_SYS_SPCTL0_VAL 0x04002400 |
281e00a3 WD |
247 | #endif |
248 | ||
249 | #ifdef BUS96 | |
6d0f6bcf | 250 | #define CONFIG_SYS_SPCTL0_VAL 0x04001800 |
281e00a3 WD |
251 | #endif |
252 | ||
253 | #ifdef BUS64 | |
6d0f6bcf | 254 | #define CONFIG_SYS_SPCTL0_VAL 0x08001800 |
281e00a3 WD |
255 | #endif |
256 | ||
257 | /* Das ist der BCLK Divider, der aus der System PLL | |
258 | BCLK und HCLK erzeugt: | |
259 | 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 | |
260 | 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 | |
261 | 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 | |
262 | 0x2f001003 : 192MHz/5=38,4MHz | |
263 | 0x2f000003 : 64MHz/1 | |
264 | Bit 22: SPLL Restart | |
265 | Bit 21: MPLL Restart */ | |
266 | ||
267 | #ifdef BUS64 | |
6d0f6bcf | 268 | #define CONFIG_SYS_CSCR_VAL 0x2f030003 |
281e00a3 WD |
269 | #endif |
270 | ||
271 | #ifdef BUS72 | |
6d0f6bcf | 272 | #define CONFIG_SYS_CSCR_VAL 0x2f030403 |
281e00a3 WD |
273 | #endif |
274 | ||
275 | /* | |
276 | * Well this has to be defined, but on the other hand it is used differently | |
277 | * one may expect. For instance loadb command do not cares :-) | |
278 | * So advice is - do not relay on this... | |
279 | */ | |
6d0f6bcf | 280 | #define CONFIG_SYS_LOAD_ADDR 0x08400000 |
281e00a3 WD |
281 | |
282 | #define MHZ16QUARZINUSE | |
283 | ||
284 | #ifdef MHZ16QUARZINUSE | |
285 | #define CONFIG_SYSPLL_CLK_FREQ 16000000 | |
286 | #else | |
287 | #define CONFIG_SYSPLL_CLK_FREQ 16780000 | |
288 | #endif | |
289 | ||
290 | #define CONFIG_SYS_CLK_FREQ 16780000 | |
291 | ||
292 | /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ | |
6d0f6bcf | 293 | #define CONFIG_SYS_FMCR_VAL 0x00000001 |
281e00a3 WD |
294 | |
295 | /* Bit[0:3] contain PERCLK1DIV for UART 1 | |
296 | 0x000b00b ->b<- -> 192MHz/12=16MHz | |
297 | 0x000b00b ->8<- -> 144MHz/09=16MHz | |
298 | 0x000b00b ->3<- -> 64MHz/4=16MHz */ | |
299 | ||
300 | #ifdef BUS96 | |
6d0f6bcf | 301 | #define CONFIG_SYS_PCDR_VAL 0x000b00b5 |
281e00a3 WD |
302 | #endif |
303 | ||
304 | #ifdef BUS64 | |
6d0f6bcf | 305 | #define CONFIG_SYS_PCDR_VAL 0x000b00b3 |
281e00a3 WD |
306 | #endif |
307 | ||
308 | #ifdef BUS72 | |
6d0f6bcf | 309 | #define CONFIG_SYS_PCDR_VAL 0x000b00b8 |
281e00a3 WD |
310 | #endif |
311 | ||
312 | #endif /* __CONFIG_H */ |