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281e00a3 WD |
1 | /* |
2 | * Copyright (C) 2003 ETC s.r.o. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
281e00a3 WD |
5 | * Written by Peter Figuli <peposh@etc.sk>, 2003. |
6 | * | |
7 | * 2003/13/06 Initial MP10 Support copied from wepep250 | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
f2168440 | 13 | #define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */ |
281e00a3 | 14 | #define CONFIG_SCB9328 1 /* on a scb9328tronix board */ |
281e00a3 | 15 | |
d3e55d07 | 16 | #define CONFIG_IMX_SERIAL |
281e00a3 WD |
17 | #define CONFIG_IMX_SERIAL1 |
18 | /* | |
19 | * Select serial console configuration | |
20 | */ | |
21 | ||
079a136c JL |
22 | /* |
23 | * BOOTP options | |
24 | */ | |
25 | #define CONFIG_BOOTP_BOOTFILESIZE | |
26 | #define CONFIG_BOOTP_BOOTPATH | |
27 | #define CONFIG_BOOTP_GATEWAY | |
28 | #define CONFIG_BOOTP_HOSTNAME | |
29 | ||
281e00a3 | 30 | /* |
46da1e96 | 31 | * Command line configuration. |
281e00a3 | 32 | */ |
46da1e96 JL |
33 | #include <config_cmd_default.h> |
34 | ||
35 | #define CONFIG_CMD_NET | |
36 | #define CONFIG_CMD_PING | |
37 | #define CONFIG_CMD_DHCP | |
38 | ||
46da1e96 | 39 | #undef CONFIG_CMD_CONSOLE |
74de7aef WD |
40 | #undef CONFIG_CMD_LOADS |
41 | #undef CONFIG_CMD_SOURCE | |
46da1e96 | 42 | |
281e00a3 WD |
43 | /* |
44 | * Boot options. Setting delay to -1 stops autostart count down. | |
45 | * NOTE: Sending parameters to kernel depends on kernel version and | |
46 | * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept | |
47 | * parameters at all! Do not get confused by them so. | |
48 | */ | |
49 | #define CONFIG_BOOTDELAY -1 | |
50 | #define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" | |
51 | #define CONFIG_BOOTCOMMAND "bootm 10040000" | |
52 | #define CONFIG_SHOW_BOOT_PROGRESS | |
53 | #define CONFIG_ETHADDR 80:81:82:83:84:85 | |
54 | #define CONFIG_NETMASK 255.255.255.0 | |
55 | #define CONFIG_IPADDR 10.10.10.9 | |
56 | #define CONFIG_SERVERIP 10.10.10.10 | |
57 | ||
58 | /* | |
59 | * General options for u-boot. Modify to save memory foot print | |
60 | */ | |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_LONGHELP /* undef saves memory */ |
62 | #define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */ | |
63 | #define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ | |
64 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ | |
65 | #define CONFIG_SYS_MAXARGS 16 /* max command args */ | |
66 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ | |
281e00a3 | 67 | |
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ |
69 | #define CONFIG_SYS_MEMTEST_END 0x08F00000 | |
281e00a3 | 70 | |
6d0f6bcf | 71 | #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ |
281e00a3 | 72 | |
281e00a3 WD |
73 | #define CONFIG_BAUDRATE 115200 |
74 | /* | |
75 | * Definitions related to passing arguments to kernel. | |
76 | */ | |
77 | #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ | |
78 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ | |
79 | #define CONFIG_INITRD_TAG 1 /* send initrd params */ | |
281e00a3 | 80 | |
281e00a3 WD |
81 | /* |
82 | * Malloc pool need to host env + 128 Kb reserve for other allocations. | |
83 | */ | |
6d0f6bcf | 84 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) |
281e00a3 | 85 | |
281e00a3 WD |
86 | /* SDRAM Setup Values |
87 | 0x910a8300 Precharge Command CAS 3 | |
88 | 0x910a8200 Precharge Command CAS 2 | |
89 | ||
90 | 0xa10a8300 AutoRefresh Command CAS 3 | |
91 | 0xa10a8200 Set AutoRefresh Command CAS 2 */ | |
92 | ||
93 | #define PRECHARGE_CMD 0x910a8200 | |
94 | #define AUTOREFRESH_CMD 0xa10a8200 | |
281e00a3 WD |
95 | |
96 | /* | |
97 | * SDRAM Memory Map | |
98 | */ | |
99 | /* SH FIXME */ | |
100 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ | |
101 | #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ | |
102 | #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ | |
103 | ||
386393c6 TK |
104 | #define CONFIG_SYS_TEXT_BASE 0x10000000 |
105 | ||
106 | #define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1 | |
107 | #define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000) | |
108 | ||
281e00a3 WD |
109 | /* |
110 | * Configuration for FLASH memory for the Synertronixx board | |
111 | */ | |
112 | ||
113 | /* #define SCB9328_FLASH_32M */ | |
114 | ||
115 | /* 32MB */ | |
116 | #ifdef SCB9328_FLASH_32M | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
118 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ | |
281e00a3 WD |
119 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ |
120 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
121 | #define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ | |
122 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
123 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
124 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
125 | #else | |
126 | ||
127 | /* 16MB */ | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
129 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ | |
281e00a3 WD |
130 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ |
131 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
132 | #define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ | |
133 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
134 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
135 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
136 | #endif /* SCB9328_FLASH_32M */ | |
137 | ||
138 | /* This should be defined if CFI FLASH device is present. Actually benefit | |
139 | is not so clear to me. In other words we can provide more informations | |
140 | to user, but this expects more complex flash handling we do not provide | |
141 | now.*/ | |
6d0f6bcf | 142 | #undef CONFIG_SYS_FLASH_CFI |
281e00a3 | 143 | |
f90aea2a MV |
144 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */ |
145 | #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */ | |
281e00a3 | 146 | |
6d0f6bcf | 147 | #define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE |
281e00a3 WD |
148 | |
149 | /* | |
150 | * This is setting for JFFS2 support in u-boot. | |
151 | * Right now there is no gain for user, but later on booting kernel might be | |
152 | * possible. Consider using XIP kernel running from flash to save RAM | |
153 | * footprint. | |
079a136c | 154 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. |
281e00a3 | 155 | */ |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
157 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 5 | |
158 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
281e00a3 WD |
159 | |
160 | /* | |
161 | * Environment setup. Definitions of monitor location and size with | |
162 | * definition of environment setup ends up in 2 possibilities. | |
163 | * 1. Embeded environment - in u-boot code is space for environment | |
164 | * 2. Environment is read from predefined sector of flash | |
165 | * Right now we support 2. possiblity, but expecting no env placed | |
166 | * on mentioned address right now. This also needs to provide whole | |
167 | * sector for it - for us 256Kb is really waste of memory. U-boot uses | |
168 | * default env. and until kernel parameters could be sent to kernel | |
169 | * env. has no sense to us. | |
170 | */ | |
171 | ||
172 | /* Setup for PA23 which is Reset Default PA23 but has to become | |
173 | CS5 */ | |
174 | ||
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_GPR_A_VAL 0x00800000 |
176 | #define CONFIG_SYS_GIUS_A_VAL 0x0043fffe | |
281e00a3 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_MONITOR_BASE 0x10000000 |
179 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ | |
5a1aceb0 | 180 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
181 | #define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ |
182 | #define CONFIG_ENV_SIZE 0x20000 | |
281e00a3 WD |
183 | |
184 | #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ | |
185 | ||
186 | /* | |
187 | * CSxU_VAL: | |
188 | * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 | |
189 | * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | | |
190 | * | |
191 | * CSxL_VAL: | |
192 | * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 | |
193 | * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| | |
194 | */ | |
195 | ||
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_CS0U_VAL 0x000F2000 |
197 | #define CONFIG_SYS_CS0L_VAL 0x11110d01 | |
198 | #define CONFIG_SYS_CS1U_VAL 0x000F0a00 | |
199 | #define CONFIG_SYS_CS1L_VAL 0x11110601 | |
200 | #define CONFIG_SYS_CS2U_VAL 0x0 | |
201 | #define CONFIG_SYS_CS2L_VAL 0x0 | |
281e00a3 | 202 | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_CS3U_VAL 0x000FFFFF |
204 | #define CONFIG_SYS_CS3L_VAL 0x00000303 | |
281e00a3 | 205 | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_CS4U_VAL 0x000F0a00 |
207 | #define CONFIG_SYS_CS4L_VAL 0x11110301 | |
281e00a3 WD |
208 | |
209 | /* CNC == 3 too long | |
6d0f6bcf | 210 | #define CONFIG_SYS_CS5U_VAL 0x0000C210 */ |
281e00a3 | 211 | |
6d0f6bcf | 212 | /* #define CONFIG_SYS_CS5U_VAL 0x00008400 |
281e00a3 WD |
213 | mal laenger mahcen, ob der bei 150MHz laenger haelt dann und |
214 | kaum langsamer ist */ | |
6d0f6bcf JCPV |
215 | /* #define CONFIG_SYS_CS5U_VAL 0x00009400 |
216 | #define CONFIG_SYS_CS5L_VAL 0x11010D03 */ | |
281e00a3 | 217 | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_CS5U_VAL 0x00008400 |
219 | #define CONFIG_SYS_CS5L_VAL 0x00000D03 | |
281e00a3 | 220 | |
281e00a3 WD |
221 | #define CONFIG_DRIVER_DM9000 1 |
222 | #define CONFIG_DM9000_BASE 0x16000000 | |
223 | #define DM9000_IO CONFIG_DM9000_BASE | |
224 | #define DM9000_DATA (CONFIG_DM9000_BASE+4) | |
281e00a3 WD |
225 | |
226 | /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) | |
227 | f_ref=16,777MHz | |
228 | ||
229 | 0x002a141f: 191,9944MHz | |
230 | 0x040b2007: 144MHz | |
231 | 0x042a141f: 96MHz | |
232 | 0x0811140d: 64MHz | |
233 | 0x040e200e: 150MHz | |
234 | 0x00321431: 200MHz | |
235 | ||
236 | 0x08001800: 64MHz mit 16er Quarz | |
237 | 0x04001800: 96MHz mit 16er Quarz | |
238 | 0x04002400: 144MHz mit 16er Quarz | |
239 | ||
240 | 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 | |
241 | |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ | |
242 | ||
243 | #define CPU200 | |
244 | ||
245 | #ifdef CPU200 | |
6d0f6bcf | 246 | #define CONFIG_SYS_MPCTL0_VAL 0x00321431 |
281e00a3 | 247 | #else |
6d0f6bcf | 248 | #define CONFIG_SYS_MPCTL0_VAL 0x040e200e |
281e00a3 WD |
249 | #endif |
250 | ||
251 | /* #define BUS64 */ | |
252 | #define BUS72 | |
253 | ||
254 | #ifdef BUS72 | |
6d0f6bcf | 255 | #define CONFIG_SYS_SPCTL0_VAL 0x04002400 |
281e00a3 WD |
256 | #endif |
257 | ||
258 | #ifdef BUS96 | |
6d0f6bcf | 259 | #define CONFIG_SYS_SPCTL0_VAL 0x04001800 |
281e00a3 WD |
260 | #endif |
261 | ||
262 | #ifdef BUS64 | |
6d0f6bcf | 263 | #define CONFIG_SYS_SPCTL0_VAL 0x08001800 |
281e00a3 WD |
264 | #endif |
265 | ||
266 | /* Das ist der BCLK Divider, der aus der System PLL | |
267 | BCLK und HCLK erzeugt: | |
268 | 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 | |
269 | 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 | |
270 | 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 | |
271 | 0x2f001003 : 192MHz/5=38,4MHz | |
272 | 0x2f000003 : 64MHz/1 | |
273 | Bit 22: SPLL Restart | |
274 | Bit 21: MPLL Restart */ | |
275 | ||
276 | #ifdef BUS64 | |
6d0f6bcf | 277 | #define CONFIG_SYS_CSCR_VAL 0x2f030003 |
281e00a3 WD |
278 | #endif |
279 | ||
280 | #ifdef BUS72 | |
6d0f6bcf | 281 | #define CONFIG_SYS_CSCR_VAL 0x2f030403 |
281e00a3 WD |
282 | #endif |
283 | ||
284 | /* | |
285 | * Well this has to be defined, but on the other hand it is used differently | |
286 | * one may expect. For instance loadb command do not cares :-) | |
287 | * So advice is - do not relay on this... | |
288 | */ | |
6d0f6bcf | 289 | #define CONFIG_SYS_LOAD_ADDR 0x08400000 |
281e00a3 WD |
290 | |
291 | #define MHZ16QUARZINUSE | |
292 | ||
293 | #ifdef MHZ16QUARZINUSE | |
294 | #define CONFIG_SYSPLL_CLK_FREQ 16000000 | |
295 | #else | |
296 | #define CONFIG_SYSPLL_CLK_FREQ 16780000 | |
297 | #endif | |
298 | ||
299 | #define CONFIG_SYS_CLK_FREQ 16780000 | |
300 | ||
301 | /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ | |
6d0f6bcf | 302 | #define CONFIG_SYS_FMCR_VAL 0x00000001 |
281e00a3 WD |
303 | |
304 | /* Bit[0:3] contain PERCLK1DIV for UART 1 | |
305 | 0x000b00b ->b<- -> 192MHz/12=16MHz | |
306 | 0x000b00b ->8<- -> 144MHz/09=16MHz | |
307 | 0x000b00b ->3<- -> 64MHz/4=16MHz */ | |
308 | ||
309 | #ifdef BUS96 | |
6d0f6bcf | 310 | #define CONFIG_SYS_PCDR_VAL 0x000b00b5 |
281e00a3 WD |
311 | #endif |
312 | ||
313 | #ifdef BUS64 | |
6d0f6bcf | 314 | #define CONFIG_SYS_PCDR_VAL 0x000b00b3 |
281e00a3 WD |
315 | #endif |
316 | ||
317 | #ifdef BUS72 | |
6d0f6bcf | 318 | #define CONFIG_SYS_PCDR_VAL 0x000b00b8 |
281e00a3 WD |
319 | #endif |
320 | ||
321 | #endif /* __CONFIG_H */ |