[people/ms/u-boot.git] / include / configs / sh7752evb.h

/*
 * Configuation settings for the sh7752evb board
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __SH7752EVB_H
#define __SH7752EVB_H

#define CONFIG_CPU_SH7752	1
#define CONFIG_SH7752EVB	1

#define CONFIG_SYS_TEXT_BASE	0x5ff80000

#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
#define CONFIG_DOS_PARTITION

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"

#define CONFIG_DISPLAY_BOARDINFO
#undef	CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/* MEMORY */
#define SH7752EVB_SDRAM_BASE		(0x40000000)
#define SH7752EVB_SDRAM_SIZE		(512 * 1024 * 1024)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF2	1

#define CONFIG_SYS_MEMTEST_START	(SH7752EVB_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					 480 * 1024 * 1024)
#undef	CONFIG_SYS_ALT_MEMTEST
#undef	CONFIG_SYS_MEMTEST_SCRATCH
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE		(SH7752EVB_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE		(SH7752EVB_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
					 128 * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_SYS_NO_FLASH

/* Ether */
#define CONFIG_SH_ETHER			1
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
#define CONFIG_SH_ETHER_USE_GETHER	1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
#define CONFIG_PHY_VITESSE

#define SH7752EVB_ETHERNET_MAC_BASE_SPI	0x00090000
#define SH7752EVB_SPI_SECTOR_SIZE	(64 * 1024)
#define SH7752EVB_ETHERNET_MAC_BASE	SH7752EVB_ETHERNET_MAC_BASE_SPI
#define SH7752EVB_ETHERNET_MAC_SIZE	17
#define SH7752EVB_ETHERNET_NUM_CH	2

/* SPI */
#define CONFIG_SH_SPI			1
#define CONFIG_SH_SPI_BASE		0xfe002000

/* MMCIF */
#define CONFIG_GENERIC_MMC		1
#define CONFIG_SH_MMCIF			1
#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
#define CONFIG_SH_MMCIF_CLK		48000000

/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_ADDR		(0x00080000)
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS				\
		"netboot=bootp; bootm\0"

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	48000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV	4
#endif	/* __SH7752EVB_H */
Commit	Line	Data
1a2621ba YS	1	/*
	2	* Configuation settings for the sh7752evb board
	3	*
	4	* Copyright (C) 2012 Renesas Solutions Corp.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
1a2621ba YS	7	*/
	8
	9	#ifndef __SH7752EVB_H
	10	#define __SH7752EVB_H
	11
1a2621ba YS	12	#define CONFIG_CPU_SH7752 1
	13	#define CONFIG_SH7752EVB 1
	14
	15	#define CONFIG_SYS_TEXT_BASE 0x5ff80000
1a2621ba	16
1a2621ba YS	17	#define CONFIG_CMD_DFL
1a2621ba YS	18	#define CONFIG_CMD_SDRAM
1a2621ba YS	19	#define CONFIG_CMD_MD5SUM
1a2621ba YS	20	#define CONFIG_MD5
1a2621ba	21	#define CONFIG_DOS_PARTITION
1a2621ba YS	22
1a2621ba YS	23	#define CONFIG_BAUDRATE 115200
1a2621ba YS	24	#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
1a2621ba YS	25
18a40e84	26	#define CONFIG_DISPLAY_BOARDINFO
1a2621ba YS	27	#undef CONFIG_SHOW_BOOT_PROGRESS
	28	#define CONFIG_CMDLINE_EDITING
	29	#define CONFIG_AUTO_COMPLETE
	30
	31	/* MEMORY */
	32	#define SH7752EVB_SDRAM_BASE (0x40000000)
	33	#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024)
	34
	35	#define CONFIG_SYS_LONGHELP
1a2621ba YS	36	#define CONFIG_SYS_CBSIZE 256
	37	#define CONFIG_SYS_PBSIZE 256
	38	#define CONFIG_SYS_MAXARGS 16
	39	#define CONFIG_SYS_BARGSIZE 512
	40	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	41
	42	/* SCIF */
	43	#define CONFIG_SCIF_CONSOLE 1
	44	#define CONFIG_CONS_SCIF2 1
1a2621ba YS	45
	46	#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)
	47	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	48	480 * 1024 * 1024)
	49	#undef CONFIG_SYS_ALT_MEMTEST
	50	#undef CONFIG_SYS_MEMTEST_SCRATCH
	51	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	52
	53	#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE)
	54	#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE)
	55	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
	56	128 * 1024 * 1024)
	57
	58	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	59	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	60	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	61	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	62
	63	/* FLASH */
	64	#define CONFIG_SYS_NO_FLASH
	65
	66	/* Ether */
	67	#define CONFIG_SH_ETHER 1
	68	#define CONFIG_SH_ETHER_USE_PORT 0
	69	#define CONFIG_SH_ETHER_PHY_ADDR 18
	70	#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
	71	#define CONFIG_SH_ETHER_USE_GETHER 1
	72	#define CONFIG_PHYLIB
	73	#define CONFIG_BITBANGMII
	74	#define CONFIG_BITBANGMII_MULTI
	75	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
	76	#define CONFIG_PHY_VITESSE
	77
	78	#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
	79	#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)
	80	#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI
	81	#define SH7752EVB_ETHERNET_MAC_SIZE 17
	82	#define SH7752EVB_ETHERNET_NUM_CH 2
1a2621ba YS	83
	84	/* SPI */
	85	#define CONFIG_SH_SPI 1
	86	#define CONFIG_SH_SPI_BASE 0xfe002000
1a2621ba YS	87
1a2621ba YS	88	/* MMCIF */
1a2621ba YS	89	#define CONFIG_GENERIC_MMC 1
	90	#define CONFIG_SH_MMCIF 1
	91	#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
	92	#define CONFIG_SH_MMCIF_CLK 48000000
	93
	94	/* ENV setting */
	95	#define CONFIG_ENV_IS_EMBEDDED
	96	#define CONFIG_ENV_IS_IN_SPI_FLASH
	97	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	98	#define CONFIG_ENV_ADDR (0x00080000)
	99	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
	100	#define CONFIG_ENV_OVERWRITE 1
	101	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	102	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	103	#define CONFIG_EXTRA_ENV_SETTINGS \
	104	"netboot=bootp; bootm\0"
	105
	106	/* Board Clock */
	107	#define CONFIG_SYS_CLK_FREQ 48000000
684a501e NI	108	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	109	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
1a2621ba	110	#define CONFIG_SYS_TMU_CLK_DIV 4
1a2621ba	111	#endif /* __SH7752EVB_H */